hw/irdma/icrdma_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
0002 /* Copyright (c) 2017 - 2021 Intel Corporation */
0003 #ifndef ICRDMA_HW_H
0004 #define ICRDMA_HW_H
0005
0006 #include "irdma.h"
0007
0008 #define VFPE_CQPTAIL1       0x0000a000
0009 #define VFPE_CQPDB1     0x0000bc00
0010 #define VFPE_CCQPSTATUS1    0x0000b800
0011 #define VFPE_CCQPHIGH1      0x00009800
0012 #define VFPE_CCQPLOW1       0x0000ac00
0013 #define VFPE_CQARM1     0x0000b400
0014 #define VFPE_CQARM1     0x0000b400
0015 #define VFPE_CQACK1     0x0000b000
0016 #define VFPE_AEQALLOC1      0x0000a400
0017 #define VFPE_CQPERRCODES1   0x00009c00
0018 #define VFPE_WQEALLOC1      0x0000c000
0019 #define VFINT_DYN_CTLN(_i)  (0x00003800 + ((_i) * 4)) /* _i=0...63 */
0020
0021 #define PFPE_CQPTAIL        0x00500880
0022 #define PFPE_CQPDB      0x00500800
0023 #define PFPE_CCQPSTATUS     0x0050a000
0024 #define PFPE_CCQPHIGH       0x0050a100
0025 #define PFPE_CCQPLOW        0x0050a080
0026 #define PFPE_CQARM      0x00502c00
0027 #define PFPE_CQACK      0x00502c80
0028 #define PFPE_AEQALLOC       0x00502d00
0029 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */
0030 #define GLPCI_LBARCTRL      0x0009de74
0031 #define GLPE_CPUSTATUS0     0x0050ba5c
0032 #define GLPE_CPUSTATUS1     0x0050ba60
0033 #define GLPE_CPUSTATUS2     0x0050ba64
0034 #define PFINT_AEQCTL        0x0016cb00
0035 #define PFPE_CQPERRCODES    0x0050a200
0036 #define PFPE_WQEALLOC       0x00504400
0037 #define GLINT_CEQCTL(_INT)  (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */
0038 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */
0039 #define PFHMC_PDINV     0x00520300
0040 #define GLHMC_VFPDINV(_i)   (0x00528300 + ((_i) * 4)) /* _i=0...31 */
0041 #define GLPE_CRITERR        0x00534000
0042 #define GLINT_RATE(_INT)    (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
0043
0044 #define ICRDMA_DB_ADDR_OFFSET       (8 * 1024 * 1024 - 64 * 1024)
0045
0046 #define ICRDMA_VF_DB_ADDR_OFFSET    (64 * 1024)
0047
0048 /* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
0049 #define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0
0050 #define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
0051 #define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31
0052 #define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
0053 #define ICRDMA_CQPSQ_STAG_PDID_S 46
0054 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
0055 #define ICRDMA_CQPSQ_CQ_CEQID_S 22
0056 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
0057 #define ICRDMA_CQPSQ_CQ_CQID_S 0
0058 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
0059 #define ICRDMA_COMMIT_FPM_CQCNT_S 0
0060 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
0061
0062 enum icrdma_device_caps_const {
0063     ICRDMA_MAX_STATS_COUNT = 128,
0064
0065     ICRDMA_MAX_IRD_SIZE         = 127,
0066     ICRDMA_MAX_ORD_SIZE         = 255,
0067
0068 };
0069
0070 void icrdma_init_hw(struct irdma_sc_dev *dev);
0071 #endif /* ICRDMA_HW_H*/