hw/irdma/i40iw_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
0002 /* Copyright (c) 2015 - 2021 Intel Corporation */
0003 #ifndef I40IW_HW_H
0004 #define I40IW_HW_H
0005 #define I40E_VFPE_CQPTAIL1            0x0000A000 /* Reset: VFR */
0006 #define I40E_VFPE_CQPDB1              0x0000BC00 /* Reset: VFR */
0007 #define I40E_VFPE_CCQPSTATUS1         0x0000B800 /* Reset: VFR */
0008 #define I40E_VFPE_CCQPHIGH1           0x00009800 /* Reset: VFR */
0009 #define I40E_VFPE_CCQPLOW1            0x0000AC00 /* Reset: VFR */
0010 #define I40E_VFPE_CQARM1              0x0000B400 /* Reset: VFR */
0011 #define I40E_VFPE_CQACK1              0x0000B000 /* Reset: VFR */
0012 #define I40E_VFPE_AEQALLOC1           0x0000A400 /* Reset: VFR */
0013 #define I40E_VFPE_CQPERRCODES1        0x00009C00 /* Reset: VFR */
0014 #define I40E_VFPE_WQEALLOC1           0x0000C000 /* Reset: VFR */
0015 #define I40E_VFINT_DYN_CTLN(_INTVF)   (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
0016
0017 #define I40E_PFPE_CQPTAIL             0x00008080 /* Reset: PFR */
0018
0019 #define I40E_PFPE_CQPDB               0x00008000 /* Reset: PFR */
0020 #define I40E_PFPE_CCQPSTATUS          0x00008100 /* Reset: PFR */
0021 #define I40E_PFPE_CCQPHIGH            0x00008200 /* Reset: PFR */
0022 #define I40E_PFPE_CCQPLOW             0x00008180 /* Reset: PFR */
0023 #define I40E_PFPE_CQARM               0x00131080 /* Reset: PFR */
0024 #define I40E_PFPE_CQACK               0x00131100 /* Reset: PFR */
0025 #define I40E_PFPE_AEQALLOC            0x00131180 /* Reset: PFR */
0026 #define I40E_PFPE_CQPERRCODES         0x00008880 /* Reset: PFR */
0027 #define I40E_PFPE_WQEALLOC            0x00138C00 /* Reset: PFR */
0028 #define I40E_GLPCI_LBARCTRL           0x000BE484 /* Reset: POR */
0029 #define I40E_GLPE_CPUSTATUS0          0x0000D040 /* Reset: PE_CORER */
0030 #define I40E_GLPE_CPUSTATUS1          0x0000D044 /* Reset: PE_CORER */
0031 #define I40E_GLPE_CPUSTATUS2          0x0000D048 /* Reset: PE_CORER */
0032 #define I40E_GLPE_CRITERR             0x000B4000 /* Reset: PE_CORER */
0033 #define I40E_PFHMC_PDINV              0x000C0300 /* Reset: PFR */
0034 #define I40E_GLHMC_VFPDINV(_i)        (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
0035 #define I40E_PFINT_DYN_CTLN(_INTPF)   (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */    /* Reset: PFR */
0036 #define I40E_PFINT_AEQCTL             0x00038700 /* Reset: CORER */
0037
0038 #define I40E_GLPES_PFIP4RXDISCARD(_i)            (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0039 #define I40E_GLPES_PFIP4RXTRUNC(_i)              (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0040 #define I40E_GLPES_PFIP4TXNOROUTE(_i)            (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0041 #define I40E_GLPES_PFIP6RXDISCARD(_i)            (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0042 #define I40E_GLPES_PFIP6RXTRUNC(_i)              (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0043
0044 #define I40E_GLPES_PFRDMAVBNDLO(_i)              (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0045 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i)           (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0046 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i)           (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0047 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i)           (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0048 #define I40E_GLPES_PFUDPRXPKTSLO(_i)             (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0049 #define I40E_GLPES_PFUDPTXPKTSLO(_i)             (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0050
0051 #define I40E_GLPES_PFIP6TXNOROUTE(_i)            (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0052 #define I40E_GLPES_PFTCPRTXSEG(_i)               (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0053 #define I40E_GLPES_PFTCPRXOPTERR(_i)             (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0054 #define I40E_GLPES_PFTCPRXPROTOERR(_i)           (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0055 #define I40E_GLPES_PFRXVLANERR(_i)               (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
0056 #define I40E_GLPES_PFIP4RXOCTSLO(_i)             (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0057 #define I40E_GLPES_PFIP4RXPKTSLO(_i)             (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0058 #define I40E_GLPES_PFIP4RXFRAGSLO(_i)            (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0059 #define I40E_GLPES_PFIP4RXMCPKTSLO(_i)           (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0060 #define I40E_GLPES_PFIP4TXOCTSLO(_i)             (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0061 #define I40E_GLPES_PFIP4TXPKTSLO(_i)             (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0062 #define I40E_GLPES_PFIP4TXFRAGSLO(_i)            (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0063 #define I40E_GLPES_PFIP4TXMCPKTSLO(_i)           (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0064 #define I40E_GLPES_PFIP6RXOCTSLO(_i)             (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0065 #define I40E_GLPES_PFIP6RXPKTSLO(_i)             (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0066 #define I40E_GLPES_PFIP6RXFRAGSLO(_i)            (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0067 #define I40E_GLPES_PFIP6TXOCTSLO(_i)             (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0068 #define I40E_GLPES_PFIP6TXPKTSLO(_i)             (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0069 #define I40E_GLPES_PFIP6TXFRAGSLO(_i)            (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0070 #define I40E_GLPES_PFIP6TXMCPKTSLO(_i)           (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0071 #define I40E_GLPES_PFTCPTXSEGLO(_i)              (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0072 #define I40E_GLPES_PFRDMARXRDSLO(_i)             (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0073 #define I40E_GLPES_PFRDMARXSNDSLO(_i)            (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0074 #define I40E_GLPES_PFRDMARXWRSLO(_i)             (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0075 #define I40E_GLPES_PFRDMATXRDSLO(_i)             (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0076 #define I40E_GLPES_PFRDMATXSNDSLO(_i)            (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0077 #define I40E_GLPES_PFRDMATXWRSLO(_i)             (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0078 #define I40E_GLPES_PFIP4RXMCOCTSLO(_i)           (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0079 #define I40E_GLPES_PFIP6RXMCPKTSLO(_i)           (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0080 #define I40E_GLPES_PFTCPRXSEGSLO(_i)             (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0081 #define I40E_GLPES_PFRDMAVINVLO(_i)              (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
0082
0083 #define I40IW_DB_ADDR_OFFSET    (4 * 1024 * 1024 - 64 * 1024)
0084
0085 #define I40IW_VF_DB_ADDR_OFFSET (64 * 1024)
0086
0087 #define I40E_PFINT_LNKLSTN(_INTPF)           (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
0088 #define I40E_PFINT_LNKLSTN_MAX_INDEX         511
0089 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX GENMASK(10, 0)
0090 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE GENMASK(12, 11)
0091
0092 #define I40E_PFINT_CEQCTL(_INTPF)          (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
0093 #define I40E_PFINT_CEQCTL_MAX_INDEX        511
0094
0095 /* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
0096 #define I40E_PFINT_CEQCTL_MSIX_INDX_S 0
0097 #define I40E_PFINT_CEQCTL_MSIX_INDX GENMASK(7, 0)
0098 #define I40E_PFINT_CEQCTL_ITR_INDX_S 11
0099 #define I40E_PFINT_CEQCTL_ITR_INDX GENMASK(12, 11)
0100 #define I40E_PFINT_CEQCTL_MSIX0_INDX_S 13
0101 #define I40E_PFINT_CEQCTL_MSIX0_INDX GENMASK(15, 13)
0102 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_S 16
0103 #define I40E_PFINT_CEQCTL_NEXTQ_INDX GENMASK(26, 16)
0104 #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_S 27
0105 #define I40E_PFINT_CEQCTL_NEXTQ_TYPE GENMASK(28, 27)
0106 #define I40E_PFINT_CEQCTL_CAUSE_ENA_S 30
0107 #define I40E_PFINT_CEQCTL_CAUSE_ENA BIT(30)
0108 #define I40E_PFINT_CEQCTL_INTEVENT_S 31
0109 #define I40E_PFINT_CEQCTL_INTEVENT BIT(31)
0110 #define I40E_CQPSQ_STAG_PDID_S 48
0111 #define I40E_CQPSQ_STAG_PDID GENMASK_ULL(62, 48)
0112 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_S 0
0113 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
0114 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_S 31
0115 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
0116 #define I40E_PFINT_DYN_CTLN_ITR_INDX_S 3
0117 #define I40E_PFINT_DYN_CTLN_ITR_INDX GENMASK(4, 3)
0118 #define I40E_PFINT_DYN_CTLN_INTENA_S 0
0119 #define I40E_PFINT_DYN_CTLN_INTENA BIT(0)
0120 #define I40E_CQPSQ_CQ_CEQID_S 24
0121 #define I40E_CQPSQ_CQ_CEQID GENMASK(30, 24)
0122 #define I40E_CQPSQ_CQ_CQID_S 0
0123 #define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)
0124 #define I40E_COMMIT_FPM_CQCNT_S 0
0125 #define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)
0126
0127 #define I40E_VSIQF_CTL(_VSI)             (0x0020D800 + ((_VSI) * 4))
0128
0129 enum i40iw_device_caps_const {
0130     I40IW_MAX_WQ_FRAGMENT_COUNT     = 3,
0131     I40IW_MAX_SGE_RD            = 1,
0132     I40IW_MAX_PUSH_PAGE_COUNT       = 0,
0133     I40IW_MAX_INLINE_DATA_SIZE      = 48,
0134     I40IW_MAX_IRD_SIZE          = 63,
0135     I40IW_MAX_ORD_SIZE          = 127,
0136     I40IW_MAX_WQ_ENTRIES            = 2048,
0137     I40IW_MAX_WQE_SIZE_RQ           = 128,
0138     I40IW_MAX_PDS               = 32768,
0139     I40IW_MAX_STATS_COUNT           = 16,
0140     I40IW_MAX_CQ_SIZE           = 1048575,
0141     I40IW_MAX_OUTBOUND_MSG_SIZE     = 2147483647,
0142     I40IW_MAX_INBOUND_MSG_SIZE      = 2147483647,
0143 };
0144
0145 #define I40IW_QP_WQE_MIN_SIZE   32
0146 #define I40IW_QP_WQE_MAX_SIZE   128
0147 #define I40IW_QP_SW_MIN_WQSIZE  4
0148 #define I40IW_MAX_RQ_WQE_SHIFT  2
0149 #define I40IW_MAX_QUANTA_PER_WR 2
0150
0151 #define I40IW_QP_SW_MAX_SQ_QUANTA 2048
0152 #define I40IW_QP_SW_MAX_RQ_QUANTA 16384
0153 #define I40IW_QP_SW_MAX_WQ_QUANTA 2048
0154 #define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTA - IRDMA_SQ_RSVD) / I40IW_MAX_QUANTA_PER_WR)
0155 #define I40IW_FIRST_VF_FPM_ID 16
0156 #define QUEUE_TYPE_CEQ        2
0157 #define NULL_QUEUE_INDEX      0x7FF
0158
0159 void i40iw_init_hw(struct irdma_sc_dev *dev);
0160 #endif /* I40IW_HW_H */