hw/irdma/i40iw_hw.c

0001 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
0002 /* Copyright (c) 2015 - 2021 Intel Corporation */
0003 #include "osdep.h"
0004 #include "type.h"
0005 #include "i40iw_hw.h"
0006 #include "protos.h"
0007
0008 static u32 i40iw_regs[IRDMA_MAX_REGS] = {
0009     I40E_PFPE_CQPTAIL,
0010     I40E_PFPE_CQPDB,
0011     I40E_PFPE_CCQPSTATUS,
0012     I40E_PFPE_CCQPHIGH,
0013     I40E_PFPE_CCQPLOW,
0014     I40E_PFPE_CQARM,
0015     I40E_PFPE_CQACK,
0016     I40E_PFPE_AEQALLOC,
0017     I40E_PFPE_CQPERRCODES,
0018     I40E_PFPE_WQEALLOC,
0019     I40E_PFINT_DYN_CTLN(0),
0020     I40IW_DB_ADDR_OFFSET,
0021
0022     I40E_GLPCI_LBARCTRL,
0023     I40E_GLPE_CPUSTATUS0,
0024     I40E_GLPE_CPUSTATUS1,
0025     I40E_GLPE_CPUSTATUS2,
0026     I40E_PFINT_AEQCTL,
0027     I40E_PFINT_CEQCTL(0),
0028     I40E_VSIQF_CTL(0),
0029     I40E_PFHMC_PDINV,
0030     I40E_GLHMC_VFPDINV(0),
0031     I40E_GLPE_CRITERR,
0032     0xffffffff      /* PFINT_RATEN not used in FPK */
0033 };
0034
0035 static u32 i40iw_stat_offsets_32[IRDMA_HW_STAT_INDEX_MAX_32] = {
0036     I40E_GLPES_PFIP4RXDISCARD(0),
0037     I40E_GLPES_PFIP4RXTRUNC(0),
0038     I40E_GLPES_PFIP4TXNOROUTE(0),
0039     I40E_GLPES_PFIP6RXDISCARD(0),
0040     I40E_GLPES_PFIP6RXTRUNC(0),
0041     I40E_GLPES_PFIP6TXNOROUTE(0),
0042     I40E_GLPES_PFTCPRTXSEG(0),
0043     I40E_GLPES_PFTCPRXOPTERR(0),
0044     I40E_GLPES_PFTCPRXPROTOERR(0),
0045     I40E_GLPES_PFRXVLANERR(0)
0046 };
0047
0048 static u32 i40iw_stat_offsets_64[IRDMA_HW_STAT_INDEX_MAX_64] = {
0049     I40E_GLPES_PFIP4RXOCTSLO(0),
0050     I40E_GLPES_PFIP4RXPKTSLO(0),
0051     I40E_GLPES_PFIP4RXFRAGSLO(0),
0052     I40E_GLPES_PFIP4RXMCPKTSLO(0),
0053     I40E_GLPES_PFIP4TXOCTSLO(0),
0054     I40E_GLPES_PFIP4TXPKTSLO(0),
0055     I40E_GLPES_PFIP4TXFRAGSLO(0),
0056     I40E_GLPES_PFIP4TXMCPKTSLO(0),
0057     I40E_GLPES_PFIP6RXOCTSLO(0),
0058     I40E_GLPES_PFIP6RXPKTSLO(0),
0059     I40E_GLPES_PFIP6RXFRAGSLO(0),
0060     I40E_GLPES_PFIP6RXMCPKTSLO(0),
0061     I40E_GLPES_PFIP6TXOCTSLO(0),
0062     I40E_GLPES_PFIP6TXPKTSLO(0),
0063     I40E_GLPES_PFIP6TXFRAGSLO(0),
0064     I40E_GLPES_PFIP6TXMCPKTSLO(0),
0065     I40E_GLPES_PFTCPRXSEGSLO(0),
0066     I40E_GLPES_PFTCPTXSEGLO(0),
0067     I40E_GLPES_PFRDMARXRDSLO(0),
0068     I40E_GLPES_PFRDMARXSNDSLO(0),
0069     I40E_GLPES_PFRDMARXWRSLO(0),
0070     I40E_GLPES_PFRDMATXRDSLO(0),
0071     I40E_GLPES_PFRDMATXSNDSLO(0),
0072     I40E_GLPES_PFRDMATXWRSLO(0),
0073     I40E_GLPES_PFRDMAVBNDLO(0),
0074     I40E_GLPES_PFRDMAVINVLO(0),
0075     I40E_GLPES_PFIP4RXMCOCTSLO(0),
0076     I40E_GLPES_PFIP4TXMCOCTSLO(0),
0077     I40E_GLPES_PFIP6RXMCOCTSLO(0),
0078     I40E_GLPES_PFIP6TXMCOCTSLO(0),
0079     I40E_GLPES_PFUDPRXPKTSLO(0),
0080     I40E_GLPES_PFUDPTXPKTSLO(0)
0081 };
0082
0083 static u64 i40iw_masks[IRDMA_MAX_MASKS] = {
0084     I40E_PFPE_CCQPSTATUS_CCQP_DONE,
0085     I40E_PFPE_CCQPSTATUS_CCQP_ERR,
0086     I40E_CQPSQ_STAG_PDID,
0087     I40E_CQPSQ_CQ_CEQID,
0088     I40E_CQPSQ_CQ_CQID,
0089     I40E_COMMIT_FPM_CQCNT,
0090 };
0091
0092 static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = {
0093     I40E_PFPE_CCQPSTATUS_CCQP_DONE_S,
0094     I40E_PFPE_CCQPSTATUS_CCQP_ERR_S,
0095     I40E_CQPSQ_STAG_PDID_S,
0096     I40E_CQPSQ_CQ_CEQID_S,
0097     I40E_CQPSQ_CQ_CQID_S,
0098     I40E_COMMIT_FPM_CQCNT_S,
0099 };
0100
0101 /**
0102  * i40iw_config_ceq- Configure CEQ interrupt
0103  * @dev: pointer to the device structure
0104  * @ceq_id: Completion Event Queue ID
0105  * @idx: vector index
0106  * @enable: Enable CEQ interrupt when true
0107  */
0108 static void i40iw_config_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
0109                  bool enable)
0110 {
0111     u32 reg_val;
0112
0113     reg_val = FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_INDX, ceq_id) |
0114           FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_TYPE, QUEUE_TYPE_CEQ);
0115     wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val);
0116
0117     reg_val = FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX, 0x3) |
0118           FIELD_PREP(I40E_PFINT_DYN_CTLN_INTENA, 0x1);
0119     wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val);
0120
0121     reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |
0122           FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) |
0123           FIELD_PREP(I40E_PFINT_CEQCTL_NEXTQ_INDX, NULL_QUEUE_INDEX) |
0124           FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, 0x3);
0125
0126     wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val);
0127 }
0128
0129 /**
0130  * i40iw_ena_irq - Enable interrupt
0131  * @dev: pointer to the device structure
0132  * @idx: vector index
0133  */
0134 static void i40iw_ena_irq(struct irdma_sc_dev *dev, u32 idx)
0135 {
0136     u32 val;
0137
0138     val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 0x1) |
0139           FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 0x1) |
0140           FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, 0x3);
0141     wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), val);
0142 }
0143
0144 /**
0145  * i40iw_disable_irq - Disable interrupt
0146  * @dev: pointer to the device structure
0147  * @idx: vector index
0148  */
0149 static void i40iw_disable_irq(struct irdma_sc_dev *dev, u32 idx)
0150 {
0151     wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), 0);
0152 }
0153
0154 static const struct irdma_irq_ops i40iw_irq_ops = {
0155     .irdma_cfg_aeq = irdma_cfg_aeq,
0156     .irdma_cfg_ceq = i40iw_config_ceq,
0157     .irdma_dis_irq = i40iw_disable_irq,
0158     .irdma_en_irq = i40iw_ena_irq,
0159 };
0160
0161 void i40iw_init_hw(struct irdma_sc_dev *dev)
0162 {
0163     int i;
0164     u8 __iomem *hw_addr;
0165
0166     for (i = 0; i < IRDMA_MAX_REGS; ++i) {
0167         hw_addr = dev->hw->hw_addr;
0168
0169         if (i == IRDMA_DB_ADDR_OFFSET)
0170             hw_addr = NULL;
0171
0172         dev->hw_regs[i] = (u32 __iomem *)(i40iw_regs[i] + hw_addr);
0173     }
0174
0175     for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_32; ++i)
0176         dev->hw_stats_regs_32[i] = i40iw_stat_offsets_32[i];
0177
0178     for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_64; ++i)
0179         dev->hw_stats_regs_64[i] = i40iw_stat_offsets_64[i];
0180
0181     dev->hw_attrs.first_hw_vf_fpm_id = I40IW_FIRST_VF_FPM_ID;
0182     dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
0183
0184     for (i = 0; i < IRDMA_MAX_SHIFTS; ++i)
0185         dev->hw_shifts[i] = i40iw_shifts[i];
0186
0187     for (i = 0; i < IRDMA_MAX_MASKS; ++i)
0188         dev->hw_masks[i] = i40iw_masks[i];
0189
0190     dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
0191     dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
0192     dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
0193     dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
0194     dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
0195     dev->ceq_itr_mask_db = NULL;
0196     dev->aeq_itr_mask_db = NULL;
0197     dev->irq_ops = &i40iw_irq_ops;
0198
0199     /* Setup the hardware limits, hmc may limit further */
0200     dev->hw_attrs.uk_attrs.max_hw_wq_frags = I40IW_MAX_WQ_FRAGMENT_COUNT;
0201     dev->hw_attrs.uk_attrs.max_hw_read_sges = I40IW_MAX_SGE_RD;
0202     dev->hw_attrs.max_hw_device_pages = I40IW_MAX_PUSH_PAGE_COUNT;
0203     dev->hw_attrs.uk_attrs.max_hw_inline = I40IW_MAX_INLINE_DATA_SIZE;
0204     dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M;
0205     dev->hw_attrs.max_hw_ird = I40IW_MAX_IRD_SIZE;
0206     dev->hw_attrs.max_hw_ord = I40IW_MAX_ORD_SIZE;
0207     dev->hw_attrs.max_hw_wqes = I40IW_MAX_WQ_ENTRIES;
0208     dev->hw_attrs.uk_attrs.max_hw_rq_quanta = I40IW_QP_SW_MAX_RQ_QUANTA;
0209     dev->hw_attrs.uk_attrs.max_hw_wq_quanta = I40IW_QP_SW_MAX_WQ_QUANTA;
0210     dev->hw_attrs.uk_attrs.max_hw_sq_chunk = I40IW_MAX_QUANTA_PER_WR;
0211     dev->hw_attrs.max_hw_pds = I40IW_MAX_PDS;
0212     dev->hw_attrs.max_stat_inst = I40IW_MAX_STATS_COUNT;
0213     dev->hw_attrs.max_hw_outbound_msg_size = I40IW_MAX_OUTBOUND_MSG_SIZE;
0214     dev->hw_attrs.max_hw_inbound_msg_size = I40IW_MAX_INBOUND_MSG_SIZE;
0215     dev->hw_attrs.max_qp_wr = I40IW_MAX_QP_WRS;
0216 }