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0001 /*
0002  * Copyright (c) 2016 Hisilicon Limited.
0003  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
0004  *
0005  * This software is available to you under a choice of one of two
0006  * licenses.  You may choose to be licensed under the terms of the GNU
0007  * General Public License (GPL) Version 2, available from the file
0008  * COPYING in the main directory of this source tree, or the
0009  * OpenIB.org BSD license below:
0010  *
0011  *     Redistribution and use in source and binary forms, with or
0012  *     without modification, are permitted provided that the following
0013  *     conditions are met:
0014  *
0015  *      - Redistributions of source code must retain the above
0016  *        copyright notice, this list of conditions and the following
0017  *        disclaimer.
0018  *
0019  *      - Redistributions in binary form must reproduce the above
0020  *        copyright notice, this list of conditions and the following
0021  *        disclaimer in the documentation and/or other materials
0022  *        provided with the distribution.
0023  *
0024  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0025  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0026  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0027  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0028  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0029  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0030  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0031  * SOFTWARE.
0032  */
0033 #include <linux/acpi.h>
0034 #include <linux/module.h>
0035 #include <linux/pci.h>
0036 #include <rdma/ib_addr.h>
0037 #include <rdma/ib_smi.h>
0038 #include <rdma/ib_user_verbs.h>
0039 #include <rdma/ib_cache.h>
0040 #include "hns_roce_common.h"
0041 #include "hns_roce_device.h"
0042 #include "hns_roce_hem.h"
0043 
0044 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
0045                 const u8 *addr)
0046 {
0047     u8 phy_port;
0048     u32 i;
0049 
0050     if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
0051         return 0;
0052 
0053     if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
0054         return 0;
0055 
0056     for (i = 0; i < ETH_ALEN; i++)
0057         hr_dev->dev_addr[port][i] = addr[i];
0058 
0059     phy_port = hr_dev->iboe.phy_port[port];
0060     return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
0061 }
0062 
0063 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
0064 {
0065     struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
0066     u32 port = attr->port_num - 1;
0067     int ret;
0068 
0069     if (port >= hr_dev->caps.num_ports)
0070         return -EINVAL;
0071 
0072     ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
0073 
0074     return ret;
0075 }
0076 
0077 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
0078 {
0079     struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
0080     u32 port = attr->port_num - 1;
0081     int ret;
0082 
0083     if (port >= hr_dev->caps.num_ports)
0084         return -EINVAL;
0085 
0086     ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
0087 
0088     return ret;
0089 }
0090 
0091 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
0092                unsigned long event)
0093 {
0094     struct device *dev = hr_dev->dev;
0095     struct net_device *netdev;
0096     int ret = 0;
0097 
0098     netdev = hr_dev->iboe.netdevs[port];
0099     if (!netdev) {
0100         dev_err(dev, "Can't find netdev on port(%u)!\n", port);
0101         return -ENODEV;
0102     }
0103 
0104     switch (event) {
0105     case NETDEV_UP:
0106     case NETDEV_CHANGE:
0107     case NETDEV_REGISTER:
0108     case NETDEV_CHANGEADDR:
0109         ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
0110         break;
0111     case NETDEV_DOWN:
0112         /*
0113          * In v1 engine, only support all ports closed together.
0114          */
0115         break;
0116     default:
0117         dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
0118         break;
0119     }
0120 
0121     return ret;
0122 }
0123 
0124 static int hns_roce_netdev_event(struct notifier_block *self,
0125                  unsigned long event, void *ptr)
0126 {
0127     struct net_device *dev = netdev_notifier_info_to_dev(ptr);
0128     struct hns_roce_ib_iboe *iboe = NULL;
0129     struct hns_roce_dev *hr_dev = NULL;
0130     int ret;
0131     u32 port;
0132 
0133     hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
0134     iboe = &hr_dev->iboe;
0135 
0136     for (port = 0; port < hr_dev->caps.num_ports; port++) {
0137         if (dev == iboe->netdevs[port]) {
0138             ret = handle_en_event(hr_dev, port, event);
0139             if (ret)
0140                 return NOTIFY_DONE;
0141             break;
0142         }
0143     }
0144 
0145     return NOTIFY_DONE;
0146 }
0147 
0148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
0149 {
0150     int ret;
0151     u8 i;
0152 
0153     for (i = 0; i < hr_dev->caps.num_ports; i++) {
0154         ret = hns_roce_set_mac(hr_dev, i,
0155                        hr_dev->iboe.netdevs[i]->dev_addr);
0156         if (ret)
0157             return ret;
0158     }
0159 
0160     return 0;
0161 }
0162 
0163 static int hns_roce_query_device(struct ib_device *ib_dev,
0164                  struct ib_device_attr *props,
0165                  struct ib_udata *uhw)
0166 {
0167     struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
0168 
0169     memset(props, 0, sizeof(*props));
0170 
0171     props->fw_ver = hr_dev->caps.fw_ver;
0172     props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
0173     props->max_mr_size = (u64)(~(0ULL));
0174     props->page_size_cap = hr_dev->caps.page_size_cap;
0175     props->vendor_id = hr_dev->vendor_id;
0176     props->vendor_part_id = hr_dev->vendor_part_id;
0177     props->hw_ver = hr_dev->hw_rev;
0178     props->max_qp = hr_dev->caps.num_qps;
0179     props->max_qp_wr = hr_dev->caps.max_wqes;
0180     props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
0181                   IB_DEVICE_RC_RNR_NAK_GEN;
0182     props->max_send_sge = hr_dev->caps.max_sq_sg;
0183     props->max_recv_sge = hr_dev->caps.max_rq_sg;
0184     props->max_sge_rd = 1;
0185     props->max_cq = hr_dev->caps.num_cqs;
0186     props->max_cqe = hr_dev->caps.max_cqes;
0187     props->max_mr = hr_dev->caps.num_mtpts;
0188     props->max_pd = hr_dev->caps.num_pds;
0189     props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
0190     props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
0191     props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
0192                 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
0193     props->max_pkeys = 1;
0194     props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
0195     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
0196         props->max_srq = hr_dev->caps.num_srqs;
0197         props->max_srq_wr = hr_dev->caps.max_srq_wrs;
0198         props->max_srq_sge = hr_dev->caps.max_srq_sges;
0199     }
0200 
0201     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
0202         hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
0203         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
0204         props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
0205     }
0206 
0207     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
0208         props->device_cap_flags |= IB_DEVICE_XRC;
0209 
0210     return 0;
0211 }
0212 
0213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
0214                    struct ib_port_attr *props)
0215 {
0216     struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
0217     struct device *dev = hr_dev->dev;
0218     struct net_device *net_dev;
0219     unsigned long flags;
0220     enum ib_mtu mtu;
0221     u32 port;
0222 
0223     port = port_num - 1;
0224 
0225     /* props being zeroed by the caller, avoid zeroing it here */
0226 
0227     props->max_mtu = hr_dev->caps.max_mtu;
0228     props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
0229     props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
0230                 IB_PORT_VENDOR_CLASS_SUP |
0231                 IB_PORT_BOOT_MGMT_SUP;
0232     props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
0233     props->pkey_tbl_len = 1;
0234     props->active_width = IB_WIDTH_4X;
0235     props->active_speed = 1;
0236 
0237     spin_lock_irqsave(&hr_dev->iboe.lock, flags);
0238 
0239     net_dev = hr_dev->iboe.netdevs[port];
0240     if (!net_dev) {
0241         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
0242         dev_err(dev, "Find netdev %u failed!\n", port);
0243         return -EINVAL;
0244     }
0245 
0246     mtu = iboe_get_mtu(net_dev->mtu);
0247     props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
0248     props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
0249                    IB_PORT_ACTIVE :
0250                    IB_PORT_DOWN;
0251     props->phys_state = props->state == IB_PORT_ACTIVE ?
0252                     IB_PORT_PHYS_STATE_LINK_UP :
0253                     IB_PORT_PHYS_STATE_DISABLED;
0254 
0255     spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
0256 
0257     return 0;
0258 }
0259 
0260 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
0261                             u32 port_num)
0262 {
0263     return IB_LINK_LAYER_ETHERNET;
0264 }
0265 
0266 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
0267                    u16 *pkey)
0268 {
0269     if (index > 0)
0270         return -EINVAL;
0271 
0272     *pkey = PKEY_ID;
0273 
0274     return 0;
0275 }
0276 
0277 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
0278                   struct ib_device_modify *props)
0279 {
0280     unsigned long flags;
0281 
0282     if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
0283         return -EOPNOTSUPP;
0284 
0285     if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
0286         spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
0287         memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
0288         spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
0289     }
0290 
0291     return 0;
0292 }
0293 
0294 struct hns_user_mmap_entry *
0295 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
0296                 size_t length,
0297                 enum hns_roce_mmap_type mmap_type)
0298 {
0299     struct hns_user_mmap_entry *entry;
0300     int ret;
0301 
0302     entry = kzalloc(sizeof(*entry), GFP_KERNEL);
0303     if (!entry)
0304         return NULL;
0305 
0306     entry->address = address;
0307     entry->mmap_type = mmap_type;
0308 
0309     switch (mmap_type) {
0310     /* pgoff 0 must be used by DB for compatibility */
0311     case HNS_ROCE_MMAP_TYPE_DB:
0312         ret = rdma_user_mmap_entry_insert_exact(
0313                 ucontext, &entry->rdma_entry, length, 0);
0314         break;
0315     case HNS_ROCE_MMAP_TYPE_DWQE:
0316         ret = rdma_user_mmap_entry_insert_range(
0317                 ucontext, &entry->rdma_entry, length, 1,
0318                 U32_MAX);
0319         break;
0320     default:
0321         ret = -EINVAL;
0322         break;
0323     }
0324 
0325     if (ret) {
0326         kfree(entry);
0327         return NULL;
0328     }
0329 
0330     return entry;
0331 }
0332 
0333 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
0334 {
0335     if (context->db_mmap_entry)
0336         rdma_user_mmap_entry_remove(
0337             &context->db_mmap_entry->rdma_entry);
0338 }
0339 
0340 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
0341 {
0342     struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
0343     u64 address;
0344 
0345     address = context->uar.pfn << PAGE_SHIFT;
0346     context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
0347         uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
0348     if (!context->db_mmap_entry)
0349         return -ENOMEM;
0350 
0351     return 0;
0352 }
0353 
0354 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
0355                    struct ib_udata *udata)
0356 {
0357     int ret;
0358     struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
0359     struct hns_roce_ib_alloc_ucontext_resp resp = {};
0360     struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
0361 
0362     if (!hr_dev->active)
0363         return -EAGAIN;
0364 
0365     resp.qp_tab_size = hr_dev->caps.num_qps;
0366     resp.srq_tab_size = hr_dev->caps.num_srqs;
0367 
0368     ret = hns_roce_uar_alloc(hr_dev, &context->uar);
0369     if (ret)
0370         goto error_fail_uar_alloc;
0371 
0372     ret = hns_roce_alloc_uar_entry(uctx);
0373     if (ret)
0374         goto error_fail_uar_entry;
0375 
0376     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
0377         hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
0378         INIT_LIST_HEAD(&context->page_list);
0379         mutex_init(&context->page_mutex);
0380     }
0381 
0382     resp.cqe_size = hr_dev->caps.cqe_sz;
0383 
0384     ret = ib_copy_to_udata(udata, &resp,
0385                    min(udata->outlen, sizeof(resp)));
0386     if (ret)
0387         goto error_fail_copy_to_udata;
0388 
0389     return 0;
0390 
0391 error_fail_copy_to_udata:
0392     hns_roce_dealloc_uar_entry(context);
0393 
0394 error_fail_uar_entry:
0395     ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
0396 
0397 error_fail_uar_alloc:
0398     return ret;
0399 }
0400 
0401 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
0402 {
0403     struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
0404     struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
0405 
0406     hns_roce_dealloc_uar_entry(context);
0407 
0408     ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
0409 }
0410 
0411 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
0412 {
0413     struct rdma_user_mmap_entry *rdma_entry;
0414     struct hns_user_mmap_entry *entry;
0415     phys_addr_t pfn;
0416     pgprot_t prot;
0417     int ret;
0418 
0419     rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
0420     if (!rdma_entry)
0421         return -EINVAL;
0422 
0423     entry = to_hns_mmap(rdma_entry);
0424     pfn = entry->address >> PAGE_SHIFT;
0425 
0426     switch (entry->mmap_type) {
0427     case HNS_ROCE_MMAP_TYPE_DB:
0428     case HNS_ROCE_MMAP_TYPE_DWQE:
0429         prot = pgprot_device(vma->vm_page_prot);
0430         break;
0431     default:
0432         return -EINVAL;
0433     }
0434 
0435     ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
0436                 prot, rdma_entry);
0437 
0438     rdma_user_mmap_entry_put(rdma_entry);
0439 
0440     return ret;
0441 }
0442 
0443 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
0444 {
0445     struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
0446 
0447     kfree(entry);
0448 }
0449 
0450 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
0451                    struct ib_port_immutable *immutable)
0452 {
0453     struct ib_port_attr attr;
0454     int ret;
0455 
0456     ret = ib_query_port(ib_dev, port_num, &attr);
0457     if (ret)
0458         return ret;
0459 
0460     immutable->pkey_tbl_len = attr.pkey_tbl_len;
0461     immutable->gid_tbl_len = attr.gid_tbl_len;
0462 
0463     immutable->max_mad_size = IB_MGMT_MAD_SIZE;
0464     immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
0465     if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
0466         immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
0467 
0468     return 0;
0469 }
0470 
0471 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
0472 {
0473 }
0474 
0475 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
0476 {
0477     u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
0478     unsigned int major, minor, sub_minor;
0479 
0480     major = upper_32_bits(fw_ver);
0481     minor = high_16_bits(lower_32_bits(fw_ver));
0482     sub_minor = low_16_bits(fw_ver);
0483 
0484     snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
0485          sub_minor);
0486 }
0487 
0488 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
0489 {
0490     struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
0491 
0492     hr_dev->active = false;
0493     unregister_netdevice_notifier(&iboe->nb);
0494     ib_unregister_device(&hr_dev->ib_dev);
0495 }
0496 
0497 static const struct ib_device_ops hns_roce_dev_ops = {
0498     .owner = THIS_MODULE,
0499     .driver_id = RDMA_DRIVER_HNS,
0500     .uverbs_abi_ver = 1,
0501     .uverbs_no_driver_id_binding = 1,
0502 
0503     .get_dev_fw_str = hns_roce_get_fw_ver,
0504     .add_gid = hns_roce_add_gid,
0505     .alloc_pd = hns_roce_alloc_pd,
0506     .alloc_ucontext = hns_roce_alloc_ucontext,
0507     .create_ah = hns_roce_create_ah,
0508     .create_user_ah = hns_roce_create_ah,
0509     .create_cq = hns_roce_create_cq,
0510     .create_qp = hns_roce_create_qp,
0511     .dealloc_pd = hns_roce_dealloc_pd,
0512     .dealloc_ucontext = hns_roce_dealloc_ucontext,
0513     .del_gid = hns_roce_del_gid,
0514     .dereg_mr = hns_roce_dereg_mr,
0515     .destroy_ah = hns_roce_destroy_ah,
0516     .destroy_cq = hns_roce_destroy_cq,
0517     .disassociate_ucontext = hns_roce_disassociate_ucontext,
0518     .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
0519     .get_dma_mr = hns_roce_get_dma_mr,
0520     .get_link_layer = hns_roce_get_link_layer,
0521     .get_port_immutable = hns_roce_port_immutable,
0522     .mmap = hns_roce_mmap,
0523     .mmap_free = hns_roce_free_mmap,
0524     .modify_device = hns_roce_modify_device,
0525     .modify_qp = hns_roce_modify_qp,
0526     .query_ah = hns_roce_query_ah,
0527     .query_device = hns_roce_query_device,
0528     .query_pkey = hns_roce_query_pkey,
0529     .query_port = hns_roce_query_port,
0530     .reg_user_mr = hns_roce_reg_user_mr,
0531 
0532     INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
0533     INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
0534     INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
0535     INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
0536     INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
0537 };
0538 
0539 static const struct ib_device_ops hns_roce_dev_mr_ops = {
0540     .rereg_user_mr = hns_roce_rereg_user_mr,
0541 };
0542 
0543 static const struct ib_device_ops hns_roce_dev_mw_ops = {
0544     .alloc_mw = hns_roce_alloc_mw,
0545     .dealloc_mw = hns_roce_dealloc_mw,
0546 
0547     INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
0548 };
0549 
0550 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
0551     .alloc_mr = hns_roce_alloc_mr,
0552     .map_mr_sg = hns_roce_map_mr_sg,
0553 };
0554 
0555 static const struct ib_device_ops hns_roce_dev_srq_ops = {
0556     .create_srq = hns_roce_create_srq,
0557     .destroy_srq = hns_roce_destroy_srq,
0558 
0559     INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
0560 };
0561 
0562 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
0563     .alloc_xrcd = hns_roce_alloc_xrcd,
0564     .dealloc_xrcd = hns_roce_dealloc_xrcd,
0565 
0566     INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
0567 };
0568 
0569 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
0570 {
0571     int ret;
0572     struct hns_roce_ib_iboe *iboe = NULL;
0573     struct ib_device *ib_dev = NULL;
0574     struct device *dev = hr_dev->dev;
0575     unsigned int i;
0576 
0577     iboe = &hr_dev->iboe;
0578     spin_lock_init(&iboe->lock);
0579 
0580     ib_dev = &hr_dev->ib_dev;
0581 
0582     ib_dev->node_type = RDMA_NODE_IB_CA;
0583     ib_dev->dev.parent = dev;
0584 
0585     ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
0586     ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
0587     ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
0588 
0589     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
0590         ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
0591 
0592     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
0593         ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
0594 
0595     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
0596         ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
0597 
0598     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
0599         ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
0600         ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
0601     }
0602 
0603     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
0604         ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
0605 
0606     ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
0607     ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
0608     for (i = 0; i < hr_dev->caps.num_ports; i++) {
0609         if (!hr_dev->iboe.netdevs[i])
0610             continue;
0611 
0612         ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
0613                        i + 1);
0614         if (ret)
0615             return ret;
0616     }
0617     dma_set_max_seg_size(dev, UINT_MAX);
0618     ret = ib_register_device(ib_dev, "hns_%d", dev);
0619     if (ret) {
0620         dev_err(dev, "ib_register_device failed!\n");
0621         return ret;
0622     }
0623 
0624     ret = hns_roce_setup_mtu_mac(hr_dev);
0625     if (ret) {
0626         dev_err(dev, "setup_mtu_mac failed!\n");
0627         goto error_failed_setup_mtu_mac;
0628     }
0629 
0630     iboe->nb.notifier_call = hns_roce_netdev_event;
0631     ret = register_netdevice_notifier(&iboe->nb);
0632     if (ret) {
0633         dev_err(dev, "register_netdevice_notifier failed!\n");
0634         goto error_failed_setup_mtu_mac;
0635     }
0636 
0637     hr_dev->active = true;
0638     return 0;
0639 
0640 error_failed_setup_mtu_mac:
0641     ib_unregister_device(ib_dev);
0642 
0643     return ret;
0644 }
0645 
0646 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
0647 {
0648     struct device *dev = hr_dev->dev;
0649     int ret;
0650 
0651     ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
0652                       HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
0653                       hr_dev->caps.num_mtpts, 1);
0654     if (ret) {
0655         dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
0656         return ret;
0657     }
0658 
0659     ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
0660                       HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
0661                       hr_dev->caps.num_qps, 1);
0662     if (ret) {
0663         dev_err(dev, "Failed to init QP context memory, aborting.\n");
0664         goto err_unmap_dmpt;
0665     }
0666 
0667     ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
0668                       HEM_TYPE_IRRL,
0669                       hr_dev->caps.irrl_entry_sz *
0670                       hr_dev->caps.max_qp_init_rdma,
0671                       hr_dev->caps.num_qps, 1);
0672     if (ret) {
0673         dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
0674         goto err_unmap_qp;
0675     }
0676 
0677     if (hr_dev->caps.trrl_entry_sz) {
0678         ret = hns_roce_init_hem_table(hr_dev,
0679                           &hr_dev->qp_table.trrl_table,
0680                           HEM_TYPE_TRRL,
0681                           hr_dev->caps.trrl_entry_sz *
0682                           hr_dev->caps.max_qp_dest_rdma,
0683                           hr_dev->caps.num_qps, 1);
0684         if (ret) {
0685             dev_err(dev,
0686                 "Failed to init trrl_table memory, aborting.\n");
0687             goto err_unmap_irrl;
0688         }
0689     }
0690 
0691     ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
0692                       HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
0693                       hr_dev->caps.num_cqs, 1);
0694     if (ret) {
0695         dev_err(dev, "Failed to init CQ context memory, aborting.\n");
0696         goto err_unmap_trrl;
0697     }
0698 
0699     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
0700         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
0701                           HEM_TYPE_SRQC,
0702                           hr_dev->caps.srqc_entry_sz,
0703                           hr_dev->caps.num_srqs, 1);
0704         if (ret) {
0705             dev_err(dev,
0706                 "Failed to init SRQ context memory, aborting.\n");
0707             goto err_unmap_cq;
0708         }
0709     }
0710 
0711     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
0712         ret = hns_roce_init_hem_table(hr_dev,
0713                           &hr_dev->qp_table.sccc_table,
0714                           HEM_TYPE_SCCC,
0715                           hr_dev->caps.sccc_sz,
0716                           hr_dev->caps.num_qps, 1);
0717         if (ret) {
0718             dev_err(dev,
0719                 "Failed to init SCC context memory, aborting.\n");
0720             goto err_unmap_srq;
0721         }
0722     }
0723 
0724     if (hr_dev->caps.qpc_timer_entry_sz) {
0725         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
0726                           HEM_TYPE_QPC_TIMER,
0727                           hr_dev->caps.qpc_timer_entry_sz,
0728                           hr_dev->caps.qpc_timer_bt_num, 1);
0729         if (ret) {
0730             dev_err(dev,
0731                 "Failed to init QPC timer memory, aborting.\n");
0732             goto err_unmap_ctx;
0733         }
0734     }
0735 
0736     if (hr_dev->caps.cqc_timer_entry_sz) {
0737         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
0738                           HEM_TYPE_CQC_TIMER,
0739                           hr_dev->caps.cqc_timer_entry_sz,
0740                           hr_dev->caps.cqc_timer_bt_num, 1);
0741         if (ret) {
0742             dev_err(dev,
0743                 "Failed to init CQC timer memory, aborting.\n");
0744             goto err_unmap_qpc_timer;
0745         }
0746     }
0747 
0748     if (hr_dev->caps.gmv_entry_sz) {
0749         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
0750                           HEM_TYPE_GMV,
0751                           hr_dev->caps.gmv_entry_sz,
0752                           hr_dev->caps.gmv_entry_num, 1);
0753         if (ret) {
0754             dev_err(dev,
0755                 "failed to init gmv table memory, ret = %d\n",
0756                 ret);
0757             goto err_unmap_cqc_timer;
0758         }
0759     }
0760 
0761     return 0;
0762 
0763 err_unmap_cqc_timer:
0764     if (hr_dev->caps.cqc_timer_entry_sz)
0765         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
0766 
0767 err_unmap_qpc_timer:
0768     if (hr_dev->caps.qpc_timer_entry_sz)
0769         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
0770 
0771 err_unmap_ctx:
0772     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
0773         hns_roce_cleanup_hem_table(hr_dev,
0774                        &hr_dev->qp_table.sccc_table);
0775 err_unmap_srq:
0776     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
0777         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
0778 
0779 err_unmap_cq:
0780     hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
0781 
0782 err_unmap_trrl:
0783     if (hr_dev->caps.trrl_entry_sz)
0784         hns_roce_cleanup_hem_table(hr_dev,
0785                        &hr_dev->qp_table.trrl_table);
0786 
0787 err_unmap_irrl:
0788     hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
0789 
0790 err_unmap_qp:
0791     hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
0792 
0793 err_unmap_dmpt:
0794     hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
0795 
0796     return ret;
0797 }
0798 
0799 /**
0800  * hns_roce_setup_hca - setup host channel adapter
0801  * @hr_dev: pointer to hns roce device
0802  * Return : int
0803  */
0804 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
0805 {
0806     struct device *dev = hr_dev->dev;
0807     int ret;
0808 
0809     spin_lock_init(&hr_dev->sm_lock);
0810 
0811     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
0812         hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
0813         INIT_LIST_HEAD(&hr_dev->pgdir_list);
0814         mutex_init(&hr_dev->pgdir_mutex);
0815     }
0816 
0817     hns_roce_init_uar_table(hr_dev);
0818 
0819     ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
0820     if (ret) {
0821         dev_err(dev, "Failed to allocate priv_uar.\n");
0822         goto err_uar_table_free;
0823     }
0824 
0825     ret = hns_roce_init_qp_table(hr_dev);
0826     if (ret) {
0827         dev_err(dev, "Failed to init qp_table.\n");
0828         goto err_uar_table_free;
0829     }
0830 
0831     hns_roce_init_pd_table(hr_dev);
0832 
0833     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
0834         hns_roce_init_xrcd_table(hr_dev);
0835 
0836     hns_roce_init_mr_table(hr_dev);
0837 
0838     hns_roce_init_cq_table(hr_dev);
0839 
0840     if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
0841         hns_roce_init_srq_table(hr_dev);
0842     }
0843 
0844     return 0;
0845 
0846 err_uar_table_free:
0847     ida_destroy(&hr_dev->uar_ida.ida);
0848     return ret;
0849 }
0850 
0851 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
0852 {
0853     struct hns_roce_cq *hr_cq = to_hr_cq(cq);
0854     unsigned long flags;
0855 
0856     spin_lock_irqsave(&hr_cq->lock, flags);
0857     if (cq->comp_handler) {
0858         if (!hr_cq->is_armed) {
0859             hr_cq->is_armed = 1;
0860             list_add_tail(&hr_cq->node, cq_list);
0861         }
0862     }
0863     spin_unlock_irqrestore(&hr_cq->lock, flags);
0864 }
0865 
0866 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
0867 {
0868     struct hns_roce_qp *hr_qp;
0869     struct hns_roce_cq *hr_cq;
0870     struct list_head cq_list;
0871     unsigned long flags_qp;
0872     unsigned long flags;
0873 
0874     INIT_LIST_HEAD(&cq_list);
0875 
0876     spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
0877     list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
0878         spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
0879         if (hr_qp->sq.tail != hr_qp->sq.head)
0880             check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
0881         spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
0882 
0883         spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
0884         if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
0885             check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
0886         spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
0887     }
0888 
0889     list_for_each_entry(hr_cq, &cq_list, node)
0890         hns_roce_cq_completion(hr_dev, hr_cq->cqn);
0891 
0892     spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
0893 }
0894 
0895 int hns_roce_init(struct hns_roce_dev *hr_dev)
0896 {
0897     struct device *dev = hr_dev->dev;
0898     int ret;
0899 
0900     hr_dev->is_reset = false;
0901 
0902     if (hr_dev->hw->cmq_init) {
0903         ret = hr_dev->hw->cmq_init(hr_dev);
0904         if (ret) {
0905             dev_err(dev, "Init RoCE Command Queue failed!\n");
0906             return ret;
0907         }
0908     }
0909 
0910     ret = hr_dev->hw->hw_profile(hr_dev);
0911     if (ret) {
0912         dev_err(dev, "Get RoCE engine profile failed!\n");
0913         goto error_failed_cmd_init;
0914     }
0915 
0916     ret = hns_roce_cmd_init(hr_dev);
0917     if (ret) {
0918         dev_err(dev, "cmd init failed!\n");
0919         goto error_failed_cmd_init;
0920     }
0921 
0922     /* EQ depends on poll mode, event mode depends on EQ */
0923     ret = hr_dev->hw->init_eq(hr_dev);
0924     if (ret) {
0925         dev_err(dev, "eq init failed!\n");
0926         goto error_failed_eq_table;
0927     }
0928 
0929     if (hr_dev->cmd_mod) {
0930         ret = hns_roce_cmd_use_events(hr_dev);
0931         if (ret)
0932             dev_warn(dev,
0933                  "Cmd event  mode failed, set back to poll!\n");
0934     }
0935 
0936     ret = hns_roce_init_hem(hr_dev);
0937     if (ret) {
0938         dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
0939         goto error_failed_init_hem;
0940     }
0941 
0942     ret = hns_roce_setup_hca(hr_dev);
0943     if (ret) {
0944         dev_err(dev, "setup hca failed!\n");
0945         goto error_failed_setup_hca;
0946     }
0947 
0948     if (hr_dev->hw->hw_init) {
0949         ret = hr_dev->hw->hw_init(hr_dev);
0950         if (ret) {
0951             dev_err(dev, "hw_init failed!\n");
0952             goto error_failed_engine_init;
0953         }
0954     }
0955 
0956     INIT_LIST_HEAD(&hr_dev->qp_list);
0957     spin_lock_init(&hr_dev->qp_list_lock);
0958     INIT_LIST_HEAD(&hr_dev->dip_list);
0959     spin_lock_init(&hr_dev->dip_list_lock);
0960 
0961     ret = hns_roce_register_device(hr_dev);
0962     if (ret)
0963         goto error_failed_register_device;
0964 
0965     return 0;
0966 
0967 error_failed_register_device:
0968     if (hr_dev->hw->hw_exit)
0969         hr_dev->hw->hw_exit(hr_dev);
0970 
0971 error_failed_engine_init:
0972     hns_roce_cleanup_bitmap(hr_dev);
0973 
0974 error_failed_setup_hca:
0975     hns_roce_cleanup_hem(hr_dev);
0976 
0977 error_failed_init_hem:
0978     if (hr_dev->cmd_mod)
0979         hns_roce_cmd_use_polling(hr_dev);
0980     hr_dev->hw->cleanup_eq(hr_dev);
0981 
0982 error_failed_eq_table:
0983     hns_roce_cmd_cleanup(hr_dev);
0984 
0985 error_failed_cmd_init:
0986     if (hr_dev->hw->cmq_exit)
0987         hr_dev->hw->cmq_exit(hr_dev);
0988 
0989     return ret;
0990 }
0991 
0992 void hns_roce_exit(struct hns_roce_dev *hr_dev)
0993 {
0994     hns_roce_unregister_device(hr_dev);
0995 
0996     if (hr_dev->hw->hw_exit)
0997         hr_dev->hw->hw_exit(hr_dev);
0998     hns_roce_cleanup_bitmap(hr_dev);
0999     hns_roce_cleanup_hem(hr_dev);
1000 
1001     if (hr_dev->cmd_mod)
1002         hns_roce_cmd_use_polling(hr_dev);
1003 
1004     hr_dev->hw->cleanup_eq(hr_dev);
1005     hns_roce_cmd_cleanup(hr_dev);
1006     if (hr_dev->hw->cmq_exit)
1007         hr_dev->hw->cmq_exit(hr_dev);
1008 }
1009 
1010 MODULE_LICENSE("Dual BSD/GPL");
1011 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1012 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1013 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1014 MODULE_DESCRIPTION("HNS RoCE Driver");
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