hw/hns/hns_roce_cmd.h

0001 /*
0002  * Copyright (c) 2016 Hisilicon Limited.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef _HNS_ROCE_CMD_H
0034 #define _HNS_ROCE_CMD_H
0035
0036 #define HNS_ROCE_MAILBOX_SIZE       4096
0037 #define HNS_ROCE_CMD_TIMEOUT_MSECS  10000
0038
0039 enum {
0040     /* QPC BT commands */
0041     HNS_ROCE_CMD_WRITE_QPC_BT0  = 0x0,
0042     HNS_ROCE_CMD_WRITE_QPC_BT1  = 0x1,
0043     HNS_ROCE_CMD_WRITE_QPC_BT2  = 0x2,
0044     HNS_ROCE_CMD_READ_QPC_BT0   = 0x4,
0045     HNS_ROCE_CMD_READ_QPC_BT1   = 0x5,
0046     HNS_ROCE_CMD_READ_QPC_BT2   = 0x6,
0047     HNS_ROCE_CMD_DESTROY_QPC_BT0    = 0x8,
0048     HNS_ROCE_CMD_DESTROY_QPC_BT1    = 0x9,
0049     HNS_ROCE_CMD_DESTROY_QPC_BT2    = 0xa,
0050
0051     /* QPC operation */
0052     HNS_ROCE_CMD_MODIFY_QPC     = 0x41,
0053     HNS_ROCE_CMD_QUERY_QPC      = 0x42,
0054
0055     HNS_ROCE_CMD_MODIFY_CQC     = 0x52,
0056     HNS_ROCE_CMD_QUERY_CQC      = 0x53,
0057     /* CQC BT commands */
0058     HNS_ROCE_CMD_WRITE_CQC_BT0  = 0x10,
0059     HNS_ROCE_CMD_WRITE_CQC_BT1  = 0x11,
0060     HNS_ROCE_CMD_WRITE_CQC_BT2  = 0x12,
0061     HNS_ROCE_CMD_READ_CQC_BT0   = 0x14,
0062     HNS_ROCE_CMD_READ_CQC_BT1   = 0x15,
0063     HNS_ROCE_CMD_READ_CQC_BT2   = 0x1b,
0064     HNS_ROCE_CMD_DESTROY_CQC_BT0    = 0x18,
0065     HNS_ROCE_CMD_DESTROY_CQC_BT1    = 0x19,
0066     HNS_ROCE_CMD_DESTROY_CQC_BT2    = 0x1a,
0067
0068     /* MPT BT commands */
0069     HNS_ROCE_CMD_WRITE_MPT_BT0  = 0x20,
0070     HNS_ROCE_CMD_WRITE_MPT_BT1  = 0x21,
0071     HNS_ROCE_CMD_WRITE_MPT_BT2  = 0x22,
0072     HNS_ROCE_CMD_READ_MPT_BT0   = 0x24,
0073     HNS_ROCE_CMD_READ_MPT_BT1   = 0x25,
0074     HNS_ROCE_CMD_READ_MPT_BT2   = 0x26,
0075     HNS_ROCE_CMD_DESTROY_MPT_BT0    = 0x28,
0076     HNS_ROCE_CMD_DESTROY_MPT_BT1    = 0x29,
0077     HNS_ROCE_CMD_DESTROY_MPT_BT2    = 0x2a,
0078
0079     /* CQC TIMER commands */
0080     HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 = 0x23,
0081     HNS_ROCE_CMD_READ_CQC_TIMER_BT0  = 0x27,
0082
0083     /* MPT commands */
0084     HNS_ROCE_CMD_QUERY_MPT      = 0x62,
0085
0086     /* SRQC BT commands */
0087     HNS_ROCE_CMD_WRITE_SRQC_BT0 = 0x30,
0088     HNS_ROCE_CMD_WRITE_SRQC_BT1 = 0x31,
0089     HNS_ROCE_CMD_WRITE_SRQC_BT2 = 0x32,
0090     HNS_ROCE_CMD_READ_SRQC_BT0  = 0x34,
0091     HNS_ROCE_CMD_READ_SRQC_BT1  = 0x35,
0092     HNS_ROCE_CMD_READ_SRQC_BT2  = 0x36,
0093     HNS_ROCE_CMD_DESTROY_SRQC_BT0   = 0x38,
0094     HNS_ROCE_CMD_DESTROY_SRQC_BT1   = 0x39,
0095     HNS_ROCE_CMD_DESTROY_SRQC_BT2   = 0x3a,
0096
0097     /* QPC TIMER commands */
0098     HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 = 0x33,
0099     HNS_ROCE_CMD_READ_QPC_TIMER_BT0  = 0x37,
0100
0101     /* EQC commands */
0102     HNS_ROCE_CMD_CREATE_AEQC    = 0x80,
0103     HNS_ROCE_CMD_MODIFY_AEQC    = 0x81,
0104     HNS_ROCE_CMD_QUERY_AEQC     = 0x82,
0105     HNS_ROCE_CMD_DESTROY_AEQC   = 0x83,
0106     HNS_ROCE_CMD_CREATE_CEQC    = 0x90,
0107     HNS_ROCE_CMD_MODIFY_CEQC    = 0x91,
0108     HNS_ROCE_CMD_QUERY_CEQC     = 0x92,
0109     HNS_ROCE_CMD_DESTROY_CEQC   = 0x93,
0110
0111     /* SCC CTX BT commands */
0112     HNS_ROCE_CMD_READ_SCCC_BT0  = 0xa4,
0113     HNS_ROCE_CMD_WRITE_SCCC_BT0 = 0xa5,
0114 };
0115
0116 enum {
0117     /* TPT commands */
0118     HNS_ROCE_CMD_CREATE_MPT     = 0xd,
0119     HNS_ROCE_CMD_DESTROY_MPT    = 0xf,
0120
0121     /* CQ commands */
0122     HNS_ROCE_CMD_CREATE_CQC     = 0x16,
0123     HNS_ROCE_CMD_DESTROY_CQC    = 0x17,
0124
0125     /* QP/EE commands */
0126     HNS_ROCE_CMD_RST2INIT_QP    = 0x19,
0127     HNS_ROCE_CMD_INIT2RTR_QP    = 0x1a,
0128     HNS_ROCE_CMD_RTR2RTS_QP     = 0x1b,
0129     HNS_ROCE_CMD_RTS2RTS_QP     = 0x1c,
0130     HNS_ROCE_CMD_2ERR_QP        = 0x1e,
0131     HNS_ROCE_CMD_RTS2SQD_QP     = 0x1f,
0132     HNS_ROCE_CMD_SQD2RTS_QP     = 0x20,
0133     HNS_ROCE_CMD_2RST_QP        = 0x21,
0134     HNS_ROCE_CMD_QUERY_QP       = 0x22,
0135     HNS_ROCE_CMD_SQD2SQD_QP     = 0x38,
0136     HNS_ROCE_CMD_CREATE_SRQ     = 0x70,
0137     HNS_ROCE_CMD_MODIFY_SRQC    = 0x72,
0138     HNS_ROCE_CMD_QUERY_SRQC     = 0x73,
0139     HNS_ROCE_CMD_DESTROY_SRQ    = 0x74,
0140 };
0141
0142 int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
0143               u8 cmd, unsigned long tag);
0144
0145 struct hns_roce_cmd_mailbox *
0146 hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
0147 void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
0148                    struct hns_roce_cmd_mailbox *mailbox);
0149 int hns_roce_create_hw_ctx(struct hns_roce_dev *dev,
0150                struct hns_roce_cmd_mailbox *mailbox,
0151                u8 cmd, unsigned long idx);
0152 int hns_roce_destroy_hw_ctx(struct hns_roce_dev *dev, u8 cmd,
0153                 unsigned long idx);
0154
0155 #endif /* _HNS_ROCE_CMD_H */