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0001 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
0002 /*
0003  * Copyright(c) 2015 - 2020 Intel Corporation.
0004  */
0005 
0006 #include <rdma/ib_mad.h>
0007 #include <rdma/ib_user_verbs.h>
0008 #include <linux/io.h>
0009 #include <linux/module.h>
0010 #include <linux/utsname.h>
0011 #include <linux/rculist.h>
0012 #include <linux/mm.h>
0013 #include <linux/vmalloc.h>
0014 #include <rdma/opa_addr.h>
0015 #include <linux/nospec.h>
0016 
0017 #include "hfi.h"
0018 #include "common.h"
0019 #include "device.h"
0020 #include "trace.h"
0021 #include "qp.h"
0022 #include "verbs_txreq.h"
0023 #include "debugfs.h"
0024 #include "vnic.h"
0025 #include "fault.h"
0026 #include "affinity.h"
0027 #include "ipoib.h"
0028 
0029 static unsigned int hfi1_lkey_table_size = 16;
0030 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
0031            S_IRUGO);
0032 MODULE_PARM_DESC(lkey_table_size,
0033          "LKEY table size in bits (2^n, 1 <= n <= 23)");
0034 
0035 static unsigned int hfi1_max_pds = 0xFFFF;
0036 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
0037 MODULE_PARM_DESC(max_pds,
0038          "Maximum number of protection domains to support");
0039 
0040 static unsigned int hfi1_max_ahs = 0xFFFF;
0041 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
0042 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
0043 
0044 unsigned int hfi1_max_cqes = 0x2FFFFF;
0045 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
0046 MODULE_PARM_DESC(max_cqes,
0047          "Maximum number of completion queue entries to support");
0048 
0049 unsigned int hfi1_max_cqs = 0x1FFFF;
0050 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
0051 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
0052 
0053 unsigned int hfi1_max_qp_wrs = 0x3FFF;
0054 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
0055 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
0056 
0057 unsigned int hfi1_max_qps = 32768;
0058 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
0059 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
0060 
0061 unsigned int hfi1_max_sges = 0x60;
0062 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
0063 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
0064 
0065 unsigned int hfi1_max_mcast_grps = 16384;
0066 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
0067 MODULE_PARM_DESC(max_mcast_grps,
0068          "Maximum number of multicast groups to support");
0069 
0070 unsigned int hfi1_max_mcast_qp_attached = 16;
0071 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
0072            uint, S_IRUGO);
0073 MODULE_PARM_DESC(max_mcast_qp_attached,
0074          "Maximum number of attached QPs to support");
0075 
0076 unsigned int hfi1_max_srqs = 1024;
0077 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
0078 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
0079 
0080 unsigned int hfi1_max_srq_sges = 128;
0081 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
0082 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
0083 
0084 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
0085 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
0086 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
0087 
0088 unsigned short piothreshold = 256;
0089 module_param(piothreshold, ushort, S_IRUGO);
0090 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
0091 
0092 static unsigned int sge_copy_mode;
0093 module_param(sge_copy_mode, uint, S_IRUGO);
0094 MODULE_PARM_DESC(sge_copy_mode,
0095          "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
0096 
0097 static void verbs_sdma_complete(
0098     struct sdma_txreq *cookie,
0099     int status);
0100 
0101 static int pio_wait(struct rvt_qp *qp,
0102             struct send_context *sc,
0103             struct hfi1_pkt_state *ps,
0104             u32 flag);
0105 
0106 /* Length of buffer to create verbs txreq cache name */
0107 #define TXREQ_NAME_LEN 24
0108 
0109 static uint wss_threshold = 80;
0110 module_param(wss_threshold, uint, S_IRUGO);
0111 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
0112 static uint wss_clean_period = 256;
0113 module_param(wss_clean_period, uint, S_IRUGO);
0114 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
0115 
0116 /*
0117  * Translate ib_wr_opcode into ib_wc_opcode.
0118  */
0119 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
0120     [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
0121     [IB_WR_TID_RDMA_WRITE] = IB_WC_RDMA_WRITE,
0122     [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
0123     [IB_WR_SEND] = IB_WC_SEND,
0124     [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
0125     [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
0126     [IB_WR_TID_RDMA_READ] = IB_WC_RDMA_READ,
0127     [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
0128     [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
0129     [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
0130     [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
0131     [IB_WR_REG_MR] = IB_WC_REG_MR
0132 };
0133 
0134 /*
0135  * Length of header by opcode, 0 --> not supported
0136  */
0137 const u8 hdr_len_by_opcode[256] = {
0138     /* RC */
0139     [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
0140     [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
0141     [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
0142     [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
0143     [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
0144     [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
0145     [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
0146     [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
0147     [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
0148     [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
0149     [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
0150     [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
0151     [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
0152     [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
0153     [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
0154     [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
0155     [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
0156     [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
0157     [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4 + 8,
0158     [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
0159     [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
0160     [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = 12 + 8 + 4,
0161     [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = 12 + 8 + 4,
0162     [IB_OPCODE_TID_RDMA_READ_REQ]                 = 12 + 8 + 36,
0163     [IB_OPCODE_TID_RDMA_READ_RESP]                = 12 + 8 + 36,
0164     [IB_OPCODE_TID_RDMA_WRITE_REQ]                = 12 + 8 + 36,
0165     [IB_OPCODE_TID_RDMA_WRITE_RESP]               = 12 + 8 + 36,
0166     [IB_OPCODE_TID_RDMA_WRITE_DATA]               = 12 + 8 + 36,
0167     [IB_OPCODE_TID_RDMA_WRITE_DATA_LAST]          = 12 + 8 + 36,
0168     [IB_OPCODE_TID_RDMA_ACK]                      = 12 + 8 + 36,
0169     [IB_OPCODE_TID_RDMA_RESYNC]                   = 12 + 8 + 36,
0170     /* UC */
0171     [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
0172     [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
0173     [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
0174     [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
0175     [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
0176     [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
0177     [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
0178     [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
0179     [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
0180     [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
0181     [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
0182     [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
0183     /* UD */
0184     [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
0185     [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
0186 };
0187 
0188 static const opcode_handler opcode_handler_tbl[256] = {
0189     /* RC */
0190     [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
0191     [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
0192     [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
0193     [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
0194     [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
0195     [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
0196     [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
0197     [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
0198     [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
0199     [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
0200     [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
0201     [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
0202     [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
0203     [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
0204     [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
0205     [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
0206     [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
0207     [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
0208     [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
0209     [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
0210     [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
0211     [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = &hfi1_rc_rcv,
0212     [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = &hfi1_rc_rcv,
0213 
0214     /* TID RDMA has separate handlers for different opcodes.*/
0215     [IB_OPCODE_TID_RDMA_WRITE_REQ]       = &hfi1_rc_rcv_tid_rdma_write_req,
0216     [IB_OPCODE_TID_RDMA_WRITE_RESP]      = &hfi1_rc_rcv_tid_rdma_write_resp,
0217     [IB_OPCODE_TID_RDMA_WRITE_DATA]      = &hfi1_rc_rcv_tid_rdma_write_data,
0218     [IB_OPCODE_TID_RDMA_WRITE_DATA_LAST] = &hfi1_rc_rcv_tid_rdma_write_data,
0219     [IB_OPCODE_TID_RDMA_READ_REQ]        = &hfi1_rc_rcv_tid_rdma_read_req,
0220     [IB_OPCODE_TID_RDMA_READ_RESP]       = &hfi1_rc_rcv_tid_rdma_read_resp,
0221     [IB_OPCODE_TID_RDMA_RESYNC]          = &hfi1_rc_rcv_tid_rdma_resync,
0222     [IB_OPCODE_TID_RDMA_ACK]             = &hfi1_rc_rcv_tid_rdma_ack,
0223 
0224     /* UC */
0225     [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
0226     [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
0227     [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
0228     [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
0229     [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
0230     [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
0231     [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
0232     [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
0233     [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
0234     [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
0235     [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
0236     [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
0237     /* UD */
0238     [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
0239     [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
0240     /* CNP */
0241     [IB_OPCODE_CNP]                   = &hfi1_cnp_rcv
0242 };
0243 
0244 #define OPMASK 0x1f
0245 
0246 static const u32 pio_opmask[BIT(3)] = {
0247     /* RC */
0248     [IB_OPCODE_RC >> 5] =
0249         BIT(RC_OP(SEND_ONLY) & OPMASK) |
0250         BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
0251         BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
0252         BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
0253         BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
0254         BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
0255         BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
0256         BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
0257         BIT(RC_OP(FETCH_ADD) & OPMASK),
0258     /* UC */
0259     [IB_OPCODE_UC >> 5] =
0260         BIT(UC_OP(SEND_ONLY) & OPMASK) |
0261         BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
0262         BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
0263         BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
0264 };
0265 
0266 /*
0267  * System image GUID.
0268  */
0269 __be64 ib_hfi1_sys_image_guid;
0270 
0271 /*
0272  * Make sure the QP is ready and able to accept the given opcode.
0273  */
0274 static inline opcode_handler qp_ok(struct hfi1_packet *packet)
0275 {
0276     if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
0277         return NULL;
0278     if (((packet->opcode & RVT_OPCODE_QP_MASK) ==
0279          packet->qp->allowed_ops) ||
0280         (packet->opcode == IB_OPCODE_CNP))
0281         return opcode_handler_tbl[packet->opcode];
0282 
0283     return NULL;
0284 }
0285 
0286 static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc)
0287 {
0288 #ifdef CONFIG_FAULT_INJECTION
0289     if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP) {
0290         /*
0291          * In order to drop non-IB traffic we
0292          * set PbcInsertHrc to NONE (0x2).
0293          * The packet will still be delivered
0294          * to the receiving node but a
0295          * KHdrHCRCErr (KDETH packet with a bad
0296          * HCRC) will be triggered and the
0297          * packet will not be delivered to the
0298          * correct context.
0299          */
0300         pbc &= ~PBC_INSERT_HCRC_SMASK;
0301         pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT;
0302     } else {
0303         /*
0304          * In order to drop regular verbs
0305          * traffic we set the PbcTestEbp
0306          * flag. The packet will still be
0307          * delivered to the receiving node but
0308          * a 'late ebp error' will be
0309          * triggered and will be dropped.
0310          */
0311         pbc |= PBC_TEST_EBP;
0312     }
0313 #endif
0314     return pbc;
0315 }
0316 
0317 static opcode_handler tid_qp_ok(int opcode, struct hfi1_packet *packet)
0318 {
0319     if (packet->qp->ibqp.qp_type != IB_QPT_RC ||
0320         !(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
0321         return NULL;
0322     if ((opcode & RVT_OPCODE_QP_MASK) == IB_OPCODE_TID_RDMA)
0323         return opcode_handler_tbl[opcode];
0324     return NULL;
0325 }
0326 
0327 void hfi1_kdeth_eager_rcv(struct hfi1_packet *packet)
0328 {
0329     struct hfi1_ctxtdata *rcd = packet->rcd;
0330     struct ib_header *hdr = packet->hdr;
0331     u32 tlen = packet->tlen;
0332     struct hfi1_pportdata *ppd = rcd->ppd;
0333     struct hfi1_ibport *ibp = &ppd->ibport_data;
0334     struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
0335     opcode_handler opcode_handler;
0336     unsigned long flags;
0337     u32 qp_num;
0338     int lnh;
0339     u8 opcode;
0340 
0341     /* DW == LRH (2) + BTH (3) + KDETH (9) + CRC (1) */
0342     if (unlikely(tlen < 15 * sizeof(u32)))
0343         goto drop;
0344 
0345     lnh = be16_to_cpu(hdr->lrh[0]) & 3;
0346     if (lnh != HFI1_LRH_BTH)
0347         goto drop;
0348 
0349     packet->ohdr = &hdr->u.oth;
0350     trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
0351 
0352     opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
0353     inc_opstats(tlen, &rcd->opstats->stats[opcode]);
0354 
0355     /* verbs_qp can be picked up from any tid_rdma header struct */
0356     qp_num = be32_to_cpu(packet->ohdr->u.tid_rdma.r_req.verbs_qp) &
0357         RVT_QPN_MASK;
0358 
0359     rcu_read_lock();
0360     packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
0361     if (!packet->qp)
0362         goto drop_rcu;
0363     spin_lock_irqsave(&packet->qp->r_lock, flags);
0364     opcode_handler = tid_qp_ok(opcode, packet);
0365     if (likely(opcode_handler))
0366         opcode_handler(packet);
0367     else
0368         goto drop_unlock;
0369     spin_unlock_irqrestore(&packet->qp->r_lock, flags);
0370     rcu_read_unlock();
0371 
0372     return;
0373 drop_unlock:
0374     spin_unlock_irqrestore(&packet->qp->r_lock, flags);
0375 drop_rcu:
0376     rcu_read_unlock();
0377 drop:
0378     ibp->rvp.n_pkt_drops++;
0379 }
0380 
0381 void hfi1_kdeth_expected_rcv(struct hfi1_packet *packet)
0382 {
0383     struct hfi1_ctxtdata *rcd = packet->rcd;
0384     struct ib_header *hdr = packet->hdr;
0385     u32 tlen = packet->tlen;
0386     struct hfi1_pportdata *ppd = rcd->ppd;
0387     struct hfi1_ibport *ibp = &ppd->ibport_data;
0388     struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
0389     opcode_handler opcode_handler;
0390     unsigned long flags;
0391     u32 qp_num;
0392     int lnh;
0393     u8 opcode;
0394 
0395     /* DW == LRH (2) + BTH (3) + KDETH (9) + CRC (1) */
0396     if (unlikely(tlen < 15 * sizeof(u32)))
0397         goto drop;
0398 
0399     lnh = be16_to_cpu(hdr->lrh[0]) & 3;
0400     if (lnh != HFI1_LRH_BTH)
0401         goto drop;
0402 
0403     packet->ohdr = &hdr->u.oth;
0404     trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
0405 
0406     opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
0407     inc_opstats(tlen, &rcd->opstats->stats[opcode]);
0408 
0409     /* verbs_qp can be picked up from any tid_rdma header struct */
0410     qp_num = be32_to_cpu(packet->ohdr->u.tid_rdma.r_rsp.verbs_qp) &
0411         RVT_QPN_MASK;
0412 
0413     rcu_read_lock();
0414     packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
0415     if (!packet->qp)
0416         goto drop_rcu;
0417     spin_lock_irqsave(&packet->qp->r_lock, flags);
0418     opcode_handler = tid_qp_ok(opcode, packet);
0419     if (likely(opcode_handler))
0420         opcode_handler(packet);
0421     else
0422         goto drop_unlock;
0423     spin_unlock_irqrestore(&packet->qp->r_lock, flags);
0424     rcu_read_unlock();
0425 
0426     return;
0427 drop_unlock:
0428     spin_unlock_irqrestore(&packet->qp->r_lock, flags);
0429 drop_rcu:
0430     rcu_read_unlock();
0431 drop:
0432     ibp->rvp.n_pkt_drops++;
0433 }
0434 
0435 static int hfi1_do_pkey_check(struct hfi1_packet *packet)
0436 {
0437     struct hfi1_ctxtdata *rcd = packet->rcd;
0438     struct hfi1_pportdata *ppd = rcd->ppd;
0439     struct hfi1_16b_header *hdr = packet->hdr;
0440     u16 pkey;
0441 
0442     /* Pkey check needed only for bypass packets */
0443     if (packet->etype != RHF_RCV_TYPE_BYPASS)
0444         return 0;
0445 
0446     /* Perform pkey check */
0447     pkey = hfi1_16B_get_pkey(hdr);
0448     return ingress_pkey_check(ppd, pkey, packet->sc,
0449                   packet->qp->s_pkey_index,
0450                   packet->slid, true);
0451 }
0452 
0453 static inline void hfi1_handle_packet(struct hfi1_packet *packet,
0454                       bool is_mcast)
0455 {
0456     u32 qp_num;
0457     struct hfi1_ctxtdata *rcd = packet->rcd;
0458     struct hfi1_pportdata *ppd = rcd->ppd;
0459     struct hfi1_ibport *ibp = rcd_to_iport(rcd);
0460     struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
0461     opcode_handler packet_handler;
0462     unsigned long flags;
0463 
0464     inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]);
0465 
0466     if (unlikely(is_mcast)) {
0467         struct rvt_mcast *mcast;
0468         struct rvt_mcast_qp *p;
0469 
0470         if (!packet->grh)
0471             goto drop;
0472         mcast = rvt_mcast_find(&ibp->rvp,
0473                        &packet->grh->dgid,
0474                        opa_get_lid(packet->dlid, 9B));
0475         if (!mcast)
0476             goto drop;
0477         rcu_read_lock();
0478         list_for_each_entry_rcu(p, &mcast->qp_list, list) {
0479             packet->qp = p->qp;
0480             if (hfi1_do_pkey_check(packet))
0481                 goto unlock_drop;
0482             spin_lock_irqsave(&packet->qp->r_lock, flags);
0483             packet_handler = qp_ok(packet);
0484             if (likely(packet_handler))
0485                 packet_handler(packet);
0486             else
0487                 ibp->rvp.n_pkt_drops++;
0488             spin_unlock_irqrestore(&packet->qp->r_lock, flags);
0489         }
0490         rcu_read_unlock();
0491         /*
0492          * Notify rvt_multicast_detach() if it is waiting for us
0493          * to finish.
0494          */
0495         if (atomic_dec_return(&mcast->refcount) <= 1)
0496             wake_up(&mcast->wait);
0497     } else {
0498         /* Get the destination QP number. */
0499         if (packet->etype == RHF_RCV_TYPE_BYPASS &&
0500             hfi1_16B_get_l4(packet->hdr) == OPA_16B_L4_FM)
0501             qp_num = hfi1_16B_get_dest_qpn(packet->mgmt);
0502         else
0503             qp_num = ib_bth_get_qpn(packet->ohdr);
0504 
0505         rcu_read_lock();
0506         packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
0507         if (!packet->qp)
0508             goto unlock_drop;
0509 
0510         if (hfi1_do_pkey_check(packet))
0511             goto unlock_drop;
0512 
0513         spin_lock_irqsave(&packet->qp->r_lock, flags);
0514         packet_handler = qp_ok(packet);
0515         if (likely(packet_handler))
0516             packet_handler(packet);
0517         else
0518             ibp->rvp.n_pkt_drops++;
0519         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
0520         rcu_read_unlock();
0521     }
0522     return;
0523 unlock_drop:
0524     rcu_read_unlock();
0525 drop:
0526     ibp->rvp.n_pkt_drops++;
0527 }
0528 
0529 /**
0530  * hfi1_ib_rcv - process an incoming packet
0531  * @packet: data packet information
0532  *
0533  * This is called to process an incoming packet at interrupt level.
0534  */
0535 void hfi1_ib_rcv(struct hfi1_packet *packet)
0536 {
0537     struct hfi1_ctxtdata *rcd = packet->rcd;
0538 
0539     trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
0540     hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
0541 }
0542 
0543 void hfi1_16B_rcv(struct hfi1_packet *packet)
0544 {
0545     struct hfi1_ctxtdata *rcd = packet->rcd;
0546 
0547     trace_input_ibhdr(rcd->dd, packet, false);
0548     hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
0549 }
0550 
0551 /*
0552  * This is called from a timer to check for QPs
0553  * which need kernel memory in order to send a packet.
0554  */
0555 static void mem_timer(struct timer_list *t)
0556 {
0557     struct hfi1_ibdev *dev = from_timer(dev, t, mem_timer);
0558     struct list_head *list = &dev->memwait;
0559     struct rvt_qp *qp = NULL;
0560     struct iowait *wait;
0561     unsigned long flags;
0562     struct hfi1_qp_priv *priv;
0563 
0564     write_seqlock_irqsave(&dev->iowait_lock, flags);
0565     if (!list_empty(list)) {
0566         wait = list_first_entry(list, struct iowait, list);
0567         qp = iowait_to_qp(wait);
0568         priv = qp->priv;
0569         list_del_init(&priv->s_iowait.list);
0570         priv->s_iowait.lock = NULL;
0571         /* refcount held until actual wake up */
0572         if (!list_empty(list))
0573             mod_timer(&dev->mem_timer, jiffies + 1);
0574     }
0575     write_sequnlock_irqrestore(&dev->iowait_lock, flags);
0576 
0577     if (qp)
0578         hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
0579 }
0580 
0581 /*
0582  * This is called with progress side lock held.
0583  */
0584 /* New API */
0585 static void verbs_sdma_complete(
0586     struct sdma_txreq *cookie,
0587     int status)
0588 {
0589     struct verbs_txreq *tx =
0590         container_of(cookie, struct verbs_txreq, txreq);
0591     struct rvt_qp *qp = tx->qp;
0592 
0593     spin_lock(&qp->s_lock);
0594     if (tx->wqe) {
0595         rvt_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
0596     } else if (qp->ibqp.qp_type == IB_QPT_RC) {
0597         struct hfi1_opa_header *hdr;
0598 
0599         hdr = &tx->phdr.hdr;
0600         if (unlikely(status == SDMA_TXREQ_S_ABORTED))
0601             hfi1_rc_verbs_aborted(qp, hdr);
0602         hfi1_rc_send_complete(qp, hdr);
0603     }
0604     spin_unlock(&qp->s_lock);
0605 
0606     hfi1_put_txreq(tx);
0607 }
0608 
0609 void hfi1_wait_kmem(struct rvt_qp *qp)
0610 {
0611     struct hfi1_qp_priv *priv = qp->priv;
0612     struct ib_qp *ibqp = &qp->ibqp;
0613     struct ib_device *ibdev = ibqp->device;
0614     struct hfi1_ibdev *dev = to_idev(ibdev);
0615 
0616     if (list_empty(&priv->s_iowait.list)) {
0617         if (list_empty(&dev->memwait))
0618             mod_timer(&dev->mem_timer, jiffies + 1);
0619         qp->s_flags |= RVT_S_WAIT_KMEM;
0620         list_add_tail(&priv->s_iowait.list, &dev->memwait);
0621         priv->s_iowait.lock = &dev->iowait_lock;
0622         trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
0623         rvt_get_qp(qp);
0624     }
0625 }
0626 
0627 static int wait_kmem(struct hfi1_ibdev *dev,
0628              struct rvt_qp *qp,
0629              struct hfi1_pkt_state *ps)
0630 {
0631     unsigned long flags;
0632     int ret = 0;
0633 
0634     spin_lock_irqsave(&qp->s_lock, flags);
0635     if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
0636         write_seqlock(&dev->iowait_lock);
0637         list_add_tail(&ps->s_txreq->txreq.list,
0638                   &ps->wait->tx_head);
0639         hfi1_wait_kmem(qp);
0640         write_sequnlock(&dev->iowait_lock);
0641         hfi1_qp_unbusy(qp, ps->wait);
0642         ret = -EBUSY;
0643     }
0644     spin_unlock_irqrestore(&qp->s_lock, flags);
0645 
0646     return ret;
0647 }
0648 
0649 /*
0650  * This routine calls txadds for each sg entry.
0651  *
0652  * Add failures will revert the sge cursor
0653  */
0654 static noinline int build_verbs_ulp_payload(
0655     struct sdma_engine *sde,
0656     u32 length,
0657     struct verbs_txreq *tx)
0658 {
0659     struct rvt_sge_state *ss = tx->ss;
0660     struct rvt_sge *sg_list = ss->sg_list;
0661     struct rvt_sge sge = ss->sge;
0662     u8 num_sge = ss->num_sge;
0663     u32 len;
0664     int ret = 0;
0665 
0666     while (length) {
0667         len = rvt_get_sge_length(&ss->sge, length);
0668         WARN_ON_ONCE(len == 0);
0669         ret = sdma_txadd_kvaddr(
0670             sde->dd,
0671             &tx->txreq,
0672             ss->sge.vaddr,
0673             len);
0674         if (ret)
0675             goto bail_txadd;
0676         rvt_update_sge(ss, len, false);
0677         length -= len;
0678     }
0679     return ret;
0680 bail_txadd:
0681     /* unwind cursor */
0682     ss->sge = sge;
0683     ss->num_sge = num_sge;
0684     ss->sg_list = sg_list;
0685     return ret;
0686 }
0687 
0688 /**
0689  * update_tx_opstats - record stats by opcode
0690  * @qp: the qp
0691  * @ps: transmit packet state
0692  * @plen: the plen in dwords
0693  *
0694  * This is a routine to record the tx opstats after a
0695  * packet has been presented to the egress mechanism.
0696  */
0697 static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
0698                   u32 plen)
0699 {
0700 #ifdef CONFIG_DEBUG_FS
0701     struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
0702     struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats);
0703 
0704     inc_opstats(plen * 4, &s->stats[ps->opcode]);
0705     put_cpu_ptr(s);
0706 #endif
0707 }
0708 
0709 /*
0710  * Build the number of DMA descriptors needed to send length bytes of data.
0711  *
0712  * NOTE: DMA mapping is held in the tx until completed in the ring or
0713  *       the tx desc is freed without having been submitted to the ring
0714  *
0715  * This routine ensures all the helper routine calls succeed.
0716  */
0717 /* New API */
0718 static int build_verbs_tx_desc(
0719     struct sdma_engine *sde,
0720     u32 length,
0721     struct verbs_txreq *tx,
0722     struct hfi1_ahg_info *ahg_info,
0723     u64 pbc)
0724 {
0725     int ret = 0;
0726     struct hfi1_sdma_header *phdr = &tx->phdr;
0727     u16 hdrbytes = (tx->hdr_dwords + sizeof(pbc) / 4) << 2;
0728     u8 extra_bytes = 0;
0729 
0730     if (tx->phdr.hdr.hdr_type) {
0731         /*
0732          * hdrbytes accounts for PBC. Need to subtract 8 bytes
0733          * before calculating padding.
0734          */
0735         extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) +
0736                   (SIZE_OF_CRC << 2) + SIZE_OF_LT;
0737     }
0738     if (!ahg_info->ahgcount) {
0739         ret = sdma_txinit_ahg(
0740             &tx->txreq,
0741             ahg_info->tx_flags,
0742             hdrbytes + length +
0743             extra_bytes,
0744             ahg_info->ahgidx,
0745             0,
0746             NULL,
0747             0,
0748             verbs_sdma_complete);
0749         if (ret)
0750             goto bail_txadd;
0751         phdr->pbc = cpu_to_le64(pbc);
0752         ret = sdma_txadd_kvaddr(
0753             sde->dd,
0754             &tx->txreq,
0755             phdr,
0756             hdrbytes);
0757         if (ret)
0758             goto bail_txadd;
0759     } else {
0760         ret = sdma_txinit_ahg(
0761             &tx->txreq,
0762             ahg_info->tx_flags,
0763             length,
0764             ahg_info->ahgidx,
0765             ahg_info->ahgcount,
0766             ahg_info->ahgdesc,
0767             hdrbytes,
0768             verbs_sdma_complete);
0769         if (ret)
0770             goto bail_txadd;
0771     }
0772     /* add the ulp payload - if any. tx->ss can be NULL for acks */
0773     if (tx->ss) {
0774         ret = build_verbs_ulp_payload(sde, length, tx);
0775         if (ret)
0776             goto bail_txadd;
0777     }
0778 
0779     /* add icrc, lt byte, and padding to flit */
0780     if (extra_bytes)
0781         ret = sdma_txadd_daddr(sde->dd, &tx->txreq,
0782                        sde->dd->sdma_pad_phys, extra_bytes);
0783 
0784 bail_txadd:
0785     return ret;
0786 }
0787 
0788 static u64 update_hcrc(u8 opcode, u64 pbc)
0789 {
0790     if ((opcode & IB_OPCODE_TID_RDMA) == IB_OPCODE_TID_RDMA) {
0791         pbc &= ~PBC_INSERT_HCRC_SMASK;
0792         pbc |= (u64)PBC_IHCRC_LKDETH << PBC_INSERT_HCRC_SHIFT;
0793     }
0794     return pbc;
0795 }
0796 
0797 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
0798             u64 pbc)
0799 {
0800     struct hfi1_qp_priv *priv = qp->priv;
0801     struct hfi1_ahg_info *ahg_info = priv->s_ahg;
0802     u32 hdrwords = ps->s_txreq->hdr_dwords;
0803     u32 len = ps->s_txreq->s_cur_size;
0804     u32 plen;
0805     struct hfi1_ibdev *dev = ps->dev;
0806     struct hfi1_pportdata *ppd = ps->ppd;
0807     struct verbs_txreq *tx;
0808     u8 sc5 = priv->s_sc;
0809     int ret;
0810     u32 dwords;
0811 
0812     if (ps->s_txreq->phdr.hdr.hdr_type) {
0813         u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len);
0814 
0815         dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) +
0816               SIZE_OF_LT) >> 2;
0817     } else {
0818         dwords = (len + 3) >> 2;
0819     }
0820     plen = hdrwords + dwords + sizeof(pbc) / 4;
0821 
0822     tx = ps->s_txreq;
0823     if (!sdma_txreq_built(&tx->txreq)) {
0824         if (likely(pbc == 0)) {
0825             u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
0826 
0827             /* No vl15 here */
0828             /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
0829             if (ps->s_txreq->phdr.hdr.hdr_type)
0830                 pbc |= PBC_PACKET_BYPASS |
0831                        PBC_INSERT_BYPASS_ICRC;
0832             else
0833                 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
0834 
0835             pbc = create_pbc(ppd,
0836                      pbc,
0837                      qp->srate_mbps,
0838                      vl,
0839                      plen);
0840 
0841             if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
0842                 pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
0843             else
0844                 /* Update HCRC based on packet opcode */
0845                 pbc = update_hcrc(ps->opcode, pbc);
0846         }
0847         tx->wqe = qp->s_wqe;
0848         ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
0849         if (unlikely(ret))
0850             goto bail_build;
0851     }
0852     ret =  sdma_send_txreq(tx->sde, ps->wait, &tx->txreq, ps->pkts_sent);
0853     if (unlikely(ret < 0)) {
0854         if (ret == -ECOMM)
0855             goto bail_ecomm;
0856         return ret;
0857     }
0858 
0859     update_tx_opstats(qp, ps, plen);
0860     trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
0861                 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
0862     return ret;
0863 
0864 bail_ecomm:
0865     /* The current one got "sent" */
0866     return 0;
0867 bail_build:
0868     ret = wait_kmem(dev, qp, ps);
0869     if (!ret) {
0870         /* free txreq - bad state */
0871         hfi1_put_txreq(ps->s_txreq);
0872         ps->s_txreq = NULL;
0873     }
0874     return ret;
0875 }
0876 
0877 /*
0878  * If we are now in the error state, return zero to flush the
0879  * send work request.
0880  */
0881 static int pio_wait(struct rvt_qp *qp,
0882             struct send_context *sc,
0883             struct hfi1_pkt_state *ps,
0884             u32 flag)
0885 {
0886     struct hfi1_qp_priv *priv = qp->priv;
0887     struct hfi1_devdata *dd = sc->dd;
0888     unsigned long flags;
0889     int ret = 0;
0890 
0891     /*
0892      * Note that as soon as want_buffer() is called and
0893      * possibly before it returns, sc_piobufavail()
0894      * could be called. Therefore, put QP on the I/O wait list before
0895      * enabling the PIO avail interrupt.
0896      */
0897     spin_lock_irqsave(&qp->s_lock, flags);
0898     if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
0899         write_seqlock(&sc->waitlock);
0900         list_add_tail(&ps->s_txreq->txreq.list,
0901                   &ps->wait->tx_head);
0902         if (list_empty(&priv->s_iowait.list)) {
0903             struct hfi1_ibdev *dev = &dd->verbs_dev;
0904             int was_empty;
0905 
0906             dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
0907             dev->n_piodrain += !!(flag & HFI1_S_WAIT_PIO_DRAIN);
0908             qp->s_flags |= flag;
0909             was_empty = list_empty(&sc->piowait);
0910             iowait_get_priority(&priv->s_iowait);
0911             iowait_queue(ps->pkts_sent, &priv->s_iowait,
0912                      &sc->piowait);
0913             priv->s_iowait.lock = &sc->waitlock;
0914             trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
0915             rvt_get_qp(qp);
0916             /* counting: only call wantpiobuf_intr if first user */
0917             if (was_empty)
0918                 hfi1_sc_wantpiobuf_intr(sc, 1);
0919         }
0920         write_sequnlock(&sc->waitlock);
0921         hfi1_qp_unbusy(qp, ps->wait);
0922         ret = -EBUSY;
0923     }
0924     spin_unlock_irqrestore(&qp->s_lock, flags);
0925     return ret;
0926 }
0927 
0928 static void verbs_pio_complete(void *arg, int code)
0929 {
0930     struct rvt_qp *qp = (struct rvt_qp *)arg;
0931     struct hfi1_qp_priv *priv = qp->priv;
0932 
0933     if (iowait_pio_dec(&priv->s_iowait))
0934         iowait_drain_wakeup(&priv->s_iowait);
0935 }
0936 
0937 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
0938             u64 pbc)
0939 {
0940     struct hfi1_qp_priv *priv = qp->priv;
0941     u32 hdrwords = ps->s_txreq->hdr_dwords;
0942     struct rvt_sge_state *ss = ps->s_txreq->ss;
0943     u32 len = ps->s_txreq->s_cur_size;
0944     u32 dwords;
0945     u32 plen;
0946     struct hfi1_pportdata *ppd = ps->ppd;
0947     u32 *hdr;
0948     u8 sc5;
0949     unsigned long flags = 0;
0950     struct send_context *sc;
0951     struct pio_buf *pbuf;
0952     int wc_status = IB_WC_SUCCESS;
0953     int ret = 0;
0954     pio_release_cb cb = NULL;
0955     u8 extra_bytes = 0;
0956 
0957     if (ps->s_txreq->phdr.hdr.hdr_type) {
0958         u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len);
0959 
0960         extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT;
0961         dwords = (len + extra_bytes) >> 2;
0962         hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah;
0963     } else {
0964         dwords = (len + 3) >> 2;
0965         hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh;
0966     }
0967     plen = hdrwords + dwords + sizeof(pbc) / 4;
0968 
0969     /* only RC/UC use complete */
0970     switch (qp->ibqp.qp_type) {
0971     case IB_QPT_RC:
0972     case IB_QPT_UC:
0973         cb = verbs_pio_complete;
0974         break;
0975     default:
0976         break;
0977     }
0978 
0979     /* vl15 special case taken care of in ud.c */
0980     sc5 = priv->s_sc;
0981     sc = ps->s_txreq->psc;
0982 
0983     if (likely(pbc == 0)) {
0984         u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
0985 
0986         /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
0987         if (ps->s_txreq->phdr.hdr.hdr_type)
0988             pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
0989         else
0990             pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
0991 
0992         pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen);
0993         if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
0994             pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
0995         else
0996             /* Update HCRC based on packet opcode */
0997             pbc = update_hcrc(ps->opcode, pbc);
0998     }
0999     if (cb)
1000         iowait_pio_inc(&priv->s_iowait);
1001     pbuf = sc_buffer_alloc(sc, plen, cb, qp);
1002     if (IS_ERR_OR_NULL(pbuf)) {
1003         if (cb)
1004             verbs_pio_complete(qp, 0);
1005         if (IS_ERR(pbuf)) {
1006             /*
1007              * If we have filled the PIO buffers to capacity and are
1008              * not in an active state this request is not going to
1009              * go out to so just complete it with an error or else a
1010              * ULP or the core may be stuck waiting.
1011              */
1012             hfi1_cdbg(
1013                 PIO,
1014                 "alloc failed. state not active, completing");
1015             wc_status = IB_WC_GENERAL_ERR;
1016             goto pio_bail;
1017         } else {
1018             /*
1019              * This is a normal occurrence. The PIO buffs are full
1020              * up but we are still happily sending, well we could be
1021              * so lets continue to queue the request.
1022              */
1023             hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1024             ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1025             if (!ret)
1026                 /* txreq not queued - free */
1027                 goto bail;
1028             /* tx consumed in wait */
1029             return ret;
1030         }
1031     }
1032 
1033     if (dwords == 0) {
1034         pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1035     } else {
1036         seg_pio_copy_start(pbuf, pbc,
1037                    hdr, hdrwords * 4);
1038         if (ss) {
1039             while (len) {
1040                 void *addr = ss->sge.vaddr;
1041                 u32 slen = rvt_get_sge_length(&ss->sge, len);
1042 
1043                 rvt_update_sge(ss, slen, false);
1044                 seg_pio_copy_mid(pbuf, addr, slen);
1045                 len -= slen;
1046             }
1047         }
1048         /* add icrc, lt byte, and padding to flit */
1049         if (extra_bytes)
1050             seg_pio_copy_mid(pbuf, ppd->dd->sdma_pad_dma,
1051                      extra_bytes);
1052 
1053         seg_pio_copy_end(pbuf);
1054     }
1055 
1056     update_tx_opstats(qp, ps, plen);
1057     trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1058                    &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
1059 
1060 pio_bail:
1061     spin_lock_irqsave(&qp->s_lock, flags);
1062     if (qp->s_wqe) {
1063         rvt_send_complete(qp, qp->s_wqe, wc_status);
1064     } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1065         if (unlikely(wc_status == IB_WC_GENERAL_ERR))
1066             hfi1_rc_verbs_aborted(qp, &ps->s_txreq->phdr.hdr);
1067         hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1068     }
1069     spin_unlock_irqrestore(&qp->s_lock, flags);
1070 
1071     ret = 0;
1072 
1073 bail:
1074     hfi1_put_txreq(ps->s_txreq);
1075     return ret;
1076 }
1077 
1078 /*
1079  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1080  * being an entry from the partition key table), return 0
1081  * otherwise. Use the matching criteria for egress partition keys
1082  * specified in the OPAv1 spec., section 9.1l.7.
1083  */
1084 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1085 {
1086     u16 mkey = pkey & PKEY_LOW_15_MASK;
1087     u16 mentry = ent & PKEY_LOW_15_MASK;
1088 
1089     if (mkey == mentry) {
1090         /*
1091          * If pkey[15] is set (full partition member),
1092          * is bit 15 in the corresponding table element
1093          * clear (limited member)?
1094          */
1095         if (pkey & PKEY_MEMBER_MASK)
1096             return !!(ent & PKEY_MEMBER_MASK);
1097         return 1;
1098     }
1099     return 0;
1100 }
1101 
1102 /**
1103  * egress_pkey_check - check P_KEY of a packet
1104  * @ppd:  Physical IB port data
1105  * @slid: SLID for packet
1106  * @pkey: PKEY for header
1107  * @sc5:  SC for packet
1108  * @s_pkey_index: It will be used for look up optimization for kernel contexts
1109  * only. If it is negative value, then it means user contexts is calling this
1110  * function.
1111  *
1112  * It checks if hdr's pkey is valid.
1113  *
1114  * Return: 0 on success, otherwise, 1
1115  */
1116 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1117               u8 sc5, int8_t s_pkey_index)
1118 {
1119     struct hfi1_devdata *dd;
1120     int i;
1121     int is_user_ctxt_mechanism = (s_pkey_index < 0);
1122 
1123     if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1124         return 0;
1125 
1126     /* If SC15, pkey[0:14] must be 0x7fff */
1127     if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1128         goto bad;
1129 
1130     /* Is the pkey = 0x0, or 0x8000? */
1131     if ((pkey & PKEY_LOW_15_MASK) == 0)
1132         goto bad;
1133 
1134     /*
1135      * For the kernel contexts only, if a qp is passed into the function,
1136      * the most likely matching pkey has index qp->s_pkey_index
1137      */
1138     if (!is_user_ctxt_mechanism &&
1139         egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1140         return 0;
1141     }
1142 
1143     for (i = 0; i < MAX_PKEY_VALUES; i++) {
1144         if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1145             return 0;
1146     }
1147 bad:
1148     /*
1149      * For the user-context mechanism, the P_KEY check would only happen
1150      * once per SDMA request, not once per packet.  Therefore, there's no
1151      * need to increment the counter for the user-context mechanism.
1152      */
1153     if (!is_user_ctxt_mechanism) {
1154         incr_cntr64(&ppd->port_xmit_constraint_errors);
1155         dd = ppd->dd;
1156         if (!(dd->err_info_xmit_constraint.status &
1157               OPA_EI_STATUS_SMASK)) {
1158             dd->err_info_xmit_constraint.status |=
1159                 OPA_EI_STATUS_SMASK;
1160             dd->err_info_xmit_constraint.slid = slid;
1161             dd->err_info_xmit_constraint.pkey = pkey;
1162         }
1163     }
1164     return 1;
1165 }
1166 
1167 /*
1168  * get_send_routine - choose an egress routine
1169  *
1170  * Choose an egress routine based on QP type
1171  * and size
1172  */
1173 static inline send_routine get_send_routine(struct rvt_qp *qp,
1174                         struct hfi1_pkt_state *ps)
1175 {
1176     struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1177     struct hfi1_qp_priv *priv = qp->priv;
1178     struct verbs_txreq *tx = ps->s_txreq;
1179 
1180     if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1181         return dd->process_pio_send;
1182     switch (qp->ibqp.qp_type) {
1183     case IB_QPT_SMI:
1184         return dd->process_pio_send;
1185     case IB_QPT_GSI:
1186     case IB_QPT_UD:
1187         break;
1188     case IB_QPT_UC:
1189     case IB_QPT_RC:
1190         priv->s_running_pkt_size =
1191             (tx->s_cur_size + priv->s_running_pkt_size) / 2;
1192         if (piothreshold &&
1193             priv->s_running_pkt_size <= min(piothreshold, qp->pmtu) &&
1194             (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) &&
1195             iowait_sdma_pending(&priv->s_iowait) == 0 &&
1196             !sdma_txreq_built(&tx->txreq))
1197             return dd->process_pio_send;
1198         break;
1199     default:
1200         break;
1201     }
1202     return dd->process_dma_send;
1203 }
1204 
1205 /**
1206  * hfi1_verbs_send - send a packet
1207  * @qp: the QP to send on
1208  * @ps: the state of the packet to send
1209  *
1210  * Return zero if packet is sent or queued OK.
1211  * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1212  */
1213 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1214 {
1215     struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1216     struct hfi1_qp_priv *priv = qp->priv;
1217     struct ib_other_headers *ohdr = NULL;
1218     send_routine sr;
1219     int ret;
1220     u16 pkey;
1221     u32 slid;
1222     u8 l4 = 0;
1223 
1224     /* locate the pkey within the headers */
1225     if (ps->s_txreq->phdr.hdr.hdr_type) {
1226         struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah;
1227 
1228         l4 = hfi1_16B_get_l4(hdr);
1229         if (l4 == OPA_16B_L4_IB_LOCAL)
1230             ohdr = &hdr->u.oth;
1231         else if (l4 == OPA_16B_L4_IB_GLOBAL)
1232             ohdr = &hdr->u.l.oth;
1233 
1234         slid = hfi1_16B_get_slid(hdr);
1235         pkey = hfi1_16B_get_pkey(hdr);
1236     } else {
1237         struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh;
1238         u8 lnh = ib_get_lnh(hdr);
1239 
1240         if (lnh == HFI1_LRH_GRH)
1241             ohdr = &hdr->u.l.oth;
1242         else
1243             ohdr = &hdr->u.oth;
1244         slid = ib_get_slid(hdr);
1245         pkey = ib_bth_get_pkey(ohdr);
1246     }
1247 
1248     if (likely(l4 != OPA_16B_L4_FM))
1249         ps->opcode = ib_bth_get_opcode(ohdr);
1250     else
1251         ps->opcode = IB_OPCODE_UD_SEND_ONLY;
1252 
1253     sr = get_send_routine(qp, ps);
1254     ret = egress_pkey_check(dd->pport, slid, pkey,
1255                 priv->s_sc, qp->s_pkey_index);
1256     if (unlikely(ret)) {
1257         /*
1258          * The value we are returning here does not get propagated to
1259          * the verbs caller. Thus we need to complete the request with
1260          * error otherwise the caller could be sitting waiting on the
1261          * completion event. Only do this for PIO. SDMA has its own
1262          * mechanism for handling the errors. So for SDMA we can just
1263          * return.
1264          */
1265         if (sr == dd->process_pio_send) {
1266             unsigned long flags;
1267 
1268             hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1269                   __func__);
1270             spin_lock_irqsave(&qp->s_lock, flags);
1271             rvt_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1272             spin_unlock_irqrestore(&qp->s_lock, flags);
1273         }
1274         return -EINVAL;
1275     }
1276     if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1277         return pio_wait(qp,
1278                 ps->s_txreq->psc,
1279                 ps,
1280                 HFI1_S_WAIT_PIO_DRAIN);
1281     return sr(qp, ps, 0);
1282 }
1283 
1284 /**
1285  * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1286  * @dd: the device data structure
1287  */
1288 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1289 {
1290     struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1291     u32 ver = dd->dc8051_ver;
1292 
1293     memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1294 
1295     rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) |
1296         ((u64)(dc8051_ver_min(ver)) << 16) |
1297         (u64)dc8051_ver_patch(ver);
1298 
1299     rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1300             IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1301             IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1302             IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1303             IB_DEVICE_MEM_MGT_EXTENSIONS;
1304     rdi->dparms.props.kernel_cap_flags = IBK_RDMA_NETDEV_OPA;
1305     rdi->dparms.props.page_size_cap = PAGE_SIZE;
1306     rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1307     rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1308     rdi->dparms.props.hw_ver = dd->minrev;
1309     rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1310     rdi->dparms.props.max_mr_size = U64_MAX;
1311     rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1312     rdi->dparms.props.max_qp = hfi1_max_qps;
1313     rdi->dparms.props.max_qp_wr =
1314         (hfi1_max_qp_wrs >= HFI1_QP_WQE_INVALID ?
1315          HFI1_QP_WQE_INVALID - 1 : hfi1_max_qp_wrs);
1316     rdi->dparms.props.max_send_sge = hfi1_max_sges;
1317     rdi->dparms.props.max_recv_sge = hfi1_max_sges;
1318     rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1319     rdi->dparms.props.max_cq = hfi1_max_cqs;
1320     rdi->dparms.props.max_ah = hfi1_max_ahs;
1321     rdi->dparms.props.max_cqe = hfi1_max_cqes;
1322     rdi->dparms.props.max_pd = hfi1_max_pds;
1323     rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1324     rdi->dparms.props.max_qp_init_rd_atom = 255;
1325     rdi->dparms.props.max_srq = hfi1_max_srqs;
1326     rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1327     rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1328     rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1329     rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1330     rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1331     rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1332     rdi->dparms.props.max_total_mcast_qp_attach =
1333                     rdi->dparms.props.max_mcast_qp_attach *
1334                     rdi->dparms.props.max_mcast_grp;
1335 }
1336 
1337 static inline u16 opa_speed_to_ib(u16 in)
1338 {
1339     u16 out = 0;
1340 
1341     if (in & OPA_LINK_SPEED_25G)
1342         out |= IB_SPEED_EDR;
1343     if (in & OPA_LINK_SPEED_12_5G)
1344         out |= IB_SPEED_FDR;
1345 
1346     return out;
1347 }
1348 
1349 /*
1350  * Convert a single OPA link width (no multiple flags) to an IB value.
1351  * A zero OPA link width means link down, which means the IB width value
1352  * is a don't care.
1353  */
1354 static inline u16 opa_width_to_ib(u16 in)
1355 {
1356     switch (in) {
1357     case OPA_LINK_WIDTH_1X:
1358     /* map 2x and 3x to 1x as they don't exist in IB */
1359     case OPA_LINK_WIDTH_2X:
1360     case OPA_LINK_WIDTH_3X:
1361         return IB_WIDTH_1X;
1362     default: /* link down or unknown, return our largest width */
1363     case OPA_LINK_WIDTH_4X:
1364         return IB_WIDTH_4X;
1365     }
1366 }
1367 
1368 static int query_port(struct rvt_dev_info *rdi, u32 port_num,
1369               struct ib_port_attr *props)
1370 {
1371     struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1372     struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1373     struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1374     u32 lid = ppd->lid;
1375 
1376     /* props being zeroed by the caller, avoid zeroing it here */
1377     props->lid = lid ? lid : 0;
1378     props->lmc = ppd->lmc;
1379     /* OPA logical states match IB logical states */
1380     props->state = driver_lstate(ppd);
1381     props->phys_state = driver_pstate(ppd);
1382     props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1383     props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1384     /* see rate_show() in ib core/sysfs.c */
1385     props->active_speed = opa_speed_to_ib(ppd->link_speed_active);
1386     props->max_vl_num = ppd->vls_supported;
1387 
1388     /* Once we are a "first class" citizen and have added the OPA MTUs to
1389      * the core we can advertise the larger MTU enum to the ULPs, for now
1390      * advertise only 4K.
1391      *
1392      * Those applications which are either OPA aware or pass the MTU enum
1393      * from the Path Records to us will get the new 8k MTU.  Those that
1394      * attempt to process the MTU enum may fail in various ways.
1395      */
1396     props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1397                       4096 : hfi1_max_mtu), IB_MTU_4096);
1398     props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1399         mtu_to_enum(ppd->ibmtu, IB_MTU_4096);
1400     props->phys_mtu = hfi1_max_mtu;
1401 
1402     return 0;
1403 }
1404 
1405 static int modify_device(struct ib_device *device,
1406              int device_modify_mask,
1407              struct ib_device_modify *device_modify)
1408 {
1409     struct hfi1_devdata *dd = dd_from_ibdev(device);
1410     unsigned i;
1411     int ret;
1412 
1413     if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1414                    IB_DEVICE_MODIFY_NODE_DESC)) {
1415         ret = -EOPNOTSUPP;
1416         goto bail;
1417     }
1418 
1419     if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1420         memcpy(device->node_desc, device_modify->node_desc,
1421                IB_DEVICE_NODE_DESC_MAX);
1422         for (i = 0; i < dd->num_pports; i++) {
1423             struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1424 
1425             hfi1_node_desc_chg(ibp);
1426         }
1427     }
1428 
1429     if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1430         ib_hfi1_sys_image_guid =
1431             cpu_to_be64(device_modify->sys_image_guid);
1432         for (i = 0; i < dd->num_pports; i++) {
1433             struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1434 
1435             hfi1_sys_guid_chg(ibp);
1436         }
1437     }
1438 
1439     ret = 0;
1440 
1441 bail:
1442     return ret;
1443 }
1444 
1445 static int shut_down_port(struct rvt_dev_info *rdi, u32 port_num)
1446 {
1447     struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1448     struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1449     struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1450     int ret;
1451 
1452     set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1453                  OPA_LINKDOWN_REASON_UNKNOWN);
1454     ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1455     return ret;
1456 }
1457 
1458 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1459                 int guid_index, __be64 *guid)
1460 {
1461     struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1462 
1463     if (guid_index >= HFI1_GUIDS_PER_PORT)
1464         return -EINVAL;
1465 
1466     *guid = get_sguid(ibp, guid_index);
1467     return 0;
1468 }
1469 
1470 /*
1471  * convert ah port,sl to sc
1472  */
1473 u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah)
1474 {
1475     struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah));
1476 
1477     return ibp->sl_to_sc[rdma_ah_get_sl(ah)];
1478 }
1479 
1480 static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1481 {
1482     struct hfi1_ibport *ibp;
1483     struct hfi1_pportdata *ppd;
1484     struct hfi1_devdata *dd;
1485     u8 sc5;
1486     u8 sl;
1487 
1488     if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) &&
1489         !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
1490         return -EINVAL;
1491 
1492     /* test the mapping for validity */
1493     ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1494     ppd = ppd_from_ibp(ibp);
1495     dd = dd_from_ppd(ppd);
1496 
1497     sl = rdma_ah_get_sl(ah_attr);
1498     if (sl >= ARRAY_SIZE(ibp->sl_to_sc))
1499         return -EINVAL;
1500     sl = array_index_nospec(sl, ARRAY_SIZE(ibp->sl_to_sc));
1501 
1502     sc5 = ibp->sl_to_sc[sl];
1503     if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1504         return -EINVAL;
1505     return 0;
1506 }
1507 
1508 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1509                    struct rdma_ah_attr *ah_attr,
1510                    struct rvt_ah *ah)
1511 {
1512     struct hfi1_ibport *ibp;
1513     struct hfi1_pportdata *ppd;
1514     struct hfi1_devdata *dd;
1515     u8 sc5;
1516     struct rdma_ah_attr *attr = &ah->attr;
1517 
1518     /*
1519      * Do not trust reading anything from rvt_ah at this point as it is not
1520      * done being setup. We can however modify things which we need to set.
1521      */
1522 
1523     ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1524     ppd = ppd_from_ibp(ibp);
1525     sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)];
1526     hfi1_update_ah_attr(ibdev, attr);
1527     hfi1_make_opa_lid(attr);
1528     dd = dd_from_ppd(ppd);
1529     ah->vl = sc_to_vlt(dd, sc5);
1530     if (ah->vl < num_vls || ah->vl == 15)
1531         ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1532 }
1533 
1534 /**
1535  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1536  * @dd: the hfi1_ib device
1537  */
1538 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1539 {
1540     return ARRAY_SIZE(dd->pport[0].pkeys);
1541 }
1542 
1543 static void init_ibport(struct hfi1_pportdata *ppd)
1544 {
1545     struct hfi1_ibport *ibp = &ppd->ibport_data;
1546     size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1547     int i;
1548 
1549     for (i = 0; i < sz; i++) {
1550         ibp->sl_to_sc[i] = i;
1551         ibp->sc_to_sl[i] = i;
1552     }
1553 
1554     for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++)
1555         INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list);
1556     timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0);
1557 
1558     spin_lock_init(&ibp->rvp.lock);
1559     /* Set the prefix to the default value (see ch. 4.1.1) */
1560     ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1561     ibp->rvp.sm_lid = 0;
1562     /*
1563      * Below should only set bits defined in OPA PortInfo.CapabilityMask
1564      * and PortInfo.CapabilityMask3
1565      */
1566     ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1567         IB_PORT_CAP_MASK_NOTICE_SUP;
1568     ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported;
1569     ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1570     ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1571     ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1572     ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1573     ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1574 
1575     RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1576     RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1577 }
1578 
1579 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str)
1580 {
1581     struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1582     struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1583     u32 ver = dd_from_dev(dev)->dc8051_ver;
1584 
1585     snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver),
1586          dc8051_ver_min(ver), dc8051_ver_patch(ver));
1587 }
1588 
1589 static const char * const driver_cntr_names[] = {
1590     /* must be element 0*/
1591     "DRIVER_KernIntr",
1592     "DRIVER_ErrorIntr",
1593     "DRIVER_Tx_Errs",
1594     "DRIVER_Rcv_Errs",
1595     "DRIVER_HW_Errs",
1596     "DRIVER_NoPIOBufs",
1597     "DRIVER_CtxtsOpen",
1598     "DRIVER_RcvLen_Errs",
1599     "DRIVER_EgrBufFull",
1600     "DRIVER_EgrHdrFull"
1601 };
1602 
1603 static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */
1604 static struct rdma_stat_desc *dev_cntr_descs;
1605 static struct rdma_stat_desc *port_cntr_descs;
1606 int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1607 static int num_dev_cntrs;
1608 static int num_port_cntrs;
1609 static int cntr_names_initialized;
1610 
1611 /*
1612  * Convert a list of names separated by '\n' into an array of NULL terminated
1613  * strings. Optionally some entries can be reserved in the array to hold extra
1614  * external strings.
1615  */
1616 static int init_cntr_names(const char *names_in, const size_t names_len,
1617                int num_extra_names, int *num_cntrs,
1618                struct rdma_stat_desc **cntr_descs)
1619 {
1620     struct rdma_stat_desc *q;
1621     char *names_out, *p;
1622     int i, n;
1623 
1624     n = 0;
1625     for (i = 0; i < names_len; i++)
1626         if (names_in[i] == '\n')
1627             n++;
1628 
1629     names_out =
1630         kzalloc((n + num_extra_names) * sizeof(*q) + names_len,
1631             GFP_KERNEL);
1632     if (!names_out) {
1633         *num_cntrs = 0;
1634         *cntr_descs = NULL;
1635         return -ENOMEM;
1636     }
1637 
1638     p = names_out + (n + num_extra_names) * sizeof(*q);
1639     memcpy(p, names_in, names_len);
1640 
1641     q = (struct rdma_stat_desc *)names_out;
1642     for (i = 0; i < n; i++) {
1643         q[i].name = p;
1644         p = strchr(p, '\n');
1645         *p++ = '\0';
1646     }
1647 
1648     *num_cntrs = n;
1649     *cntr_descs = (struct rdma_stat_desc *)names_out;
1650     return 0;
1651 }
1652 
1653 static int init_counters(struct ib_device *ibdev)
1654 {
1655     struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1656     int i, err = 0;
1657 
1658     mutex_lock(&cntr_names_lock);
1659     if (cntr_names_initialized)
1660         goto out_unlock;
1661 
1662     err = init_cntr_names(dd->cntrnames, dd->cntrnameslen, num_driver_cntrs,
1663                   &num_dev_cntrs, &dev_cntr_descs);
1664     if (err)
1665         goto out_unlock;
1666 
1667     for (i = 0; i < num_driver_cntrs; i++)
1668         dev_cntr_descs[num_dev_cntrs + i].name = driver_cntr_names[i];
1669 
1670     err = init_cntr_names(dd->portcntrnames, dd->portcntrnameslen, 0,
1671                   &num_port_cntrs, &port_cntr_descs);
1672     if (err) {
1673         kfree(dev_cntr_descs);
1674         dev_cntr_descs = NULL;
1675         goto out_unlock;
1676     }
1677     cntr_names_initialized = 1;
1678 
1679 out_unlock:
1680     mutex_unlock(&cntr_names_lock);
1681     return err;
1682 }
1683 
1684 static struct rdma_hw_stats *hfi1_alloc_hw_device_stats(struct ib_device *ibdev)
1685 {
1686     if (init_counters(ibdev))
1687         return NULL;
1688     return rdma_alloc_hw_stats_struct(dev_cntr_descs,
1689                       num_dev_cntrs + num_driver_cntrs,
1690                       RDMA_HW_STATS_DEFAULT_LIFESPAN);
1691 }
1692 
1693 static struct rdma_hw_stats *hfi_alloc_hw_port_stats(struct ib_device *ibdev,
1694                              u32 port_num)
1695 {
1696     if (init_counters(ibdev))
1697         return NULL;
1698     return rdma_alloc_hw_stats_struct(port_cntr_descs, num_port_cntrs,
1699                       RDMA_HW_STATS_DEFAULT_LIFESPAN);
1700 }
1701 
1702 static u64 hfi1_sps_ints(void)
1703 {
1704     unsigned long index, flags;
1705     struct hfi1_devdata *dd;
1706     u64 sps_ints = 0;
1707 
1708     xa_lock_irqsave(&hfi1_dev_table, flags);
1709     xa_for_each(&hfi1_dev_table, index, dd) {
1710         sps_ints += get_all_cpu_total(dd->int_counter);
1711     }
1712     xa_unlock_irqrestore(&hfi1_dev_table, flags);
1713     return sps_ints;
1714 }
1715 
1716 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1717             u32 port, int index)
1718 {
1719     u64 *values;
1720     int count;
1721 
1722     if (!port) {
1723         u64 *stats = (u64 *)&hfi1_stats;
1724         int i;
1725 
1726         hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1727         values[num_dev_cntrs] = hfi1_sps_ints();
1728         for (i = 1; i < num_driver_cntrs; i++)
1729             values[num_dev_cntrs + i] = stats[i];
1730         count = num_dev_cntrs + num_driver_cntrs;
1731     } else {
1732         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1733 
1734         hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1735         count = num_port_cntrs;
1736     }
1737 
1738     memcpy(stats->value, values, count * sizeof(u64));
1739     return count;
1740 }
1741 
1742 static const struct ib_device_ops hfi1_dev_ops = {
1743     .owner = THIS_MODULE,
1744     .driver_id = RDMA_DRIVER_HFI1,
1745 
1746     .alloc_hw_device_stats = hfi1_alloc_hw_device_stats,
1747     .alloc_hw_port_stats = hfi_alloc_hw_port_stats,
1748     .alloc_rdma_netdev = hfi1_vnic_alloc_rn,
1749     .device_group = &ib_hfi1_attr_group,
1750     .get_dev_fw_str = hfi1_get_dev_fw_str,
1751     .get_hw_stats = get_hw_stats,
1752     .modify_device = modify_device,
1753     .port_groups = hfi1_attr_port_groups,
1754     /* keep process mad in the driver */
1755     .process_mad = hfi1_process_mad,
1756     .rdma_netdev_get_params = hfi1_ipoib_rn_get_params,
1757 };
1758 
1759 /**
1760  * hfi1_register_ib_device - register our device with the infiniband core
1761  * @dd: the device data structure
1762  * Return 0 if successful, errno if unsuccessful.
1763  */
1764 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1765 {
1766     struct hfi1_ibdev *dev = &dd->verbs_dev;
1767     struct ib_device *ibdev = &dev->rdi.ibdev;
1768     struct hfi1_pportdata *ppd = dd->pport;
1769     struct hfi1_ibport *ibp = &ppd->ibport_data;
1770     unsigned i;
1771     int ret;
1772 
1773     for (i = 0; i < dd->num_pports; i++)
1774         init_ibport(ppd + i);
1775 
1776     /* Only need to initialize non-zero fields. */
1777 
1778     timer_setup(&dev->mem_timer, mem_timer, 0);
1779 
1780     seqlock_init(&dev->iowait_lock);
1781     seqlock_init(&dev->txwait_lock);
1782     INIT_LIST_HEAD(&dev->txwait);
1783     INIT_LIST_HEAD(&dev->memwait);
1784 
1785     ret = verbs_txreq_init(dev);
1786     if (ret)
1787         goto err_verbs_txreq;
1788 
1789     /* Use first-port GUID as node guid */
1790     ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1791 
1792     /*
1793      * The system image GUID is supposed to be the same for all
1794      * HFIs in a single system but since there can be other
1795      * device types in the system, we can't be sure this is unique.
1796      */
1797     if (!ib_hfi1_sys_image_guid)
1798         ib_hfi1_sys_image_guid = ibdev->node_guid;
1799     ibdev->phys_port_cnt = dd->num_pports;
1800     ibdev->dev.parent = &dd->pcidev->dev;
1801 
1802     ib_set_device_ops(ibdev, &hfi1_dev_ops);
1803 
1804     strlcpy(ibdev->node_desc, init_utsname()->nodename,
1805         sizeof(ibdev->node_desc));
1806 
1807     /*
1808      * Fill in rvt info object.
1809      */
1810     dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1811     dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1812     dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1813     dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1814     dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1815     dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1816     dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1817     /*
1818      * Fill in rvt info device attributes.
1819      */
1820     hfi1_fill_device_attr(dd);
1821 
1822     /* queue pair */
1823     dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1824     dd->verbs_dev.rdi.dparms.qpn_start = 0;
1825     dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1826     dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1827     dd->verbs_dev.rdi.dparms.qpn_res_start = RVT_KDETH_QP_BASE;
1828     dd->verbs_dev.rdi.dparms.qpn_res_end = RVT_AIP_QP_MAX;
1829     dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1830     dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1831     dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1832     dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1833     dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA |
1834                         RDMA_CORE_CAP_OPA_AH;
1835     dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1836 
1837     dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1838     dd->verbs_dev.rdi.driver_f.qp_priv_init = hfi1_qp_priv_init;
1839     dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1840     dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1841     dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1842     dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt;
1843     dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1844     dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1845     dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1846     dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1847     dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1848     dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1849     dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1850     dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1851     dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1852     dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1853     dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1854     dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1855     dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc;
1856     dd->verbs_dev.rdi.driver_f.setup_wqe = hfi1_setup_wqe;
1857     dd->verbs_dev.rdi.driver_f.comp_vect_cpu_lookup =
1858                         hfi1_comp_vect_mappings_lookup;
1859 
1860     /* completeion queue */
1861     dd->verbs_dev.rdi.ibdev.num_comp_vectors = dd->comp_vect_possible_cpus;
1862     dd->verbs_dev.rdi.dparms.node = dd->node;
1863 
1864     /* misc settings */
1865     dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1866     dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1867     dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1868     dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1869     dd->verbs_dev.rdi.dparms.sge_copy_mode = sge_copy_mode;
1870     dd->verbs_dev.rdi.dparms.wss_threshold = wss_threshold;
1871     dd->verbs_dev.rdi.dparms.wss_clean_period = wss_clean_period;
1872     dd->verbs_dev.rdi.dparms.reserved_operations = 1;
1873     dd->verbs_dev.rdi.dparms.extra_rdma_atomic = HFI1_TID_RDMA_WRITE_CNT;
1874 
1875     /* post send table */
1876     dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1877 
1878     /* opcode translation table */
1879     dd->verbs_dev.rdi.wc_opcode = ib_hfi1_wc_opcode;
1880 
1881     ppd = dd->pport;
1882     for (i = 0; i < dd->num_pports; i++, ppd++)
1883         rvt_init_port(&dd->verbs_dev.rdi,
1884                   &ppd->ibport_data.rvp,
1885                   i,
1886                   ppd->pkeys);
1887 
1888     ret = rvt_register_device(&dd->verbs_dev.rdi);
1889     if (ret)
1890         goto err_verbs_txreq;
1891 
1892     ret = hfi1_verbs_register_sysfs(dd);
1893     if (ret)
1894         goto err_class;
1895 
1896     return ret;
1897 
1898 err_class:
1899     rvt_unregister_device(&dd->verbs_dev.rdi);
1900 err_verbs_txreq:
1901     verbs_txreq_exit(dev);
1902     dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1903     return ret;
1904 }
1905 
1906 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1907 {
1908     struct hfi1_ibdev *dev = &dd->verbs_dev;
1909 
1910     hfi1_verbs_unregister_sysfs(dd);
1911 
1912     rvt_unregister_device(&dd->verbs_dev.rdi);
1913 
1914     if (!list_empty(&dev->txwait))
1915         dd_dev_err(dd, "txwait list not empty!\n");
1916     if (!list_empty(&dev->memwait))
1917         dd_dev_err(dd, "memwait list not empty!\n");
1918 
1919     del_timer_sync(&dev->mem_timer);
1920     verbs_txreq_exit(dev);
1921 
1922     mutex_lock(&cntr_names_lock);
1923     kfree(dev_cntr_descs);
1924     kfree(port_cntr_descs);
1925     dev_cntr_descs = NULL;
1926     port_cntr_descs = NULL;
1927     cntr_names_initialized = 0;
1928     mutex_unlock(&cntr_names_lock);
1929 }
1930 
1931 void hfi1_cnp_rcv(struct hfi1_packet *packet)
1932 {
1933     struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1934     struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1935     struct ib_header *hdr = packet->hdr;
1936     struct rvt_qp *qp = packet->qp;
1937     u32 lqpn, rqpn = 0;
1938     u16 rlid = 0;
1939     u8 sl, sc5, svc_type;
1940 
1941     switch (packet->qp->ibqp.qp_type) {
1942     case IB_QPT_UC:
1943         rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
1944         rqpn = qp->remote_qpn;
1945         svc_type = IB_CC_SVCTYPE_UC;
1946         break;
1947     case IB_QPT_RC:
1948         rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
1949         rqpn = qp->remote_qpn;
1950         svc_type = IB_CC_SVCTYPE_RC;
1951         break;
1952     case IB_QPT_SMI:
1953     case IB_QPT_GSI:
1954     case IB_QPT_UD:
1955         svc_type = IB_CC_SVCTYPE_UD;
1956         break;
1957     default:
1958         ibp->rvp.n_pkt_drops++;
1959         return;
1960     }
1961 
1962     sc5 = hfi1_9B_get_sc5(hdr, packet->rhf);
1963     sl = ibp->sc_to_sl[sc5];
1964     lqpn = qp->ibqp.qp_num;
1965 
1966     process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
1967 }
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