hw/hfi1/user_sdma.h

0001 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
0002 /*
0003  * Copyright(c) 2020 - Cornelis Networks, Inc.
0004  * Copyright(c) 2015 - 2018 Intel Corporation.
0005  */
0006 #ifndef _HFI1_USER_SDMA_H
0007 #define _HFI1_USER_SDMA_H
0008
0009 #include <linux/device.h>
0010 #include <linux/wait.h>
0011
0012 #include "common.h"
0013 #include "iowait.h"
0014 #include "user_exp_rcv.h"
0015 #include "mmu_rb.h"
0016
0017 /* The maximum number of Data io vectors per message/request */
0018 #define MAX_VECTORS_PER_REQ 8
0019 /*
0020  * Maximum number of packet to send from each message/request
0021  * before moving to the next one.
0022  */
0023 #define MAX_PKTS_PER_QUEUE 16
0024
0025 #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
0026
0027 #define req_opcode(x) \
0028     (((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
0029 #define req_version(x) \
0030     (((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
0031 #define req_iovcnt(x) \
0032     (((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK)
0033
0034 /* Number of BTH.PSN bits used for sequence number in expected rcvs */
0035 #define BTH_SEQ_MASK 0x7ffull
0036
0037 #define AHG_KDETH_INTR_SHIFT 12
0038 #define AHG_KDETH_SH_SHIFT   13
0039 #define AHG_KDETH_ARRAY_SIZE  9
0040
0041 #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
0042 #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
0043
0044 /**
0045  * Build an SDMA AHG header update descriptor and save it to an array.
0046  * @arr        - Array to save the descriptor to.
0047  * @idx        - Index of the array at which the descriptor will be saved.
0048  * @array_size - Size of the array arr.
0049  * @dw         - Update index into the header in DWs.
0050  * @bit        - Start bit.
0051  * @width      - Field width.
0052  * @value      - 16 bits of immediate data to write into the field.
0053  * Returns -ERANGE if idx is invalid. If successful, returns the next index
0054  * (idx + 1) of the array to be used for the next descriptor.
0055  */
0056 static inline int ahg_header_set(u32 *arr, int idx, size_t array_size,
0057                  u8 dw, u8 bit, u8 width, u16 value)
0058 {
0059     if ((size_t)idx >= array_size)
0060         return -ERANGE;
0061     arr[idx++] = sdma_build_ahg_descriptor(value, dw, bit, width);
0062     return idx;
0063 }
0064
0065 /* Tx request flag bits */
0066 #define TXREQ_FLAGS_REQ_ACK   BIT(0)      /* Set the ACK bit in the header */
0067 #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */
0068
0069 enum pkt_q_sdma_state {
0070     SDMA_PKT_Q_ACTIVE,
0071     SDMA_PKT_Q_DEFERRED,
0072 };
0073
0074 #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */
0075
0076 #define SDMA_DBG(req, fmt, ...)                  \
0077     hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
0078          (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \
0079          ##__VA_ARGS__)
0080
0081 struct hfi1_user_sdma_pkt_q {
0082     u16 ctxt;
0083     u16 subctxt;
0084     u16 n_max_reqs;
0085     atomic_t n_reqs;
0086     u16 reqidx;
0087     struct hfi1_devdata *dd;
0088     struct kmem_cache *txreq_cache;
0089     struct user_sdma_request *reqs;
0090     unsigned long *req_in_use;
0091     struct iowait busy;
0092     enum pkt_q_sdma_state state;
0093     wait_queue_head_t wait;
0094     unsigned long unpinned;
0095     struct mmu_rb_handler *handler;
0096     atomic_t n_locked;
0097 };
0098
0099 struct hfi1_user_sdma_comp_q {
0100     u16 nentries;
0101     struct hfi1_sdma_comp_entry *comps;
0102 };
0103
0104 struct sdma_mmu_node {
0105     struct mmu_rb_node rb;
0106     struct hfi1_user_sdma_pkt_q *pq;
0107     atomic_t refcount;
0108     struct page **pages;
0109     unsigned int npages;
0110 };
0111
0112 struct user_sdma_iovec {
0113     struct list_head list;
0114     struct iovec iov;
0115     /* number of pages in this vector */
0116     unsigned int npages;
0117     /* array of pinned pages for this vector */
0118     struct page **pages;
0119     /*
0120      * offset into the virtual address space of the vector at
0121      * which we last left off.
0122      */
0123     u64 offset;
0124     struct sdma_mmu_node *node;
0125 };
0126
0127 /* evict operation argument */
0128 struct evict_data {
0129     u32 cleared;    /* count evicted so far */
0130     u32 target; /* target count to evict */
0131 };
0132
0133 struct user_sdma_request {
0134     /* This is the original header from user space */
0135     struct hfi1_pkt_header hdr;
0136
0137     /* Read mostly fields */
0138     struct hfi1_user_sdma_pkt_q *pq ____cacheline_aligned_in_smp;
0139     struct hfi1_user_sdma_comp_q *cq;
0140     /*
0141      * Pointer to the SDMA engine for this request.
0142      * Since different request could be on different VLs,
0143      * each request will need it's own engine pointer.
0144      */
0145     struct sdma_engine *sde;
0146     struct sdma_req_info info;
0147     /* TID array values copied from the tid_iov vector */
0148     u32 *tids;
0149     /* total length of the data in the request */
0150     u32 data_len;
0151     /* number of elements copied to the tids array */
0152     u16 n_tids;
0153     /*
0154      * We copy the iovs for this request (based on
0155      * info.iovcnt). These are only the data vectors
0156      */
0157     u8 data_iovs;
0158     s8 ahg_idx;
0159
0160     /* Writeable fields shared with interrupt */
0161     u16 seqcomp ____cacheline_aligned_in_smp;
0162     u16 seqsubmitted;
0163
0164     /* Send side fields */
0165     struct list_head txps ____cacheline_aligned_in_smp;
0166     u16 seqnum;
0167     /*
0168      * KDETH.OFFSET (TID) field
0169      * The offset can cover multiple packets, depending on the
0170      * size of the TID entry.
0171      */
0172     u32 tidoffset;
0173     /*
0174      * KDETH.Offset (Eager) field
0175      * We need to remember the initial value so the headers
0176      * can be updated properly.
0177      */
0178     u32 koffset;
0179     u32 sent;
0180     /* TID index copied from the tid_iov vector */
0181     u16 tididx;
0182     /* progress index moving along the iovs array */
0183     u8 iov_idx;
0184     u8 has_error;
0185
0186     struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ];
0187 } ____cacheline_aligned_in_smp;
0188
0189 /*
0190  * A single txreq could span up to 3 physical pages when the MTU
0191  * is sufficiently large (> 4K). Each of the IOV pointers also
0192  * needs it's own set of flags so the vector has been handled
0193  * independently of each other.
0194  */
0195 struct user_sdma_txreq {
0196     /* Packet header for the txreq */
0197     struct hfi1_pkt_header hdr;
0198     struct sdma_txreq txreq;
0199     struct list_head list;
0200     struct user_sdma_request *req;
0201     u16 flags;
0202     u16 seqnum;
0203 };
0204
0205 int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt,
0206                 struct hfi1_filedata *fd);
0207 int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd,
0208                    struct hfi1_ctxtdata *uctxt);
0209 int hfi1_user_sdma_process_request(struct hfi1_filedata *fd,
0210                    struct iovec *iovec, unsigned long dim,
0211                    unsigned long *count);
0212
0213 static inline struct mm_struct *mm_from_sdma_node(struct sdma_mmu_node *node)
0214 {
0215     return node->rb.handler->mn.mm;
0216 }
0217
0218 #endif /* _HFI1_USER_SDMA_H */