hw/hfi1/platform.h

0001 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
0002 /*
0003  * Copyright(c) 2015, 2016 Intel Corporation.
0004  */
0005
0006 #ifndef __PLATFORM_H
0007 #define __PLATFORM_H
0008
0009 #define METADATA_TABLE_FIELD_START_SHIFT        0
0010 #define METADATA_TABLE_FIELD_START_LEN_BITS     15
0011 #define METADATA_TABLE_FIELD_LEN_SHIFT          16
0012 #define METADATA_TABLE_FIELD_LEN_LEN_BITS       16
0013
0014 /* Header structure */
0015 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT         0
0016 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS      6
0017 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT       16
0018 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS        12
0019 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT         28
0020 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS      4
0021
0022 enum platform_config_table_type_encoding {
0023     PLATFORM_CONFIG_TABLE_RESERVED,
0024     PLATFORM_CONFIG_SYSTEM_TABLE,
0025     PLATFORM_CONFIG_PORT_TABLE,
0026     PLATFORM_CONFIG_RX_PRESET_TABLE,
0027     PLATFORM_CONFIG_TX_PRESET_TABLE,
0028     PLATFORM_CONFIG_QSFP_ATTEN_TABLE,
0029     PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE,
0030     PLATFORM_CONFIG_TABLE_MAX
0031 };
0032
0033 enum platform_config_system_table_fields {
0034     SYSTEM_TABLE_RESERVED,
0035     SYSTEM_TABLE_NODE_STRING,
0036     SYSTEM_TABLE_SYSTEM_IMAGE_GUID,
0037     SYSTEM_TABLE_NODE_GUID,
0038     SYSTEM_TABLE_REVISION,
0039     SYSTEM_TABLE_VENDOR_OUI,
0040     SYSTEM_TABLE_META_VERSION,
0041     SYSTEM_TABLE_DEVICE_ID,
0042     SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP,
0043     SYSTEM_TABLE_QSFP_POWER_CLASS_MAX,
0044     SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G,
0045     SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
0046     SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT,
0047     SYSTEM_TABLE_MAX
0048 };
0049
0050 enum platform_config_port_table_fields {
0051     PORT_TABLE_RESERVED,
0052     PORT_TABLE_PORT_TYPE,
0053     PORT_TABLE_LOCAL_ATTEN_12G,
0054     PORT_TABLE_LOCAL_ATTEN_25G,
0055     PORT_TABLE_LINK_SPEED_SUPPORTED,
0056     PORT_TABLE_LINK_WIDTH_SUPPORTED,
0057     PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED,
0058     PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED,
0059     PORT_TABLE_VL_CAP,
0060     PORT_TABLE_MTU_CAP,
0061     PORT_TABLE_TX_LANE_ENABLE_MASK,
0062     PORT_TABLE_LOCAL_MAX_TIMEOUT,
0063     PORT_TABLE_REMOTE_ATTEN_12G,
0064     PORT_TABLE_REMOTE_ATTEN_25G,
0065     PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
0066     PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
0067     PORT_TABLE_RX_PRESET_IDX,
0068     PORT_TABLE_CABLE_REACH_CLASS,
0069     PORT_TABLE_MAX
0070 };
0071
0072 enum platform_config_rx_preset_table_fields {
0073     RX_PRESET_TABLE_RESERVED,
0074     RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
0075     RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
0076     RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
0077     RX_PRESET_TABLE_QSFP_RX_CDR,
0078     RX_PRESET_TABLE_QSFP_RX_EMP,
0079     RX_PRESET_TABLE_QSFP_RX_AMP,
0080     RX_PRESET_TABLE_MAX
0081 };
0082
0083 enum platform_config_tx_preset_table_fields {
0084     TX_PRESET_TABLE_RESERVED,
0085     TX_PRESET_TABLE_PRECUR,
0086     TX_PRESET_TABLE_ATTN,
0087     TX_PRESET_TABLE_POSTCUR,
0088     TX_PRESET_TABLE_QSFP_TX_CDR_APPLY,
0089     TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
0090     TX_PRESET_TABLE_QSFP_TX_CDR,
0091     TX_PRESET_TABLE_QSFP_TX_EQ,
0092     TX_PRESET_TABLE_MAX
0093 };
0094
0095 enum platform_config_qsfp_attn_table_fields {
0096     QSFP_ATTEN_TABLE_RESERVED,
0097     QSFP_ATTEN_TABLE_TX_PRESET_IDX,
0098     QSFP_ATTEN_TABLE_RX_PRESET_IDX,
0099     QSFP_ATTEN_TABLE_MAX
0100 };
0101
0102 enum platform_config_variable_settings_table_fields {
0103     VARIABLE_SETTINGS_TABLE_RESERVED,
0104     VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX,
0105     VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX,
0106     VARIABLE_SETTINGS_TABLE_MAX
0107 };
0108
0109 struct platform_config {
0110     size_t size;
0111     const u8 *data;
0112 };
0113
0114 struct platform_config_data {
0115     u32 *table;
0116     u32 *table_metadata;
0117     u32 num_table;
0118 };
0119
0120 /*
0121  * This struct acts as a quick reference into the platform_data binary image
0122  * and is populated by parse_platform_config(...) depending on the specific
0123  * META_VERSION
0124  */
0125 struct platform_config_cache {
0126     u8  cache_valid;
0127     struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
0128 };
0129
0130 /* This section defines default values and encodings for the
0131  * fields defined for each table above
0132  */
0133
0134 /*
0135  * =====================================================
0136  *  System table encodings
0137  * =====================================================
0138  */
0139 #define PLATFORM_CONFIG_MAGIC_NUM       0x3d4f5041
0140 #define PLATFORM_CONFIG_MAGIC_NUMBER_LEN    4
0141
0142 /*
0143  * These power classes are the same as defined in SFF 8636 spec rev 2.4
0144  * describing byte 129 in table 6-16, except enumerated in a different order
0145  */
0146 enum platform_config_qsfp_power_class_encoding {
0147     QSFP_POWER_CLASS_1 = 1,
0148     QSFP_POWER_CLASS_2,
0149     QSFP_POWER_CLASS_3,
0150     QSFP_POWER_CLASS_4,
0151     QSFP_POWER_CLASS_5,
0152     QSFP_POWER_CLASS_6,
0153     QSFP_POWER_CLASS_7
0154 };
0155
0156 /*
0157  * ====================================================
0158  *  Port table encodings
0159  * ====================================================
0160  */
0161 enum platform_config_port_type_encoding {
0162     PORT_TYPE_UNKNOWN,
0163     PORT_TYPE_DISCONNECTED,
0164     PORT_TYPE_FIXED,
0165     PORT_TYPE_VARIABLE,
0166     PORT_TYPE_QSFP,
0167     PORT_TYPE_MAX
0168 };
0169
0170 enum platform_config_link_speed_supported_encoding {
0171     LINK_SPEED_SUPP_12G = 1,
0172     LINK_SPEED_SUPP_25G,
0173     LINK_SPEED_SUPP_12G_25G,
0174     LINK_SPEED_SUPP_MAX
0175 };
0176
0177 /*
0178  * This is a subset (not strict) of the link downgrades
0179  * supported. The link downgrades supported are expected
0180  * to be supplied to the driver by another entity such as
0181  * the fabric manager
0182  */
0183 enum platform_config_link_width_supported_encoding {
0184     LINK_WIDTH_SUPP_1X = 1,
0185     LINK_WIDTH_SUPP_2X,
0186     LINK_WIDTH_SUPP_2X_1X,
0187     LINK_WIDTH_SUPP_3X,
0188     LINK_WIDTH_SUPP_3X_1X,
0189     LINK_WIDTH_SUPP_3X_2X,
0190     LINK_WIDTH_SUPP_3X_2X_1X,
0191     LINK_WIDTH_SUPP_4X,
0192     LINK_WIDTH_SUPP_4X_1X,
0193     LINK_WIDTH_SUPP_4X_2X,
0194     LINK_WIDTH_SUPP_4X_2X_1X,
0195     LINK_WIDTH_SUPP_4X_3X,
0196     LINK_WIDTH_SUPP_4X_3X_1X,
0197     LINK_WIDTH_SUPP_4X_3X_2X,
0198     LINK_WIDTH_SUPP_4X_3X_2X_1X,
0199     LINK_WIDTH_SUPP_MAX
0200 };
0201
0202 enum platform_config_virtual_lane_capability_encoding {
0203     VL_CAP_VL0 = 1,
0204     VL_CAP_VL0_1,
0205     VL_CAP_VL0_2,
0206     VL_CAP_VL0_3,
0207     VL_CAP_VL0_4,
0208     VL_CAP_VL0_5,
0209     VL_CAP_VL0_6,
0210     VL_CAP_VL0_7,
0211     VL_CAP_VL0_8,
0212     VL_CAP_VL0_9,
0213     VL_CAP_VL0_10,
0214     VL_CAP_VL0_11,
0215     VL_CAP_VL0_12,
0216     VL_CAP_VL0_13,
0217     VL_CAP_VL0_14,
0218     VL_CAP_MAX
0219 };
0220
0221 /* Max MTU */
0222 enum platform_config_mtu_capability_encoding {
0223     MTU_CAP_256   = 1,
0224     MTU_CAP_512   = 2,
0225     MTU_CAP_1024  = 3,
0226     MTU_CAP_2048  = 4,
0227     MTU_CAP_4096  = 5,
0228     MTU_CAP_8192  = 6,
0229     MTU_CAP_10240 = 7
0230 };
0231
0232 enum platform_config_local_max_timeout_encoding {
0233     LOCAL_MAX_TIMEOUT_10_MS = 1,
0234     LOCAL_MAX_TIMEOUT_100_MS,
0235     LOCAL_MAX_TIMEOUT_1_S,
0236     LOCAL_MAX_TIMEOUT_10_S,
0237     LOCAL_MAX_TIMEOUT_100_S,
0238     LOCAL_MAX_TIMEOUT_1000_S
0239 };
0240
0241 enum link_tuning_encoding {
0242     OPA_PASSIVE_TUNING,
0243     OPA_ACTIVE_TUNING,
0244     OPA_UNKNOWN_TUNING
0245 };
0246
0247 /*
0248  * Shifts and masks for the link SI tuning values stuffed into the ASIC scratch
0249  * registers for integrated platforms
0250  */
0251 #define PORT0_PORT_TYPE_SHIFT       0
0252 #define PORT0_LOCAL_ATTEN_SHIFT     4
0253 #define PORT0_REMOTE_ATTEN_SHIFT    10
0254 #define PORT0_DEFAULT_ATTEN_SHIFT   32
0255
0256 #define PORT1_PORT_TYPE_SHIFT       16
0257 #define PORT1_LOCAL_ATTEN_SHIFT     20
0258 #define PORT1_REMOTE_ATTEN_SHIFT    26
0259 #define PORT1_DEFAULT_ATTEN_SHIFT   40
0260
0261 #define PORT0_PORT_TYPE_MASK        0xFUL
0262 #define PORT0_LOCAL_ATTEN_MASK      0x3FUL
0263 #define PORT0_REMOTE_ATTEN_MASK     0x3FUL
0264 #define PORT0_DEFAULT_ATTEN_MASK    0xFFUL
0265
0266 #define PORT1_PORT_TYPE_MASK        0xFUL
0267 #define PORT1_LOCAL_ATTEN_MASK      0x3FUL
0268 #define PORT1_REMOTE_ATTEN_MASK     0x3FUL
0269 #define PORT1_DEFAULT_ATTEN_MASK    0xFFUL
0270
0271 #define PORT0_PORT_TYPE_SMASK       (PORT0_PORT_TYPE_MASK << \
0272                      PORT0_PORT_TYPE_SHIFT)
0273 #define PORT0_LOCAL_ATTEN_SMASK     (PORT0_LOCAL_ATTEN_MASK << \
0274                      PORT0_LOCAL_ATTEN_SHIFT)
0275 #define PORT0_REMOTE_ATTEN_SMASK    (PORT0_REMOTE_ATTEN_MASK << \
0276                      PORT0_REMOTE_ATTEN_SHIFT)
0277 #define PORT0_DEFAULT_ATTEN_SMASK   (PORT0_DEFAULT_ATTEN_MASK << \
0278                      PORT0_DEFAULT_ATTEN_SHIFT)
0279
0280 #define PORT1_PORT_TYPE_SMASK       (PORT1_PORT_TYPE_MASK << \
0281                      PORT1_PORT_TYPE_SHIFT)
0282 #define PORT1_LOCAL_ATTEN_SMASK     (PORT1_LOCAL_ATTEN_MASK << \
0283                      PORT1_LOCAL_ATTEN_SHIFT)
0284 #define PORT1_REMOTE_ATTEN_SMASK    (PORT1_REMOTE_ATTEN_MASK << \
0285                      PORT1_REMOTE_ATTEN_SHIFT)
0286 #define PORT1_DEFAULT_ATTEN_SMASK   (PORT1_DEFAULT_ATTEN_MASK << \
0287                      PORT1_DEFAULT_ATTEN_SHIFT)
0288
0289 #define QSFP_MAX_POWER_SHIFT        0
0290 #define TX_NO_EQ_SHIFT          4
0291 #define TX_EQ_SHIFT         25
0292 #define RX_SHIFT            46
0293
0294 #define QSFP_MAX_POWER_MASK     0xFUL
0295 #define TX_NO_EQ_MASK           0x1FFFFFUL
0296 #define TX_EQ_MASK          0x1FFFFFUL
0297 #define RX_MASK             0xFFFFUL
0298
0299 #define QSFP_MAX_POWER_SMASK        (QSFP_MAX_POWER_MASK << \
0300                      QSFP_MAX_POWER_SHIFT)
0301 #define TX_NO_EQ_SMASK          (TX_NO_EQ_MASK << TX_NO_EQ_SHIFT)
0302 #define TX_EQ_SMASK         (TX_EQ_MASK << TX_EQ_SHIFT)
0303 #define RX_SMASK            (RX_MASK << RX_SHIFT)
0304
0305 #define TX_PRECUR_SHIFT         0
0306 #define TX_ATTN_SHIFT           4
0307 #define QSFP_TX_CDR_APPLY_SHIFT     9
0308 #define QSFP_TX_EQ_APPLY_SHIFT      10
0309 #define QSFP_TX_CDR_SHIFT       11
0310 #define QSFP_TX_EQ_SHIFT        12
0311 #define TX_POSTCUR_SHIFT        16
0312
0313 #define TX_PRECUR_MASK          0xFUL
0314 #define TX_ATTN_MASK            0x1FUL
0315 #define QSFP_TX_CDR_APPLY_MASK      0x1UL
0316 #define QSFP_TX_EQ_APPLY_MASK       0x1UL
0317 #define QSFP_TX_CDR_MASK        0x1UL
0318 #define QSFP_TX_EQ_MASK         0xFUL
0319 #define TX_POSTCUR_MASK         0x1FUL
0320
0321 #define TX_PRECUR_SMASK         (TX_PRECUR_MASK << TX_PRECUR_SHIFT)
0322 #define TX_ATTN_SMASK           (TX_ATTN_MASK << TX_ATTN_SHIFT)
0323 #define QSFP_TX_CDR_APPLY_SMASK     (QSFP_TX_CDR_APPLY_MASK << \
0324                      QSFP_TX_CDR_APPLY_SHIFT)
0325 #define QSFP_TX_EQ_APPLY_SMASK      (QSFP_TX_EQ_APPLY_MASK << \
0326                      QSFP_TX_EQ_APPLY_SHIFT)
0327 #define QSFP_TX_CDR_SMASK       (QSFP_TX_CDR_MASK << QSFP_TX_CDR_SHIFT)
0328 #define QSFP_TX_EQ_SMASK        (QSFP_TX_EQ_MASK << QSFP_TX_EQ_SHIFT)
0329 #define TX_POSTCUR_SMASK        (TX_POSTCUR_MASK << TX_POSTCUR_SHIFT)
0330
0331 #define QSFP_RX_CDR_APPLY_SHIFT     0
0332 #define QSFP_RX_EMP_APPLY_SHIFT     1
0333 #define QSFP_RX_AMP_APPLY_SHIFT     2
0334 #define QSFP_RX_CDR_SHIFT       3
0335 #define QSFP_RX_EMP_SHIFT       4
0336 #define QSFP_RX_AMP_SHIFT       8
0337
0338 #define QSFP_RX_CDR_APPLY_MASK      0x1UL
0339 #define QSFP_RX_EMP_APPLY_MASK      0x1UL
0340 #define QSFP_RX_AMP_APPLY_MASK      0x1UL
0341 #define QSFP_RX_CDR_MASK        0x1UL
0342 #define QSFP_RX_EMP_MASK        0xFUL
0343 #define QSFP_RX_AMP_MASK        0x3UL
0344
0345 #define QSFP_RX_CDR_APPLY_SMASK     (QSFP_RX_CDR_APPLY_MASK << \
0346                      QSFP_RX_CDR_APPLY_SHIFT)
0347 #define QSFP_RX_EMP_APPLY_SMASK     (QSFP_RX_EMP_APPLY_MASK << \
0348                      QSFP_RX_EMP_APPLY_SHIFT)
0349 #define QSFP_RX_AMP_APPLY_SMASK     (QSFP_RX_AMP_APPLY_MASK << \
0350                      QSFP_RX_AMP_APPLY_SHIFT)
0351 #define QSFP_RX_CDR_SMASK       (QSFP_RX_CDR_MASK << QSFP_RX_CDR_SHIFT)
0352 #define QSFP_RX_EMP_SMASK       (QSFP_RX_EMP_MASK << QSFP_RX_EMP_SHIFT)
0353 #define QSFP_RX_AMP_SMASK       (QSFP_RX_AMP_MASK << QSFP_RX_AMP_SHIFT)
0354
0355 #define BITMAP_VERSION          1
0356 #define BITMAP_VERSION_SHIFT        44
0357 #define BITMAP_VERSION_MASK     0xFUL
0358 #define BITMAP_VERSION_SMASK        (BITMAP_VERSION_MASK << \
0359                      BITMAP_VERSION_SHIFT)
0360 #define CHECKSUM_SHIFT          48
0361 #define CHECKSUM_MASK           0xFFFFUL
0362 #define CHECKSUM_SMASK          (CHECKSUM_MASK << CHECKSUM_SHIFT)
0363
0364 /* platform.c */
0365 void get_platform_config(struct hfi1_devdata *dd);
0366 void free_platform_config(struct hfi1_devdata *dd);
0367 void get_port_type(struct hfi1_pportdata *ppd);
0368 int set_qsfp_tx(struct hfi1_pportdata *ppd, int on);
0369 void tune_serdes(struct hfi1_pportdata *ppd);
0370
0371 #endif          /*__PLATFORM_H*/