hw/hfi1/pio.h

0001 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
0002 /*
0003  * Copyright(c) 2015-2017 Intel Corporation.
0004  */
0005
0006 #ifndef _PIO_H
0007 #define _PIO_H
0008 /* send context types */
0009 #define SC_KERNEL 0
0010 #define SC_VL15   1
0011 #define SC_ACK    2
0012 #define SC_USER   3 /* must be the last one: it may take all left */
0013 #define SC_MAX    4 /* count of send context types */
0014
0015 /* invalid send context index */
0016 #define INVALID_SCI 0xff
0017
0018 /* PIO buffer release callback function */
0019 typedef void (*pio_release_cb)(void *arg, int code);
0020
0021 /* PIO release codes - in bits, as there could more than one that apply */
0022 #define PRC_OK      0   /* no known error */
0023 #define PRC_STATUS_ERR  0x01    /* credit return due to status error */
0024 #define PRC_PBC     0x02    /* credit return due to PBC */
0025 #define PRC_THRESHOLD   0x04    /* credit return due to threshold */
0026 #define PRC_FILL_ERR    0x08    /* credit return due fill error */
0027 #define PRC_FORCE   0x10    /* credit return due credit force */
0028 #define PRC_SC_DISABLE  0x20    /* clean-up after a context disable */
0029
0030 /* byte helper */
0031 union mix {
0032     u64 val64;
0033     u32 val32[2];
0034     u8  val8[8];
0035 };
0036
0037 /* an allocated PIO buffer */
0038 struct pio_buf {
0039     struct send_context *sc;/* back pointer to owning send context */
0040     pio_release_cb cb;  /* called when the buffer is released */
0041     void *arg;      /* argument for cb */
0042     void __iomem *start;    /* buffer start address */
0043     void __iomem *end;  /* context end address */
0044     unsigned long sent_at;  /* buffer is sent when <= free */
0045     union mix carry;    /* pending unwritten bytes */
0046     u16 qw_written;     /* QW written so far */
0047     u8 carry_bytes; /* number of valid bytes in carry */
0048 };
0049
0050 /* cache line aligned pio buffer array */
0051 union pio_shadow_ring {
0052     struct pio_buf pbuf;
0053 } ____cacheline_aligned;
0054
0055 /* per-NUMA send context */
0056 struct send_context {
0057     /* read-only after init */
0058     struct hfi1_devdata *dd;        /* device */
0059     union pio_shadow_ring *sr;  /* shadow ring */
0060     void __iomem *base_addr;    /* start of PIO memory */
0061     u32 __percpu *buffers_allocated;/* count of buffers allocated */
0062     u32 size;           /* context size, in bytes */
0063
0064     int node;           /* context home node */
0065     u32 sr_size;            /* size of the shadow ring */
0066     u16 flags;          /* flags */
0067     u8  type;           /* context type */
0068     u8  sw_index;           /* software index number */
0069     u8  hw_context;         /* hardware context number */
0070     u8  group;          /* credit return group */
0071
0072     /* allocator fields */
0073     spinlock_t alloc_lock ____cacheline_aligned_in_smp;
0074     u32 sr_head;            /* shadow ring head */
0075     unsigned long fill;     /* official alloc count */
0076     unsigned long alloc_free;   /* copy of free (less cache thrash) */
0077     u32 fill_wrap;          /* tracks fill within ring */
0078     u32 credits;            /* number of blocks in context */
0079     /* adding a new field here would make it part of this cacheline */
0080
0081     /* releaser fields */
0082     spinlock_t release_lock ____cacheline_aligned_in_smp;
0083     u32 sr_tail;            /* shadow ring tail */
0084     unsigned long free;     /* official free count */
0085     volatile __le64 *hw_free;   /* HW free counter */
0086     /* list for PIO waiters */
0087     struct list_head piowait  ____cacheline_aligned_in_smp;
0088     seqlock_t waitlock;
0089
0090     spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
0091     u32 credit_intr_count;      /* count of credit intr users */
0092     u64 credit_ctrl;        /* cache for credit control */
0093     wait_queue_head_t halt_wait;    /* wait until kernel sees interrupt */
0094     struct work_struct halt_work;   /* halted context work queue entry */
0095 };
0096
0097 /* send context flags */
0098 #define SCF_ENABLED 0x01
0099 #define SCF_IN_FREE 0x02
0100 #define SCF_HALTED  0x04
0101 #define SCF_FROZEN  0x08
0102 #define SCF_LINK_DOWN 0x10
0103
0104 struct send_context_info {
0105     struct send_context *sc;    /* allocated working context */
0106     u16 allocated;          /* has this been allocated? */
0107     u16 type;           /* context type */
0108     u16 base;           /* base in PIO array */
0109     u16 credits;            /* size in PIO array */
0110 };
0111
0112 /* DMA credit return, index is always (context & 0x7) */
0113 struct credit_return {
0114     volatile __le64 cr[8];
0115 };
0116
0117 /* NUMA indexed credit return array */
0118 struct credit_return_base {
0119     struct credit_return *va;
0120     dma_addr_t dma;
0121 };
0122
0123 /* send context configuration sizes (one per type) */
0124 struct sc_config_sizes {
0125     short int size;
0126     short int count;
0127 };
0128
0129 /*
0130  * The diagram below details the relationship of the mapping structures
0131  *
0132  * Since the mapping now allows for non-uniform send contexts per vl, the
0133  * number of send contexts for a vl is either the vl_scontexts[vl] or
0134  * a computation based on num_kernel_send_contexts/num_vls:
0135  *
0136  * For example:
0137  * nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls
0138  *
0139  * n = roundup to next highest power of 2 using nactual
0140  *
0141  * In the case where there are num_kernel_send_contexts/num_vls doesn't divide
0142  * evenly, the extras are added from the last vl downward.
0143  *
0144  * For the case where n > nactual, the send contexts are assigned
0145  * in a round robin fashion wrapping back to the first send context
0146  * for a particular vl.
0147  *
0148  *               dd->pio_map
0149  *                    |                                   pio_map_elem[0]
0150  *                    |                                +--------------------+
0151  *                    v                                |       mask         |
0152  *               pio_vl_map                            |--------------------|
0153  *      +--------------------------+                   | ksc[0] -> sc 1     |
0154  *      |    list (RCU)            |                   |--------------------|
0155  *      |--------------------------|                 ->| ksc[1] -> sc 2     |
0156  *      |    mask                  |              --/  |--------------------|
0157  *      |--------------------------|            -/     |        *           |
0158  *      |    actual_vls (max 8)    |          -/       |--------------------|
0159  *      |--------------------------|       --/         | ksc[n-1] -> sc n   |
0160  *      |    vls (max 8)           |     -/            +--------------------+
0161  *      |--------------------------|  --/
0162  *      |    map[0]                |-/
0163  *      |--------------------------|                   +--------------------+
0164  *      |    map[1]                |---                |       mask         |
0165  *      |--------------------------|   \----           |--------------------|
0166  *      |           *              |        \--        | ksc[0] -> sc 1+n   |
0167  *      |           *              |           \----   |--------------------|
0168  *      |           *              |                \->| ksc[1] -> sc 2+n   |
0169  *      |--------------------------|                   |--------------------|
0170  *      |   map[vls - 1]           |-                  |         *          |
0171  *      +--------------------------+ \-                |--------------------|
0172  *                                     \-              | ksc[m-1] -> sc m+n |
0173  *                                       \             +--------------------+
0174  *                                        \-
0175  *                                          \
0176  *                                           \-        +----------------------+
0177  *                                             \-      |       mask           |
0178  *                                               \     |----------------------|
0179  *                                                \-   | ksc[0] -> sc 1+m+n   |
0180  *                                                  \- |----------------------|
0181  *                                                    >| ksc[1] -> sc 2+m+n   |
0182  *                                                     |----------------------|
0183  *                                                     |         *            |
0184  *                                                     |----------------------|
0185  *                                                     | ksc[o-1] -> sc o+m+n |
0186  *                                                     +----------------------+
0187  *
0188  */
0189
0190 /* Initial number of send contexts per VL */
0191 #define INIT_SC_PER_VL 2
0192
0193 /*
0194  * struct pio_map_elem - mapping for a vl
0195  * @mask - selector mask
0196  * @ksc - array of kernel send contexts for this vl
0197  *
0198  * The mask is used to "mod" the selector to
0199  * produce index into the trailing array of
0200  * kscs
0201  */
0202 struct pio_map_elem {
0203     u32 mask;
0204     struct send_context *ksc[];
0205 };
0206
0207 /*
0208  * struct pio_vl_map - mapping for a vl
0209  * @list - rcu head for free callback
0210  * @mask - vl mask to "mod" the vl to produce an index to map array
0211  * @actual_vls - number of vls
0212  * @vls - numbers of vls rounded to next power of 2
0213  * @map - array of pio_map_elem entries
0214  *
0215  * This is the parent mapping structure. The trailing members of the
0216  * struct point to pio_map_elem entries, which in turn point to an
0217  * array of kscs for that vl.
0218  */
0219 struct pio_vl_map {
0220     struct rcu_head list;
0221     u32 mask;
0222     u8 actual_vls;
0223     u8 vls;
0224     struct pio_map_elem *map[];
0225 };
0226
0227 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls,
0228          u8 *vl_scontexts);
0229 void free_pio_map(struct hfi1_devdata *dd);
0230 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
0231                         u32 selector, u8 vl);
0232 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
0233                         u32 selector, u8 sc5);
0234
0235 /* send context functions */
0236 int init_credit_return(struct hfi1_devdata *dd);
0237 void free_credit_return(struct hfi1_devdata *dd);
0238 int init_sc_pools_and_sizes(struct hfi1_devdata *dd);
0239 int init_send_contexts(struct hfi1_devdata *dd);
0240 int init_pervl_scs(struct hfi1_devdata *dd);
0241 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
0242                   uint hdrqentsize, int numa);
0243 void sc_free(struct send_context *sc);
0244 int sc_enable(struct send_context *sc);
0245 void sc_disable(struct send_context *sc);
0246 int sc_restart(struct send_context *sc);
0247 void sc_return_credits(struct send_context *sc);
0248 void sc_flush(struct send_context *sc);
0249 void sc_drop(struct send_context *sc);
0250 void sc_stop(struct send_context *sc, int bit);
0251 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
0252                 pio_release_cb cb, void *arg);
0253 void sc_release_update(struct send_context *sc);
0254 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
0255 void sc_add_credit_return_intr(struct send_context *sc);
0256 void sc_del_credit_return_intr(struct send_context *sc);
0257 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold);
0258 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent);
0259 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize);
0260 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint);
0261 void sc_wait(struct hfi1_devdata *dd);
0262 void set_pio_integrity(struct send_context *sc);
0263
0264 /* support functions */
0265 void pio_reset_all(struct hfi1_devdata *dd);
0266 void pio_freeze(struct hfi1_devdata *dd);
0267 void pio_kernel_unfreeze(struct hfi1_devdata *dd);
0268 void pio_kernel_linkup(struct hfi1_devdata *dd);
0269
0270 /* global PIO send control operations */
0271 #define PSC_GLOBAL_ENABLE 0
0272 #define PSC_GLOBAL_DISABLE 1
0273 #define PSC_GLOBAL_VLARB_ENABLE 2
0274 #define PSC_GLOBAL_VLARB_DISABLE 3
0275 #define PSC_CM_RESET 4
0276 #define PSC_DATA_VL_ENABLE 5
0277 #define PSC_DATA_VL_DISABLE 6
0278
0279 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl);
0280 void pio_send_control(struct hfi1_devdata *dd, int op);
0281
0282 /* PIO copy routines */
0283 void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
0284           const void *from, size_t count);
0285 void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
0286             const void *from, size_t nbytes);
0287 void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
0288 void seg_pio_copy_end(struct pio_buf *pbuf);
0289
0290 void seqfile_dump_sci(struct seq_file *s, u32 i,
0291               struct send_context_info *sci);
0292
0293 #endif /* _PIO_H */