hw/efa/efa_admin_defs.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
0002 /*
0003  * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
0004  */
0005
0006 #ifndef _EFA_ADMIN_H_
0007 #define _EFA_ADMIN_H_
0008
0009 enum efa_admin_aq_completion_status {
0010     EFA_ADMIN_SUCCESS                           = 0,
0011     EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
0012     EFA_ADMIN_BAD_OPCODE                        = 2,
0013     EFA_ADMIN_UNSUPPORTED_OPCODE                = 3,
0014     EFA_ADMIN_MALFORMED_REQUEST                 = 4,
0015     /* Additional status is provided in ACQ entry extended_status */
0016     EFA_ADMIN_ILLEGAL_PARAMETER                 = 5,
0017     EFA_ADMIN_UNKNOWN_ERROR                     = 6,
0018     EFA_ADMIN_RESOURCE_BUSY                     = 7,
0019 };
0020
0021 struct efa_admin_aq_common_desc {
0022     /*
0023      * 11:0 : command_id
0024      * 15:12 : reserved12
0025      */
0026     u16 command_id;
0027
0028     /* as appears in efa_admin_aq_opcode */
0029     u8 opcode;
0030
0031     /*
0032      * 0 : phase
0033      * 1 : ctrl_data - control buffer address valid
0034      * 2 : ctrl_data_indirect - control buffer address
0035      *    points to list of pages with addresses of control
0036      *    buffers
0037      * 7:3 : reserved3
0038      */
0039     u8 flags;
0040 };
0041
0042 /*
0043  * used in efa_admin_aq_entry. Can point directly to control data, or to a
0044  * page list chunk. Used also at the end of indirect mode page list chunks,
0045  * for chaining.
0046  */
0047 struct efa_admin_ctrl_buff_info {
0048     u32 length;
0049
0050     struct efa_common_mem_addr address;
0051 };
0052
0053 struct efa_admin_aq_entry {
0054     struct efa_admin_aq_common_desc aq_common_descriptor;
0055
0056     union {
0057         u32 inline_data_w1[3];
0058
0059         struct efa_admin_ctrl_buff_info control_buffer;
0060     } u;
0061
0062     u32 inline_data_w4[12];
0063 };
0064
0065 struct efa_admin_acq_common_desc {
0066     /*
0067      * command identifier to associate it with the aq descriptor
0068      * 11:0 : command_id
0069      * 15:12 : reserved12
0070      */
0071     u16 command;
0072
0073     u8 status;
0074
0075     /*
0076      * 0 : phase
0077      * 7:1 : reserved1
0078      */
0079     u8 flags;
0080
0081     u16 extended_status;
0082
0083     /*
0084      * indicates to the driver which AQ entry has been consumed by the
0085      * device and could be reused
0086      */
0087     u16 sq_head_indx;
0088 };
0089
0090 struct efa_admin_acq_entry {
0091     struct efa_admin_acq_common_desc acq_common_descriptor;
0092
0093     u32 response_specific_data[14];
0094 };
0095
0096 struct efa_admin_aenq_common_desc {
0097     u16 group;
0098
0099     u16 syndrom;
0100
0101     /*
0102      * 0 : phase
0103      * 7:1 : reserved - MBZ
0104      */
0105     u8 flags;
0106
0107     u8 reserved1[3];
0108
0109     u32 timestamp_low;
0110
0111     u32 timestamp_high;
0112 };
0113
0114 struct efa_admin_aenq_entry {
0115     struct efa_admin_aenq_common_desc aenq_common_desc;
0116
0117     /* command specific inline data */
0118     u32 inline_data_w4[12];
0119 };
0120
0121 enum efa_admin_eqe_event_type {
0122     EFA_ADMIN_EQE_EVENT_TYPE_COMPLETION         = 0,
0123 };
0124
0125 /* Completion event */
0126 struct efa_admin_comp_event {
0127     /* CQ number */
0128     u16 cqn;
0129
0130     /* MBZ */
0131     u16 reserved;
0132
0133     /* MBZ */
0134     u32 reserved2;
0135 };
0136
0137 /* Event Queue Element */
0138 struct efa_admin_eqe {
0139     /*
0140      * 0 : phase
0141      * 8:1 : event_type - Event type
0142      * 31:9 : reserved - MBZ
0143      */
0144     u32 common;
0145
0146     /* MBZ */
0147     u32 reserved;
0148
0149     union {
0150         /* Event data */
0151         u32 event_data[2];
0152
0153         /* Completion Event */
0154         struct efa_admin_comp_event comp_event;
0155     } u;
0156 };
0157
0158 /* aq_common_desc */
0159 #define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
0160 #define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
0161 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
0162 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
0163
0164 /* acq_common_desc */
0165 #define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
0166 #define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
0167
0168 /* aenq_common_desc */
0169 #define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
0170
0171 /* eqe */
0172 #define EFA_ADMIN_EQE_PHASE_MASK                            BIT(0)
0173 #define EFA_ADMIN_EQE_EVENT_TYPE_MASK                       GENMASK(8, 1)
0174
0175 #endif /* _EFA_ADMIN_H_ */