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0001 /*
0002  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *      - Redistributions in binary form must reproduce the above
0018  *        copyright notice, this list of conditions and the following
0019  *        disclaimer in the documentation and/or other materials
0020  *        provided with the distribution.
0021  *
0022  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0023  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0024  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0025  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0026  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0027  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0028  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0029  * SOFTWARE.
0030  */
0031 #ifndef _T4FW_RI_API_H_
0032 #define _T4FW_RI_API_H_
0033 
0034 #include "t4fw_api.h"
0035 
0036 enum fw_ri_wr_opcode {
0037     FW_RI_RDMA_WRITE        = 0x0,  /* IETF RDMAP v1.0 ... */
0038     FW_RI_READ_REQ          = 0x1,
0039     FW_RI_READ_RESP         = 0x2,
0040     FW_RI_SEND          = 0x3,
0041     FW_RI_SEND_WITH_INV     = 0x4,
0042     FW_RI_SEND_WITH_SE      = 0x5,
0043     FW_RI_SEND_WITH_SE_INV      = 0x6,
0044     FW_RI_TERMINATE         = 0x7,
0045     FW_RI_RDMA_INIT         = 0x8,  /* CHELSIO RI specific ... */
0046     FW_RI_BIND_MW           = 0x9,
0047     FW_RI_FAST_REGISTER     = 0xa,
0048     FW_RI_LOCAL_INV         = 0xb,
0049     FW_RI_QP_MODIFY         = 0xc,
0050     FW_RI_BYPASS            = 0xd,
0051     FW_RI_RECEIVE           = 0xe,
0052 
0053     FW_RI_SGE_EC_CR_RETURN      = 0xf,
0054     FW_RI_WRITE_IMMEDIATE           = FW_RI_RDMA_INIT
0055 };
0056 
0057 enum fw_ri_wr_flags {
0058     FW_RI_COMPLETION_FLAG       = 0x01,
0059     FW_RI_NOTIFICATION_FLAG     = 0x02,
0060     FW_RI_SOLICITED_EVENT_FLAG  = 0x04,
0061     FW_RI_READ_FENCE_FLAG       = 0x08,
0062     FW_RI_LOCAL_FENCE_FLAG      = 0x10,
0063     FW_RI_RDMA_READ_INVALIDATE  = 0x20,
0064     FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
0065 };
0066 
0067 enum fw_ri_mpa_attrs {
0068     FW_RI_MPA_RX_MARKER_ENABLE  = 0x01,
0069     FW_RI_MPA_TX_MARKER_ENABLE  = 0x02,
0070     FW_RI_MPA_CRC_ENABLE        = 0x04,
0071     FW_RI_MPA_IETF_ENABLE       = 0x08
0072 };
0073 
0074 enum fw_ri_qp_caps {
0075     FW_RI_QP_RDMA_READ_ENABLE   = 0x01,
0076     FW_RI_QP_RDMA_WRITE_ENABLE  = 0x02,
0077     FW_RI_QP_BIND_ENABLE        = 0x04,
0078     FW_RI_QP_FAST_REGISTER_ENABLE   = 0x08,
0079     FW_RI_QP_STAG0_ENABLE       = 0x10
0080 };
0081 
0082 enum fw_ri_addr_type {
0083     FW_RI_ZERO_BASED_TO     = 0x00,
0084     FW_RI_VA_BASED_TO       = 0x01
0085 };
0086 
0087 enum fw_ri_mem_perms {
0088     FW_RI_MEM_ACCESS_REM_WRITE  = 0x01,
0089     FW_RI_MEM_ACCESS_REM_READ   = 0x02,
0090     FW_RI_MEM_ACCESS_REM        = 0x03,
0091     FW_RI_MEM_ACCESS_LOCAL_WRITE    = 0x04,
0092     FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
0093     FW_RI_MEM_ACCESS_LOCAL      = 0x0C
0094 };
0095 
0096 enum fw_ri_stag_type {
0097     FW_RI_STAG_NSMR         = 0x00,
0098     FW_RI_STAG_SMR          = 0x01,
0099     FW_RI_STAG_MW           = 0x02,
0100     FW_RI_STAG_MW_RELAXED       = 0x03
0101 };
0102 
0103 enum fw_ri_data_op {
0104     FW_RI_DATA_IMMD         = 0x81,
0105     FW_RI_DATA_DSGL         = 0x82,
0106     FW_RI_DATA_ISGL         = 0x83
0107 };
0108 
0109 enum fw_ri_sgl_depth {
0110     FW_RI_SGL_DEPTH_MAX_SQ      = 16,
0111     FW_RI_SGL_DEPTH_MAX_RQ      = 4
0112 };
0113 
0114 struct fw_ri_dsge_pair {
0115     __be32  len[2];
0116     __be64  addr[2];
0117 };
0118 
0119 struct fw_ri_dsgl {
0120     __u8    op;
0121     __u8    r1;
0122     __be16  nsge;
0123     __be32  len0;
0124     __be64  addr0;
0125 #ifndef C99_NOT_SUPPORTED
0126     struct fw_ri_dsge_pair sge[];
0127 #endif
0128 };
0129 
0130 struct fw_ri_sge {
0131     __be32 stag;
0132     __be32 len;
0133     __be64 to;
0134 };
0135 
0136 struct fw_ri_isgl {
0137     __u8    op;
0138     __u8    r1;
0139     __be16  nsge;
0140     __be32  r2;
0141 #ifndef C99_NOT_SUPPORTED
0142     struct fw_ri_sge sge[];
0143 #endif
0144 };
0145 
0146 struct fw_ri_immd {
0147     __u8    op;
0148     __u8    r1;
0149     __be16  r2;
0150     __be32  immdlen;
0151 #ifndef C99_NOT_SUPPORTED
0152     __u8    data[];
0153 #endif
0154 };
0155 
0156 struct fw_ri_tpte {
0157     __be32 valid_to_pdid;
0158     __be32 locread_to_qpid;
0159     __be32 nosnoop_pbladdr;
0160     __be32 len_lo;
0161     __be32 va_hi;
0162     __be32 va_lo_fbo;
0163     __be32 dca_mwbcnt_pstag;
0164     __be32 len_hi;
0165 };
0166 
0167 #define FW_RI_TPTE_VALID_S      31
0168 #define FW_RI_TPTE_VALID_M      0x1
0169 #define FW_RI_TPTE_VALID_V(x)       ((x) << FW_RI_TPTE_VALID_S)
0170 #define FW_RI_TPTE_VALID_G(x)       \
0171     (((x) >> FW_RI_TPTE_VALID_S) & FW_RI_TPTE_VALID_M)
0172 #define FW_RI_TPTE_VALID_F      FW_RI_TPTE_VALID_V(1U)
0173 
0174 #define FW_RI_TPTE_STAGKEY_S        23
0175 #define FW_RI_TPTE_STAGKEY_M        0xff
0176 #define FW_RI_TPTE_STAGKEY_V(x)     ((x) << FW_RI_TPTE_STAGKEY_S)
0177 #define FW_RI_TPTE_STAGKEY_G(x)     \
0178     (((x) >> FW_RI_TPTE_STAGKEY_S) & FW_RI_TPTE_STAGKEY_M)
0179 
0180 #define FW_RI_TPTE_STAGSTATE_S      22
0181 #define FW_RI_TPTE_STAGSTATE_M      0x1
0182 #define FW_RI_TPTE_STAGSTATE_V(x)   ((x) << FW_RI_TPTE_STAGSTATE_S)
0183 #define FW_RI_TPTE_STAGSTATE_G(x)   \
0184     (((x) >> FW_RI_TPTE_STAGSTATE_S) & FW_RI_TPTE_STAGSTATE_M)
0185 #define FW_RI_TPTE_STAGSTATE_F      FW_RI_TPTE_STAGSTATE_V(1U)
0186 
0187 #define FW_RI_TPTE_STAGTYPE_S       20
0188 #define FW_RI_TPTE_STAGTYPE_M       0x3
0189 #define FW_RI_TPTE_STAGTYPE_V(x)    ((x) << FW_RI_TPTE_STAGTYPE_S)
0190 #define FW_RI_TPTE_STAGTYPE_G(x)    \
0191     (((x) >> FW_RI_TPTE_STAGTYPE_S) & FW_RI_TPTE_STAGTYPE_M)
0192 
0193 #define FW_RI_TPTE_PDID_S       0
0194 #define FW_RI_TPTE_PDID_M       0xfffff
0195 #define FW_RI_TPTE_PDID_V(x)        ((x) << FW_RI_TPTE_PDID_S)
0196 #define FW_RI_TPTE_PDID_G(x)        \
0197     (((x) >> FW_RI_TPTE_PDID_S) & FW_RI_TPTE_PDID_M)
0198 
0199 #define FW_RI_TPTE_PERM_S       28
0200 #define FW_RI_TPTE_PERM_M       0xf
0201 #define FW_RI_TPTE_PERM_V(x)        ((x) << FW_RI_TPTE_PERM_S)
0202 #define FW_RI_TPTE_PERM_G(x)        \
0203     (((x) >> FW_RI_TPTE_PERM_S) & FW_RI_TPTE_PERM_M)
0204 
0205 #define FW_RI_TPTE_REMINVDIS_S      27
0206 #define FW_RI_TPTE_REMINVDIS_M      0x1
0207 #define FW_RI_TPTE_REMINVDIS_V(x)   ((x) << FW_RI_TPTE_REMINVDIS_S)
0208 #define FW_RI_TPTE_REMINVDIS_G(x)   \
0209     (((x) >> FW_RI_TPTE_REMINVDIS_S) & FW_RI_TPTE_REMINVDIS_M)
0210 #define FW_RI_TPTE_REMINVDIS_F      FW_RI_TPTE_REMINVDIS_V(1U)
0211 
0212 #define FW_RI_TPTE_ADDRTYPE_S       26
0213 #define FW_RI_TPTE_ADDRTYPE_M       1
0214 #define FW_RI_TPTE_ADDRTYPE_V(x)    ((x) << FW_RI_TPTE_ADDRTYPE_S)
0215 #define FW_RI_TPTE_ADDRTYPE_G(x)    \
0216     (((x) >> FW_RI_TPTE_ADDRTYPE_S) & FW_RI_TPTE_ADDRTYPE_M)
0217 #define FW_RI_TPTE_ADDRTYPE_F       FW_RI_TPTE_ADDRTYPE_V(1U)
0218 
0219 #define FW_RI_TPTE_MWBINDEN_S       25
0220 #define FW_RI_TPTE_MWBINDEN_M       0x1
0221 #define FW_RI_TPTE_MWBINDEN_V(x)    ((x) << FW_RI_TPTE_MWBINDEN_S)
0222 #define FW_RI_TPTE_MWBINDEN_G(x)    \
0223     (((x) >> FW_RI_TPTE_MWBINDEN_S) & FW_RI_TPTE_MWBINDEN_M)
0224 #define FW_RI_TPTE_MWBINDEN_F       FW_RI_TPTE_MWBINDEN_V(1U)
0225 
0226 #define FW_RI_TPTE_PS_S         20
0227 #define FW_RI_TPTE_PS_M         0x1f
0228 #define FW_RI_TPTE_PS_V(x)      ((x) << FW_RI_TPTE_PS_S)
0229 #define FW_RI_TPTE_PS_G(x)      \
0230     (((x) >> FW_RI_TPTE_PS_S) & FW_RI_TPTE_PS_M)
0231 
0232 #define FW_RI_TPTE_QPID_S       0
0233 #define FW_RI_TPTE_QPID_M       0xfffff
0234 #define FW_RI_TPTE_QPID_V(x)        ((x) << FW_RI_TPTE_QPID_S)
0235 #define FW_RI_TPTE_QPID_G(x)        \
0236     (((x) >> FW_RI_TPTE_QPID_S) & FW_RI_TPTE_QPID_M)
0237 
0238 #define FW_RI_TPTE_NOSNOOP_S        30
0239 #define FW_RI_TPTE_NOSNOOP_M        0x1
0240 #define FW_RI_TPTE_NOSNOOP_V(x)     ((x) << FW_RI_TPTE_NOSNOOP_S)
0241 #define FW_RI_TPTE_NOSNOOP_G(x)     \
0242     (((x) >> FW_RI_TPTE_NOSNOOP_S) & FW_RI_TPTE_NOSNOOP_M)
0243 #define FW_RI_TPTE_NOSNOOP_F        FW_RI_TPTE_NOSNOOP_V(1U)
0244 
0245 #define FW_RI_TPTE_PBLADDR_S        0
0246 #define FW_RI_TPTE_PBLADDR_M        0x1fffffff
0247 #define FW_RI_TPTE_PBLADDR_V(x)     ((x) << FW_RI_TPTE_PBLADDR_S)
0248 #define FW_RI_TPTE_PBLADDR_G(x)     \
0249     (((x) >> FW_RI_TPTE_PBLADDR_S) & FW_RI_TPTE_PBLADDR_M)
0250 
0251 #define FW_RI_TPTE_DCA_S        24
0252 #define FW_RI_TPTE_DCA_M        0x1f
0253 #define FW_RI_TPTE_DCA_V(x)     ((x) << FW_RI_TPTE_DCA_S)
0254 #define FW_RI_TPTE_DCA_G(x)     \
0255     (((x) >> FW_RI_TPTE_DCA_S) & FW_RI_TPTE_DCA_M)
0256 
0257 #define FW_RI_TPTE_MWBCNT_PSTAG_S   0
0258 #define FW_RI_TPTE_MWBCNT_PSTAG_M   0xffffff
0259 #define FW_RI_TPTE_MWBCNT_PSTAT_V(x)    \
0260     ((x) << FW_RI_TPTE_MWBCNT_PSTAG_S)
0261 #define FW_RI_TPTE_MWBCNT_PSTAG_G(x)    \
0262     (((x) >> FW_RI_TPTE_MWBCNT_PSTAG_S) & FW_RI_TPTE_MWBCNT_PSTAG_M)
0263 
0264 enum fw_ri_res_type {
0265     FW_RI_RES_TYPE_SQ,
0266     FW_RI_RES_TYPE_RQ,
0267     FW_RI_RES_TYPE_CQ,
0268     FW_RI_RES_TYPE_SRQ,
0269 };
0270 
0271 enum fw_ri_res_op {
0272     FW_RI_RES_OP_WRITE,
0273     FW_RI_RES_OP_RESET,
0274 };
0275 
0276 struct fw_ri_res {
0277     union fw_ri_restype {
0278         struct fw_ri_res_sqrq {
0279             __u8   restype;
0280             __u8   op;
0281             __be16 r3;
0282             __be32 eqid;
0283             __be32 r4[2];
0284             __be32 fetchszm_to_iqid;
0285             __be32 dcaen_to_eqsize;
0286             __be64 eqaddr;
0287         } sqrq;
0288         struct fw_ri_res_cq {
0289             __u8   restype;
0290             __u8   op;
0291             __be16 r3;
0292             __be32 iqid;
0293             __be32 r4[2];
0294             __be32 iqandst_to_iqandstindex;
0295             __be16 iqdroprss_to_iqesize;
0296             __be16 iqsize;
0297             __be64 iqaddr;
0298             __be32 iqns_iqro;
0299             __be32 r6_lo;
0300             __be64 r7;
0301         } cq;
0302         struct fw_ri_res_srq {
0303             __u8   restype;
0304             __u8   op;
0305             __be16 r3;
0306             __be32 eqid;
0307             __be32 r4[2];
0308             __be32 fetchszm_to_iqid;
0309             __be32 dcaen_to_eqsize;
0310             __be64 eqaddr;
0311             __be32 srqid;
0312             __be32 pdid;
0313             __be32 hwsrqsize;
0314             __be32 hwsrqaddr;
0315         } srq;
0316     } u;
0317 };
0318 
0319 struct fw_ri_res_wr {
0320     __be32 op_nres;
0321     __be32 len16_pkd;
0322     __u64  cookie;
0323 #ifndef C99_NOT_SUPPORTED
0324     struct fw_ri_res res[];
0325 #endif
0326 };
0327 
0328 #define FW_RI_RES_WR_NRES_S 0
0329 #define FW_RI_RES_WR_NRES_M 0xff
0330 #define FW_RI_RES_WR_NRES_V(x)  ((x) << FW_RI_RES_WR_NRES_S)
0331 #define FW_RI_RES_WR_NRES_G(x)  \
0332     (((x) >> FW_RI_RES_WR_NRES_S) & FW_RI_RES_WR_NRES_M)
0333 
0334 #define FW_RI_RES_WR_FETCHSZM_S     26
0335 #define FW_RI_RES_WR_FETCHSZM_M     0x1
0336 #define FW_RI_RES_WR_FETCHSZM_V(x)  ((x) << FW_RI_RES_WR_FETCHSZM_S)
0337 #define FW_RI_RES_WR_FETCHSZM_G(x)  \
0338     (((x) >> FW_RI_RES_WR_FETCHSZM_S) & FW_RI_RES_WR_FETCHSZM_M)
0339 #define FW_RI_RES_WR_FETCHSZM_F FW_RI_RES_WR_FETCHSZM_V(1U)
0340 
0341 #define FW_RI_RES_WR_STATUSPGNS_S   25
0342 #define FW_RI_RES_WR_STATUSPGNS_M   0x1
0343 #define FW_RI_RES_WR_STATUSPGNS_V(x)    ((x) << FW_RI_RES_WR_STATUSPGNS_S)
0344 #define FW_RI_RES_WR_STATUSPGNS_G(x)    \
0345     (((x) >> FW_RI_RES_WR_STATUSPGNS_S) & FW_RI_RES_WR_STATUSPGNS_M)
0346 #define FW_RI_RES_WR_STATUSPGNS_F   FW_RI_RES_WR_STATUSPGNS_V(1U)
0347 
0348 #define FW_RI_RES_WR_STATUSPGRO_S   24
0349 #define FW_RI_RES_WR_STATUSPGRO_M   0x1
0350 #define FW_RI_RES_WR_STATUSPGRO_V(x)    ((x) << FW_RI_RES_WR_STATUSPGRO_S)
0351 #define FW_RI_RES_WR_STATUSPGRO_G(x)    \
0352     (((x) >> FW_RI_RES_WR_STATUSPGRO_S) & FW_RI_RES_WR_STATUSPGRO_M)
0353 #define FW_RI_RES_WR_STATUSPGRO_F   FW_RI_RES_WR_STATUSPGRO_V(1U)
0354 
0355 #define FW_RI_RES_WR_FETCHNS_S      23
0356 #define FW_RI_RES_WR_FETCHNS_M      0x1
0357 #define FW_RI_RES_WR_FETCHNS_V(x)   ((x) << FW_RI_RES_WR_FETCHNS_S)
0358 #define FW_RI_RES_WR_FETCHNS_G(x)   \
0359     (((x) >> FW_RI_RES_WR_FETCHNS_S) & FW_RI_RES_WR_FETCHNS_M)
0360 #define FW_RI_RES_WR_FETCHNS_F  FW_RI_RES_WR_FETCHNS_V(1U)
0361 
0362 #define FW_RI_RES_WR_FETCHRO_S      22
0363 #define FW_RI_RES_WR_FETCHRO_M      0x1
0364 #define FW_RI_RES_WR_FETCHRO_V(x)   ((x) << FW_RI_RES_WR_FETCHRO_S)
0365 #define FW_RI_RES_WR_FETCHRO_G(x)   \
0366     (((x) >> FW_RI_RES_WR_FETCHRO_S) & FW_RI_RES_WR_FETCHRO_M)
0367 #define FW_RI_RES_WR_FETCHRO_F  FW_RI_RES_WR_FETCHRO_V(1U)
0368 
0369 #define FW_RI_RES_WR_HOSTFCMODE_S   20
0370 #define FW_RI_RES_WR_HOSTFCMODE_M   0x3
0371 #define FW_RI_RES_WR_HOSTFCMODE_V(x)    ((x) << FW_RI_RES_WR_HOSTFCMODE_S)
0372 #define FW_RI_RES_WR_HOSTFCMODE_G(x)    \
0373     (((x) >> FW_RI_RES_WR_HOSTFCMODE_S) & FW_RI_RES_WR_HOSTFCMODE_M)
0374 
0375 #define FW_RI_RES_WR_CPRIO_S    19
0376 #define FW_RI_RES_WR_CPRIO_M    0x1
0377 #define FW_RI_RES_WR_CPRIO_V(x) ((x) << FW_RI_RES_WR_CPRIO_S)
0378 #define FW_RI_RES_WR_CPRIO_G(x) \
0379     (((x) >> FW_RI_RES_WR_CPRIO_S) & FW_RI_RES_WR_CPRIO_M)
0380 #define FW_RI_RES_WR_CPRIO_F    FW_RI_RES_WR_CPRIO_V(1U)
0381 
0382 #define FW_RI_RES_WR_ONCHIP_S       18
0383 #define FW_RI_RES_WR_ONCHIP_M       0x1
0384 #define FW_RI_RES_WR_ONCHIP_V(x)    ((x) << FW_RI_RES_WR_ONCHIP_S)
0385 #define FW_RI_RES_WR_ONCHIP_G(x)    \
0386     (((x) >> FW_RI_RES_WR_ONCHIP_S) & FW_RI_RES_WR_ONCHIP_M)
0387 #define FW_RI_RES_WR_ONCHIP_F   FW_RI_RES_WR_ONCHIP_V(1U)
0388 
0389 #define FW_RI_RES_WR_PCIECHN_S      16
0390 #define FW_RI_RES_WR_PCIECHN_M      0x3
0391 #define FW_RI_RES_WR_PCIECHN_V(x)   ((x) << FW_RI_RES_WR_PCIECHN_S)
0392 #define FW_RI_RES_WR_PCIECHN_G(x)   \
0393     (((x) >> FW_RI_RES_WR_PCIECHN_S) & FW_RI_RES_WR_PCIECHN_M)
0394 
0395 #define FW_RI_RES_WR_IQID_S 0
0396 #define FW_RI_RES_WR_IQID_M 0xffff
0397 #define FW_RI_RES_WR_IQID_V(x)  ((x) << FW_RI_RES_WR_IQID_S)
0398 #define FW_RI_RES_WR_IQID_G(x)  \
0399     (((x) >> FW_RI_RES_WR_IQID_S) & FW_RI_RES_WR_IQID_M)
0400 
0401 #define FW_RI_RES_WR_DCAEN_S    31
0402 #define FW_RI_RES_WR_DCAEN_M    0x1
0403 #define FW_RI_RES_WR_DCAEN_V(x) ((x) << FW_RI_RES_WR_DCAEN_S)
0404 #define FW_RI_RES_WR_DCAEN_G(x) \
0405     (((x) >> FW_RI_RES_WR_DCAEN_S) & FW_RI_RES_WR_DCAEN_M)
0406 #define FW_RI_RES_WR_DCAEN_F    FW_RI_RES_WR_DCAEN_V(1U)
0407 
0408 #define FW_RI_RES_WR_DCACPU_S       26
0409 #define FW_RI_RES_WR_DCACPU_M       0x1f
0410 #define FW_RI_RES_WR_DCACPU_V(x)    ((x) << FW_RI_RES_WR_DCACPU_S)
0411 #define FW_RI_RES_WR_DCACPU_G(x)    \
0412     (((x) >> FW_RI_RES_WR_DCACPU_S) & FW_RI_RES_WR_DCACPU_M)
0413 
0414 #define FW_RI_RES_WR_FBMIN_S    23
0415 #define FW_RI_RES_WR_FBMIN_M    0x7
0416 #define FW_RI_RES_WR_FBMIN_V(x) ((x) << FW_RI_RES_WR_FBMIN_S)
0417 #define FW_RI_RES_WR_FBMIN_G(x) \
0418     (((x) >> FW_RI_RES_WR_FBMIN_S) & FW_RI_RES_WR_FBMIN_M)
0419 
0420 #define FW_RI_RES_WR_FBMAX_S    20
0421 #define FW_RI_RES_WR_FBMAX_M    0x7
0422 #define FW_RI_RES_WR_FBMAX_V(x) ((x) << FW_RI_RES_WR_FBMAX_S)
0423 #define FW_RI_RES_WR_FBMAX_G(x) \
0424     (((x) >> FW_RI_RES_WR_FBMAX_S) & FW_RI_RES_WR_FBMAX_M)
0425 
0426 #define FW_RI_RES_WR_CIDXFTHRESHO_S 19
0427 #define FW_RI_RES_WR_CIDXFTHRESHO_M 0x1
0428 #define FW_RI_RES_WR_CIDXFTHRESHO_V(x)  ((x) << FW_RI_RES_WR_CIDXFTHRESHO_S)
0429 #define FW_RI_RES_WR_CIDXFTHRESHO_G(x)  \
0430     (((x) >> FW_RI_RES_WR_CIDXFTHRESHO_S) & FW_RI_RES_WR_CIDXFTHRESHO_M)
0431 #define FW_RI_RES_WR_CIDXFTHRESHO_F FW_RI_RES_WR_CIDXFTHRESHO_V(1U)
0432 
0433 #define FW_RI_RES_WR_CIDXFTHRESH_S  16
0434 #define FW_RI_RES_WR_CIDXFTHRESH_M  0x7
0435 #define FW_RI_RES_WR_CIDXFTHRESH_V(x)   ((x) << FW_RI_RES_WR_CIDXFTHRESH_S)
0436 #define FW_RI_RES_WR_CIDXFTHRESH_G(x)   \
0437     (((x) >> FW_RI_RES_WR_CIDXFTHRESH_S) & FW_RI_RES_WR_CIDXFTHRESH_M)
0438 
0439 #define FW_RI_RES_WR_EQSIZE_S       0
0440 #define FW_RI_RES_WR_EQSIZE_M       0xffff
0441 #define FW_RI_RES_WR_EQSIZE_V(x)    ((x) << FW_RI_RES_WR_EQSIZE_S)
0442 #define FW_RI_RES_WR_EQSIZE_G(x)    \
0443     (((x) >> FW_RI_RES_WR_EQSIZE_S) & FW_RI_RES_WR_EQSIZE_M)
0444 
0445 #define FW_RI_RES_WR_IQANDST_S      15
0446 #define FW_RI_RES_WR_IQANDST_M      0x1
0447 #define FW_RI_RES_WR_IQANDST_V(x)   ((x) << FW_RI_RES_WR_IQANDST_S)
0448 #define FW_RI_RES_WR_IQANDST_G(x)   \
0449     (((x) >> FW_RI_RES_WR_IQANDST_S) & FW_RI_RES_WR_IQANDST_M)
0450 #define FW_RI_RES_WR_IQANDST_F  FW_RI_RES_WR_IQANDST_V(1U)
0451 
0452 #define FW_RI_RES_WR_IQANUS_S       14
0453 #define FW_RI_RES_WR_IQANUS_M       0x1
0454 #define FW_RI_RES_WR_IQANUS_V(x)    ((x) << FW_RI_RES_WR_IQANUS_S)
0455 #define FW_RI_RES_WR_IQANUS_G(x)    \
0456     (((x) >> FW_RI_RES_WR_IQANUS_S) & FW_RI_RES_WR_IQANUS_M)
0457 #define FW_RI_RES_WR_IQANUS_F   FW_RI_RES_WR_IQANUS_V(1U)
0458 
0459 #define FW_RI_RES_WR_IQANUD_S       12
0460 #define FW_RI_RES_WR_IQANUD_M       0x3
0461 #define FW_RI_RES_WR_IQANUD_V(x)    ((x) << FW_RI_RES_WR_IQANUD_S)
0462 #define FW_RI_RES_WR_IQANUD_G(x)    \
0463     (((x) >> FW_RI_RES_WR_IQANUD_S) & FW_RI_RES_WR_IQANUD_M)
0464 
0465 #define FW_RI_RES_WR_IQANDSTINDEX_S 0
0466 #define FW_RI_RES_WR_IQANDSTINDEX_M 0xfff
0467 #define FW_RI_RES_WR_IQANDSTINDEX_V(x)  ((x) << FW_RI_RES_WR_IQANDSTINDEX_S)
0468 #define FW_RI_RES_WR_IQANDSTINDEX_G(x)  \
0469     (((x) >> FW_RI_RES_WR_IQANDSTINDEX_S) & FW_RI_RES_WR_IQANDSTINDEX_M)
0470 
0471 #define FW_RI_RES_WR_IQDROPRSS_S    15
0472 #define FW_RI_RES_WR_IQDROPRSS_M    0x1
0473 #define FW_RI_RES_WR_IQDROPRSS_V(x) ((x) << FW_RI_RES_WR_IQDROPRSS_S)
0474 #define FW_RI_RES_WR_IQDROPRSS_G(x) \
0475     (((x) >> FW_RI_RES_WR_IQDROPRSS_S) & FW_RI_RES_WR_IQDROPRSS_M)
0476 #define FW_RI_RES_WR_IQDROPRSS_F    FW_RI_RES_WR_IQDROPRSS_V(1U)
0477 
0478 #define FW_RI_RES_WR_IQGTSMODE_S    14
0479 #define FW_RI_RES_WR_IQGTSMODE_M    0x1
0480 #define FW_RI_RES_WR_IQGTSMODE_V(x) ((x) << FW_RI_RES_WR_IQGTSMODE_S)
0481 #define FW_RI_RES_WR_IQGTSMODE_G(x) \
0482     (((x) >> FW_RI_RES_WR_IQGTSMODE_S) & FW_RI_RES_WR_IQGTSMODE_M)
0483 #define FW_RI_RES_WR_IQGTSMODE_F    FW_RI_RES_WR_IQGTSMODE_V(1U)
0484 
0485 #define FW_RI_RES_WR_IQPCIECH_S     12
0486 #define FW_RI_RES_WR_IQPCIECH_M     0x3
0487 #define FW_RI_RES_WR_IQPCIECH_V(x)  ((x) << FW_RI_RES_WR_IQPCIECH_S)
0488 #define FW_RI_RES_WR_IQPCIECH_G(x)  \
0489     (((x) >> FW_RI_RES_WR_IQPCIECH_S) & FW_RI_RES_WR_IQPCIECH_M)
0490 
0491 #define FW_RI_RES_WR_IQDCAEN_S      11
0492 #define FW_RI_RES_WR_IQDCAEN_M      0x1
0493 #define FW_RI_RES_WR_IQDCAEN_V(x)   ((x) << FW_RI_RES_WR_IQDCAEN_S)
0494 #define FW_RI_RES_WR_IQDCAEN_G(x)   \
0495     (((x) >> FW_RI_RES_WR_IQDCAEN_S) & FW_RI_RES_WR_IQDCAEN_M)
0496 #define FW_RI_RES_WR_IQDCAEN_F  FW_RI_RES_WR_IQDCAEN_V(1U)
0497 
0498 #define FW_RI_RES_WR_IQDCACPU_S     6
0499 #define FW_RI_RES_WR_IQDCACPU_M     0x1f
0500 #define FW_RI_RES_WR_IQDCACPU_V(x)  ((x) << FW_RI_RES_WR_IQDCACPU_S)
0501 #define FW_RI_RES_WR_IQDCACPU_G(x)  \
0502     (((x) >> FW_RI_RES_WR_IQDCACPU_S) & FW_RI_RES_WR_IQDCACPU_M)
0503 
0504 #define FW_RI_RES_WR_IQINTCNTTHRESH_S       4
0505 #define FW_RI_RES_WR_IQINTCNTTHRESH_M       0x3
0506 #define FW_RI_RES_WR_IQINTCNTTHRESH_V(x)    \
0507     ((x) << FW_RI_RES_WR_IQINTCNTTHRESH_S)
0508 #define FW_RI_RES_WR_IQINTCNTTHRESH_G(x)    \
0509     (((x) >> FW_RI_RES_WR_IQINTCNTTHRESH_S) & FW_RI_RES_WR_IQINTCNTTHRESH_M)
0510 
0511 #define FW_RI_RES_WR_IQO_S  3
0512 #define FW_RI_RES_WR_IQO_M  0x1
0513 #define FW_RI_RES_WR_IQO_V(x)   ((x) << FW_RI_RES_WR_IQO_S)
0514 #define FW_RI_RES_WR_IQO_G(x)   \
0515     (((x) >> FW_RI_RES_WR_IQO_S) & FW_RI_RES_WR_IQO_M)
0516 #define FW_RI_RES_WR_IQO_F  FW_RI_RES_WR_IQO_V(1U)
0517 
0518 #define FW_RI_RES_WR_IQCPRIO_S      2
0519 #define FW_RI_RES_WR_IQCPRIO_M      0x1
0520 #define FW_RI_RES_WR_IQCPRIO_V(x)   ((x) << FW_RI_RES_WR_IQCPRIO_S)
0521 #define FW_RI_RES_WR_IQCPRIO_G(x)   \
0522     (((x) >> FW_RI_RES_WR_IQCPRIO_S) & FW_RI_RES_WR_IQCPRIO_M)
0523 #define FW_RI_RES_WR_IQCPRIO_F  FW_RI_RES_WR_IQCPRIO_V(1U)
0524 
0525 #define FW_RI_RES_WR_IQESIZE_S      0
0526 #define FW_RI_RES_WR_IQESIZE_M      0x3
0527 #define FW_RI_RES_WR_IQESIZE_V(x)   ((x) << FW_RI_RES_WR_IQESIZE_S)
0528 #define FW_RI_RES_WR_IQESIZE_G(x)   \
0529     (((x) >> FW_RI_RES_WR_IQESIZE_S) & FW_RI_RES_WR_IQESIZE_M)
0530 
0531 #define FW_RI_RES_WR_IQNS_S 31
0532 #define FW_RI_RES_WR_IQNS_M 0x1
0533 #define FW_RI_RES_WR_IQNS_V(x)  ((x) << FW_RI_RES_WR_IQNS_S)
0534 #define FW_RI_RES_WR_IQNS_G(x)  \
0535     (((x) >> FW_RI_RES_WR_IQNS_S) & FW_RI_RES_WR_IQNS_M)
0536 #define FW_RI_RES_WR_IQNS_F FW_RI_RES_WR_IQNS_V(1U)
0537 
0538 #define FW_RI_RES_WR_IQRO_S 30
0539 #define FW_RI_RES_WR_IQRO_M 0x1
0540 #define FW_RI_RES_WR_IQRO_V(x)  ((x) << FW_RI_RES_WR_IQRO_S)
0541 #define FW_RI_RES_WR_IQRO_G(x)  \
0542     (((x) >> FW_RI_RES_WR_IQRO_S) & FW_RI_RES_WR_IQRO_M)
0543 #define FW_RI_RES_WR_IQRO_F FW_RI_RES_WR_IQRO_V(1U)
0544 
0545 struct fw_ri_rdma_write_wr {
0546     __u8   opcode;
0547     __u8   flags;
0548     __u16  wrid;
0549     __u8   r1[3];
0550     __u8   len16;
0551     /*
0552      * Use union for immediate data to be consistent with stack's 32 bit
0553      * data and iWARP spec's 64 bit data.
0554      */
0555     union {
0556         struct {
0557             __be32 imm_data32;
0558             u32 reserved;
0559         } ib_imm_data;
0560         __be64 imm_data64;
0561     } iw_imm_data;
0562     __be32 plen;
0563     __be32 stag_sink;
0564     __be64 to_sink;
0565 #ifndef C99_NOT_SUPPORTED
0566     union {
0567         struct fw_ri_immd immd_src[0];
0568         struct fw_ri_isgl isgl_src[0];
0569     } u;
0570 #endif
0571 };
0572 
0573 struct fw_ri_send_wr {
0574     __u8   opcode;
0575     __u8   flags;
0576     __u16  wrid;
0577     __u8   r1[3];
0578     __u8   len16;
0579     __be32 sendop_pkd;
0580     __be32 stag_inv;
0581     __be32 plen;
0582     __be32 r3;
0583     __be64 r4;
0584 #ifndef C99_NOT_SUPPORTED
0585     union {
0586         struct fw_ri_immd immd_src[0];
0587         struct fw_ri_isgl isgl_src[0];
0588     } u;
0589 #endif
0590 };
0591 
0592 #define FW_RI_SEND_WR_SENDOP_S      0
0593 #define FW_RI_SEND_WR_SENDOP_M      0xf
0594 #define FW_RI_SEND_WR_SENDOP_V(x)   ((x) << FW_RI_SEND_WR_SENDOP_S)
0595 #define FW_RI_SEND_WR_SENDOP_G(x)   \
0596     (((x) >> FW_RI_SEND_WR_SENDOP_S) & FW_RI_SEND_WR_SENDOP_M)
0597 
0598 struct fw_ri_rdma_write_cmpl_wr {
0599     __u8   opcode;
0600     __u8   flags;
0601     __u16  wrid;
0602     __u8   r1[3];
0603     __u8   len16;
0604     __u8   r2;
0605     __u8   flags_send;
0606     __u16  wrid_send;
0607     __be32 stag_inv;
0608     __be32 plen;
0609     __be32 stag_sink;
0610     __be64 to_sink;
0611     union fw_ri_cmpl {
0612         struct fw_ri_immd_cmpl {
0613             __u8   op;
0614             __u8   r1[6];
0615             __u8   immdlen;
0616             __u8   data[16];
0617         } immd_src;
0618         struct fw_ri_isgl isgl_src;
0619     } u_cmpl;
0620     __be64 r3;
0621 #ifndef C99_NOT_SUPPORTED
0622     union fw_ri_write {
0623         struct fw_ri_immd immd_src[0];
0624         struct fw_ri_isgl isgl_src[0];
0625     } u;
0626 #endif
0627 };
0628 
0629 struct fw_ri_rdma_read_wr {
0630     __u8   opcode;
0631     __u8   flags;
0632     __u16  wrid;
0633     __u8   r1[3];
0634     __u8   len16;
0635     __be64 r2;
0636     __be32 stag_sink;
0637     __be32 to_sink_hi;
0638     __be32 to_sink_lo;
0639     __be32 plen;
0640     __be32 stag_src;
0641     __be32 to_src_hi;
0642     __be32 to_src_lo;
0643     __be32 r5;
0644 };
0645 
0646 struct fw_ri_recv_wr {
0647     __u8   opcode;
0648     __u8   r1;
0649     __u16  wrid;
0650     __u8   r2[3];
0651     __u8   len16;
0652     struct fw_ri_isgl isgl;
0653 };
0654 
0655 struct fw_ri_bind_mw_wr {
0656     __u8   opcode;
0657     __u8   flags;
0658     __u16  wrid;
0659     __u8   r1[3];
0660     __u8   len16;
0661     __u8   qpbinde_to_dcacpu;
0662     __u8   pgsz_shift;
0663     __u8   addr_type;
0664     __u8   mem_perms;
0665     __be32 stag_mr;
0666     __be32 stag_mw;
0667     __be32 r3;
0668     __be64 len_mw;
0669     __be64 va_fbo;
0670     __be64 r4;
0671 };
0672 
0673 #define FW_RI_BIND_MW_WR_QPBINDE_S  6
0674 #define FW_RI_BIND_MW_WR_QPBINDE_M  0x1
0675 #define FW_RI_BIND_MW_WR_QPBINDE_V(x)   ((x) << FW_RI_BIND_MW_WR_QPBINDE_S)
0676 #define FW_RI_BIND_MW_WR_QPBINDE_G(x)   \
0677     (((x) >> FW_RI_BIND_MW_WR_QPBINDE_S) & FW_RI_BIND_MW_WR_QPBINDE_M)
0678 #define FW_RI_BIND_MW_WR_QPBINDE_F  FW_RI_BIND_MW_WR_QPBINDE_V(1U)
0679 
0680 #define FW_RI_BIND_MW_WR_NS_S       5
0681 #define FW_RI_BIND_MW_WR_NS_M       0x1
0682 #define FW_RI_BIND_MW_WR_NS_V(x)    ((x) << FW_RI_BIND_MW_WR_NS_S)
0683 #define FW_RI_BIND_MW_WR_NS_G(x)    \
0684     (((x) >> FW_RI_BIND_MW_WR_NS_S) & FW_RI_BIND_MW_WR_NS_M)
0685 #define FW_RI_BIND_MW_WR_NS_F   FW_RI_BIND_MW_WR_NS_V(1U)
0686 
0687 #define FW_RI_BIND_MW_WR_DCACPU_S   0
0688 #define FW_RI_BIND_MW_WR_DCACPU_M   0x1f
0689 #define FW_RI_BIND_MW_WR_DCACPU_V(x)    ((x) << FW_RI_BIND_MW_WR_DCACPU_S)
0690 #define FW_RI_BIND_MW_WR_DCACPU_G(x)    \
0691     (((x) >> FW_RI_BIND_MW_WR_DCACPU_S) & FW_RI_BIND_MW_WR_DCACPU_M)
0692 
0693 struct fw_ri_fr_nsmr_wr {
0694     __u8   opcode;
0695     __u8   flags;
0696     __u16  wrid;
0697     __u8   r1[3];
0698     __u8   len16;
0699     __u8   qpbinde_to_dcacpu;
0700     __u8   pgsz_shift;
0701     __u8   addr_type;
0702     __u8   mem_perms;
0703     __be32 stag;
0704     __be32 len_hi;
0705     __be32 len_lo;
0706     __be32 va_hi;
0707     __be32 va_lo_fbo;
0708 };
0709 
0710 #define FW_RI_FR_NSMR_WR_QPBINDE_S  6
0711 #define FW_RI_FR_NSMR_WR_QPBINDE_M  0x1
0712 #define FW_RI_FR_NSMR_WR_QPBINDE_V(x)   ((x) << FW_RI_FR_NSMR_WR_QPBINDE_S)
0713 #define FW_RI_FR_NSMR_WR_QPBINDE_G(x)   \
0714     (((x) >> FW_RI_FR_NSMR_WR_QPBINDE_S) & FW_RI_FR_NSMR_WR_QPBINDE_M)
0715 #define FW_RI_FR_NSMR_WR_QPBINDE_F  FW_RI_FR_NSMR_WR_QPBINDE_V(1U)
0716 
0717 #define FW_RI_FR_NSMR_WR_NS_S       5
0718 #define FW_RI_FR_NSMR_WR_NS_M       0x1
0719 #define FW_RI_FR_NSMR_WR_NS_V(x)    ((x) << FW_RI_FR_NSMR_WR_NS_S)
0720 #define FW_RI_FR_NSMR_WR_NS_G(x)    \
0721     (((x) >> FW_RI_FR_NSMR_WR_NS_S) & FW_RI_FR_NSMR_WR_NS_M)
0722 #define FW_RI_FR_NSMR_WR_NS_F   FW_RI_FR_NSMR_WR_NS_V(1U)
0723 
0724 #define FW_RI_FR_NSMR_WR_DCACPU_S   0
0725 #define FW_RI_FR_NSMR_WR_DCACPU_M   0x1f
0726 #define FW_RI_FR_NSMR_WR_DCACPU_V(x)    ((x) << FW_RI_FR_NSMR_WR_DCACPU_S)
0727 #define FW_RI_FR_NSMR_WR_DCACPU_G(x)    \
0728     (((x) >> FW_RI_FR_NSMR_WR_DCACPU_S) & FW_RI_FR_NSMR_WR_DCACPU_M)
0729 
0730 struct fw_ri_fr_nsmr_tpte_wr {
0731     __u8    opcode;
0732     __u8   flags;
0733     __u16  wrid;
0734     __u8   r1[3];
0735     __u8   len16;
0736     __be32  r2;
0737     __be32  stag;
0738     struct fw_ri_tpte tpte;
0739     __u64  pbl[2];
0740 };
0741 
0742 struct fw_ri_inv_lstag_wr {
0743     __u8   opcode;
0744     __u8   flags;
0745     __u16  wrid;
0746     __u8   r1[3];
0747     __u8   len16;
0748     __be32 r2;
0749     __be32 stag_inv;
0750 };
0751 
0752 enum fw_ri_type {
0753     FW_RI_TYPE_INIT,
0754     FW_RI_TYPE_FINI,
0755     FW_RI_TYPE_TERMINATE
0756 };
0757 
0758 enum fw_ri_init_p2ptype {
0759     FW_RI_INIT_P2PTYPE_RDMA_WRITE       = FW_RI_RDMA_WRITE,
0760     FW_RI_INIT_P2PTYPE_READ_REQ     = FW_RI_READ_REQ,
0761     FW_RI_INIT_P2PTYPE_SEND         = FW_RI_SEND,
0762     FW_RI_INIT_P2PTYPE_SEND_WITH_INV    = FW_RI_SEND_WITH_INV,
0763     FW_RI_INIT_P2PTYPE_SEND_WITH_SE     = FW_RI_SEND_WITH_SE,
0764     FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
0765     FW_RI_INIT_P2PTYPE_DISABLED     = 0xf,
0766 };
0767 
0768 enum fw_ri_init_rqeqid_srq {
0769     FW_RI_INIT_RQEQID_SRQ           = 1 << 31,
0770 };
0771 
0772 struct fw_ri_wr {
0773     __be32 op_compl;
0774     __be32 flowid_len16;
0775     __u64  cookie;
0776     union fw_ri {
0777         struct fw_ri_init {
0778             __u8   type;
0779             __u8   mpareqbit_p2ptype;
0780             __u8   r4[2];
0781             __u8   mpa_attrs;
0782             __u8   qp_caps;
0783             __be16 nrqe;
0784             __be32 pdid;
0785             __be32 qpid;
0786             __be32 sq_eqid;
0787             __be32 rq_eqid;
0788             __be32 scqid;
0789             __be32 rcqid;
0790             __be32 ord_max;
0791             __be32 ird_max;
0792             __be32 iss;
0793             __be32 irs;
0794             __be32 hwrqsize;
0795             __be32 hwrqaddr;
0796             __be64 r5;
0797             union fw_ri_init_p2p {
0798                 struct fw_ri_rdma_write_wr write;
0799                 struct fw_ri_rdma_read_wr read;
0800                 struct fw_ri_send_wr send;
0801             } u;
0802         } init;
0803         struct fw_ri_fini {
0804             __u8   type;
0805             __u8   r3[7];
0806             __be64 r4;
0807         } fini;
0808         struct fw_ri_terminate {
0809             __u8   type;
0810             __u8   r3[3];
0811             __be32 immdlen;
0812             __u8   termmsg[40];
0813         } terminate;
0814     } u;
0815 };
0816 
0817 #define FW_RI_WR_MPAREQBIT_S    7
0818 #define FW_RI_WR_MPAREQBIT_M    0x1
0819 #define FW_RI_WR_MPAREQBIT_V(x) ((x) << FW_RI_WR_MPAREQBIT_S)
0820 #define FW_RI_WR_MPAREQBIT_G(x) \
0821     (((x) >> FW_RI_WR_MPAREQBIT_S) & FW_RI_WR_MPAREQBIT_M)
0822 #define FW_RI_WR_MPAREQBIT_F    FW_RI_WR_MPAREQBIT_V(1U)
0823 
0824 #define FW_RI_WR_P2PTYPE_S  0
0825 #define FW_RI_WR_P2PTYPE_M  0xf
0826 #define FW_RI_WR_P2PTYPE_V(x)   ((x) << FW_RI_WR_P2PTYPE_S)
0827 #define FW_RI_WR_P2PTYPE_G(x)   \
0828     (((x) >> FW_RI_WR_P2PTYPE_S) & FW_RI_WR_P2PTYPE_M)
0829 
0830 #endif /* _T4FW_RI_API_H_ */
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