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0001 /*
0002  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *    copyright notice, this list of conditions and the following
0016  *    disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *    copyright notice, this list of conditions and the following
0020  *    disclaimer in the documentation and/or other materials
0021  *    provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032 
0033 #include <rdma/uverbs_ioctl.h>
0034 
0035 #include "iw_cxgb4.h"
0036 
0037 static void destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
0038                struct c4iw_dev_ucontext *uctx, struct sk_buff *skb,
0039                struct c4iw_wr_wait *wr_waitp)
0040 {
0041     struct fw_ri_res_wr *res_wr;
0042     struct fw_ri_res *res;
0043     int wr_len;
0044 
0045     wr_len = sizeof(*res_wr) + sizeof(*res);
0046     set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
0047 
0048     res_wr = __skb_put_zero(skb, wr_len);
0049     res_wr->op_nres = cpu_to_be32(
0050             FW_WR_OP_V(FW_RI_RES_WR) |
0051             FW_RI_RES_WR_NRES_V(1) |
0052             FW_WR_COMPL_F);
0053     res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
0054     res_wr->cookie = (uintptr_t)wr_waitp;
0055     res = res_wr->res;
0056     res->u.cq.restype = FW_RI_RES_TYPE_CQ;
0057     res->u.cq.op = FW_RI_RES_OP_RESET;
0058     res->u.cq.iqid = cpu_to_be32(cq->cqid);
0059 
0060     c4iw_init_wr_wait(wr_waitp);
0061     c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
0062 
0063     kfree(cq->sw_queue);
0064     dma_free_coherent(&(rdev->lldi.pdev->dev),
0065               cq->memsize, cq->queue,
0066               dma_unmap_addr(cq, mapping));
0067     c4iw_put_cqid(rdev, cq->cqid, uctx);
0068 }
0069 
0070 static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
0071              struct c4iw_dev_ucontext *uctx,
0072              struct c4iw_wr_wait *wr_waitp)
0073 {
0074     struct fw_ri_res_wr *res_wr;
0075     struct fw_ri_res *res;
0076     int wr_len;
0077     int user = (uctx != &rdev->uctx);
0078     int ret;
0079     struct sk_buff *skb;
0080     struct c4iw_ucontext *ucontext = NULL;
0081 
0082     if (user)
0083         ucontext = container_of(uctx, struct c4iw_ucontext, uctx);
0084 
0085     cq->cqid = c4iw_get_cqid(rdev, uctx);
0086     if (!cq->cqid) {
0087         ret = -ENOMEM;
0088         goto err1;
0089     }
0090 
0091     if (!user) {
0092         cq->sw_queue = kzalloc(cq->memsize, GFP_KERNEL);
0093         if (!cq->sw_queue) {
0094             ret = -ENOMEM;
0095             goto err2;
0096         }
0097     }
0098     cq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev, cq->memsize,
0099                        &cq->dma_addr, GFP_KERNEL);
0100     if (!cq->queue) {
0101         ret = -ENOMEM;
0102         goto err3;
0103     }
0104     dma_unmap_addr_set(cq, mapping, cq->dma_addr);
0105 
0106     if (user && ucontext->is_32b_cqe) {
0107         cq->qp_errp = &((struct t4_status_page *)
0108         ((u8 *)cq->queue + (cq->size - 1) *
0109          (sizeof(*cq->queue) / 2)))->qp_err;
0110     } else {
0111         cq->qp_errp = &((struct t4_status_page *)
0112         ((u8 *)cq->queue + (cq->size - 1) *
0113          sizeof(*cq->queue)))->qp_err;
0114     }
0115 
0116     /* build fw_ri_res_wr */
0117     wr_len = sizeof(*res_wr) + sizeof(*res);
0118 
0119     skb = alloc_skb(wr_len, GFP_KERNEL);
0120     if (!skb) {
0121         ret = -ENOMEM;
0122         goto err4;
0123     }
0124     set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
0125 
0126     res_wr = __skb_put_zero(skb, wr_len);
0127     res_wr->op_nres = cpu_to_be32(
0128             FW_WR_OP_V(FW_RI_RES_WR) |
0129             FW_RI_RES_WR_NRES_V(1) |
0130             FW_WR_COMPL_F);
0131     res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
0132     res_wr->cookie = (uintptr_t)wr_waitp;
0133     res = res_wr->res;
0134     res->u.cq.restype = FW_RI_RES_TYPE_CQ;
0135     res->u.cq.op = FW_RI_RES_OP_WRITE;
0136     res->u.cq.iqid = cpu_to_be32(cq->cqid);
0137     res->u.cq.iqandst_to_iqandstindex = cpu_to_be32(
0138             FW_RI_RES_WR_IQANUS_V(0) |
0139             FW_RI_RES_WR_IQANUD_V(1) |
0140             FW_RI_RES_WR_IQANDST_F |
0141             FW_RI_RES_WR_IQANDSTINDEX_V(
0142                 rdev->lldi.ciq_ids[cq->vector]));
0143     res->u.cq.iqdroprss_to_iqesize = cpu_to_be16(
0144             FW_RI_RES_WR_IQDROPRSS_F |
0145             FW_RI_RES_WR_IQPCIECH_V(2) |
0146             FW_RI_RES_WR_IQINTCNTTHRESH_V(0) |
0147             FW_RI_RES_WR_IQO_F |
0148             ((user && ucontext->is_32b_cqe) ?
0149              FW_RI_RES_WR_IQESIZE_V(1) :
0150              FW_RI_RES_WR_IQESIZE_V(2)));
0151     res->u.cq.iqsize = cpu_to_be16(cq->size);
0152     res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr);
0153 
0154     c4iw_init_wr_wait(wr_waitp);
0155     ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
0156     if (ret)
0157         goto err4;
0158 
0159     cq->gen = 1;
0160     cq->gts = rdev->lldi.gts_reg;
0161     cq->rdev = rdev;
0162 
0163     cq->bar2_va = c4iw_bar2_addrs(rdev, cq->cqid, CXGB4_BAR2_QTYPE_INGRESS,
0164                       &cq->bar2_qid,
0165                       user ? &cq->bar2_pa : NULL);
0166     if (user && !cq->bar2_pa) {
0167         pr_warn("%s: cqid %u not in BAR2 range\n",
0168             pci_name(rdev->lldi.pdev), cq->cqid);
0169         ret = -EINVAL;
0170         goto err4;
0171     }
0172     return 0;
0173 err4:
0174     dma_free_coherent(&rdev->lldi.pdev->dev, cq->memsize, cq->queue,
0175               dma_unmap_addr(cq, mapping));
0176 err3:
0177     kfree(cq->sw_queue);
0178 err2:
0179     c4iw_put_cqid(rdev, cq->cqid, uctx);
0180 err1:
0181     return ret;
0182 }
0183 
0184 static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq, u32 srqidx)
0185 {
0186     struct t4_cqe cqe;
0187 
0188     pr_debug("wq %p cq %p sw_cidx %u sw_pidx %u\n",
0189          wq, cq, cq->sw_cidx, cq->sw_pidx);
0190     memset(&cqe, 0, sizeof(cqe));
0191     cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
0192                  CQE_OPCODE_V(FW_RI_SEND) |
0193                  CQE_TYPE_V(0) |
0194                  CQE_SWCQE_V(1) |
0195                  CQE_QPID_V(wq->sq.qid));
0196     cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
0197     if (srqidx)
0198         cqe.u.srcqe.abs_rqe_idx = cpu_to_be32(srqidx);
0199     cq->sw_queue[cq->sw_pidx] = cqe;
0200     t4_swcq_produce(cq);
0201 }
0202 
0203 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
0204 {
0205     int flushed = 0;
0206     int in_use = wq->rq.in_use - count;
0207 
0208     pr_debug("wq %p cq %p rq.in_use %u skip count %u\n",
0209          wq, cq, wq->rq.in_use, count);
0210     while (in_use--) {
0211         insert_recv_cqe(wq, cq, 0);
0212         flushed++;
0213     }
0214     return flushed;
0215 }
0216 
0217 static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
0218               struct t4_swsqe *swcqe)
0219 {
0220     struct t4_cqe cqe;
0221 
0222     pr_debug("wq %p cq %p sw_cidx %u sw_pidx %u\n",
0223          wq, cq, cq->sw_cidx, cq->sw_pidx);
0224     memset(&cqe, 0, sizeof(cqe));
0225     cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
0226                  CQE_OPCODE_V(swcqe->opcode) |
0227                  CQE_TYPE_V(1) |
0228                  CQE_SWCQE_V(1) |
0229                  CQE_QPID_V(wq->sq.qid));
0230     CQE_WRID_SQ_IDX(&cqe) = swcqe->idx;
0231     cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
0232     cq->sw_queue[cq->sw_pidx] = cqe;
0233     t4_swcq_produce(cq);
0234 }
0235 
0236 static void advance_oldest_read(struct t4_wq *wq);
0237 
0238 int c4iw_flush_sq(struct c4iw_qp *qhp)
0239 {
0240     int flushed = 0;
0241     struct t4_wq *wq = &qhp->wq;
0242     struct c4iw_cq *chp = to_c4iw_cq(qhp->ibqp.send_cq);
0243     struct t4_cq *cq = &chp->cq;
0244     int idx;
0245     struct t4_swsqe *swsqe;
0246 
0247     if (wq->sq.flush_cidx == -1)
0248         wq->sq.flush_cidx = wq->sq.cidx;
0249     idx = wq->sq.flush_cidx;
0250     while (idx != wq->sq.pidx) {
0251         swsqe = &wq->sq.sw_sq[idx];
0252         swsqe->flushed = 1;
0253         insert_sq_cqe(wq, cq, swsqe);
0254         if (wq->sq.oldest_read == swsqe) {
0255             advance_oldest_read(wq);
0256         }
0257         flushed++;
0258         if (++idx == wq->sq.size)
0259             idx = 0;
0260     }
0261     wq->sq.flush_cidx += flushed;
0262     if (wq->sq.flush_cidx >= wq->sq.size)
0263         wq->sq.flush_cidx -= wq->sq.size;
0264     return flushed;
0265 }
0266 
0267 static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
0268 {
0269     struct t4_swsqe *swsqe;
0270     int cidx;
0271 
0272     if (wq->sq.flush_cidx == -1)
0273         wq->sq.flush_cidx = wq->sq.cidx;
0274     cidx = wq->sq.flush_cidx;
0275 
0276     while (cidx != wq->sq.pidx) {
0277         swsqe = &wq->sq.sw_sq[cidx];
0278         if (!swsqe->signaled) {
0279             if (++cidx == wq->sq.size)
0280                 cidx = 0;
0281         } else if (swsqe->complete) {
0282 
0283             /*
0284              * Insert this completed cqe into the swcq.
0285              */
0286             pr_debug("moving cqe into swcq sq idx %u cq idx %u\n",
0287                  cidx, cq->sw_pidx);
0288             swsqe->cqe.header |= htonl(CQE_SWCQE_V(1));
0289             cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
0290             t4_swcq_produce(cq);
0291             swsqe->flushed = 1;
0292             if (++cidx == wq->sq.size)
0293                 cidx = 0;
0294             wq->sq.flush_cidx = cidx;
0295         } else
0296             break;
0297     }
0298 }
0299 
0300 static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe,
0301         struct t4_cqe *read_cqe)
0302 {
0303     read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx;
0304     read_cqe->len = htonl(wq->sq.oldest_read->read_len);
0305     read_cqe->header = htonl(CQE_QPID_V(CQE_QPID(hw_cqe)) |
0306             CQE_SWCQE_V(SW_CQE(hw_cqe)) |
0307             CQE_OPCODE_V(FW_RI_READ_REQ) |
0308             CQE_TYPE_V(1));
0309     read_cqe->bits_type_ts = hw_cqe->bits_type_ts;
0310 }
0311 
0312 static void advance_oldest_read(struct t4_wq *wq)
0313 {
0314 
0315     u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1;
0316 
0317     if (rptr == wq->sq.size)
0318         rptr = 0;
0319     while (rptr != wq->sq.pidx) {
0320         wq->sq.oldest_read = &wq->sq.sw_sq[rptr];
0321 
0322         if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ)
0323             return;
0324         if (++rptr == wq->sq.size)
0325             rptr = 0;
0326     }
0327     wq->sq.oldest_read = NULL;
0328 }
0329 
0330 /*
0331  * Move all CQEs from the HWCQ into the SWCQ.
0332  * Deal with out-of-order and/or completions that complete
0333  * prior unsignalled WRs.
0334  */
0335 void c4iw_flush_hw_cq(struct c4iw_cq *chp, struct c4iw_qp *flush_qhp)
0336 {
0337     struct t4_cqe *hw_cqe, *swcqe, read_cqe;
0338     struct c4iw_qp *qhp;
0339     struct t4_swsqe *swsqe;
0340     int ret;
0341 
0342     pr_debug("cqid 0x%x\n", chp->cq.cqid);
0343     ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
0344 
0345     /*
0346      * This logic is similar to poll_cq(), but not quite the same
0347      * unfortunately.  Need to move pertinent HW CQEs to the SW CQ but
0348      * also do any translation magic that poll_cq() normally does.
0349      */
0350     while (!ret) {
0351         qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe));
0352 
0353         /*
0354          * drop CQEs with no associated QP
0355          */
0356         if (qhp == NULL)
0357             goto next_cqe;
0358 
0359         if (flush_qhp != qhp) {
0360             spin_lock(&qhp->lock);
0361 
0362             if (qhp->wq.flushed == 1)
0363                 goto next_cqe;
0364         }
0365 
0366         if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE)
0367             goto next_cqe;
0368 
0369         if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
0370 
0371             /* If we have reached here because of async
0372              * event or other error, and have egress error
0373              * then drop
0374              */
0375             if (CQE_TYPE(hw_cqe) == 1)
0376                 goto next_cqe;
0377 
0378             /* drop peer2peer RTR reads.
0379              */
0380             if (CQE_WRID_STAG(hw_cqe) == 1)
0381                 goto next_cqe;
0382 
0383             /*
0384              * Eat completions for unsignaled read WRs.
0385              */
0386             if (!qhp->wq.sq.oldest_read->signaled) {
0387                 advance_oldest_read(&qhp->wq);
0388                 goto next_cqe;
0389             }
0390 
0391             /*
0392              * Don't write to the HWCQ, create a new read req CQE
0393              * in local memory and move it into the swcq.
0394              */
0395             create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe);
0396             hw_cqe = &read_cqe;
0397             advance_oldest_read(&qhp->wq);
0398         }
0399 
0400         /* if its a SQ completion, then do the magic to move all the
0401          * unsignaled and now in-order completions into the swcq.
0402          */
0403         if (SQ_TYPE(hw_cqe)) {
0404             swsqe = &qhp->wq.sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
0405             swsqe->cqe = *hw_cqe;
0406             swsqe->complete = 1;
0407             flush_completed_wrs(&qhp->wq, &chp->cq);
0408         } else {
0409             swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx];
0410             *swcqe = *hw_cqe;
0411             swcqe->header |= cpu_to_be32(CQE_SWCQE_V(1));
0412             t4_swcq_produce(&chp->cq);
0413         }
0414 next_cqe:
0415         t4_hwcq_consume(&chp->cq);
0416         ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
0417         if (qhp && flush_qhp != qhp)
0418             spin_unlock(&qhp->lock);
0419     }
0420 }
0421 
0422 static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
0423 {
0424     if (DRAIN_CQE(cqe)) {
0425         WARN_ONCE(1, "Unexpected DRAIN CQE qp id %u!\n", wq->sq.qid);
0426         return 0;
0427     }
0428 
0429     if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
0430         return 0;
0431 
0432     if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe))
0433         return 0;
0434 
0435     if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe))
0436         return 0;
0437 
0438     if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq))
0439         return 0;
0440     return 1;
0441 }
0442 
0443 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
0444 {
0445     struct t4_cqe *cqe;
0446     u32 ptr;
0447 
0448     *count = 0;
0449     pr_debug("count zero %d\n", *count);
0450     ptr = cq->sw_cidx;
0451     while (ptr != cq->sw_pidx) {
0452         cqe = &cq->sw_queue[ptr];
0453         if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) &&
0454             (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq))
0455             (*count)++;
0456         if (++ptr == cq->size)
0457             ptr = 0;
0458     }
0459     pr_debug("cq %p count %d\n", cq, *count);
0460 }
0461 
0462 static void post_pending_srq_wrs(struct t4_srq *srq)
0463 {
0464     struct t4_srq_pending_wr *pwr;
0465     u16 idx = 0;
0466 
0467     while (srq->pending_in_use) {
0468         pwr = &srq->pending_wrs[srq->pending_cidx];
0469         srq->sw_rq[srq->pidx].wr_id = pwr->wr_id;
0470         srq->sw_rq[srq->pidx].valid = 1;
0471 
0472         pr_debug("%s posting pending cidx %u pidx %u wq_pidx %u in_use %u rq_size %u wr_id %llx\n",
0473              __func__,
0474              srq->cidx, srq->pidx, srq->wq_pidx,
0475              srq->in_use, srq->size,
0476              (unsigned long long)pwr->wr_id);
0477 
0478         c4iw_copy_wr_to_srq(srq, &pwr->wqe, pwr->len16);
0479         t4_srq_consume_pending_wr(srq);
0480         t4_srq_produce(srq, pwr->len16);
0481         idx += DIV_ROUND_UP(pwr->len16 * 16, T4_EQ_ENTRY_SIZE);
0482     }
0483 
0484     if (idx) {
0485         t4_ring_srq_db(srq, idx, pwr->len16, &pwr->wqe);
0486         srq->queue[srq->size].status.host_wq_pidx =
0487             srq->wq_pidx;
0488     }
0489 }
0490 
0491 static u64 reap_srq_cqe(struct t4_cqe *hw_cqe, struct t4_srq *srq)
0492 {
0493     int rel_idx = CQE_ABS_RQE_IDX(hw_cqe) - srq->rqt_abs_idx;
0494     u64 wr_id;
0495 
0496     srq->sw_rq[rel_idx].valid = 0;
0497     wr_id = srq->sw_rq[rel_idx].wr_id;
0498 
0499     if (rel_idx == srq->cidx) {
0500         pr_debug("%s in order cqe rel_idx %u cidx %u pidx %u wq_pidx %u in_use %u rq_size %u wr_id %llx\n",
0501              __func__, rel_idx, srq->cidx, srq->pidx,
0502              srq->wq_pidx, srq->in_use, srq->size,
0503              (unsigned long long)srq->sw_rq[rel_idx].wr_id);
0504         t4_srq_consume(srq);
0505         while (srq->ooo_count && !srq->sw_rq[srq->cidx].valid) {
0506             pr_debug("%s eat ooo cidx %u pidx %u wq_pidx %u in_use %u rq_size %u ooo_count %u wr_id %llx\n",
0507                  __func__, srq->cidx, srq->pidx,
0508                  srq->wq_pidx, srq->in_use,
0509                  srq->size, srq->ooo_count,
0510                  (unsigned long long)
0511                  srq->sw_rq[srq->cidx].wr_id);
0512             t4_srq_consume_ooo(srq);
0513         }
0514         if (srq->ooo_count == 0 && srq->pending_in_use)
0515             post_pending_srq_wrs(srq);
0516     } else {
0517         pr_debug("%s ooo cqe rel_idx %u cidx %u pidx %u wq_pidx %u in_use %u rq_size %u ooo_count %u wr_id %llx\n",
0518              __func__, rel_idx, srq->cidx,
0519              srq->pidx, srq->wq_pidx,
0520              srq->in_use, srq->size,
0521              srq->ooo_count,
0522              (unsigned long long)srq->sw_rq[rel_idx].wr_id);
0523         t4_srq_produce_ooo(srq);
0524     }
0525     return wr_id;
0526 }
0527 
0528 /*
0529  * poll_cq
0530  *
0531  * Caller must:
0532  *     check the validity of the first CQE,
0533  *     supply the wq assicated with the qpid.
0534  *
0535  * credit: cq credit to return to sge.
0536  * cqe_flushed: 1 iff the CQE is flushed.
0537  * cqe: copy of the polled CQE.
0538  *
0539  * return value:
0540  *    0         CQE returned ok.
0541  *    -EAGAIN       CQE skipped, try again.
0542  *    -EOVERFLOW    CQ overflow detected.
0543  */
0544 static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
0545            u8 *cqe_flushed, u64 *cookie, u32 *credit,
0546            struct t4_srq *srq)
0547 {
0548     int ret = 0;
0549     struct t4_cqe *hw_cqe, read_cqe;
0550 
0551     *cqe_flushed = 0;
0552     *credit = 0;
0553     ret = t4_next_cqe(cq, &hw_cqe);
0554     if (ret)
0555         return ret;
0556 
0557     pr_debug("CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
0558          CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
0559          CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
0560          CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
0561          CQE_WRID_LOW(hw_cqe));
0562 
0563     /*
0564      * skip cqe's not affiliated with a QP.
0565      */
0566     if (wq == NULL) {
0567         ret = -EAGAIN;
0568         goto skip_cqe;
0569     }
0570 
0571     /*
0572     * skip hw cqe's if the wq is flushed.
0573     */
0574     if (wq->flushed && !SW_CQE(hw_cqe)) {
0575         ret = -EAGAIN;
0576         goto skip_cqe;
0577     }
0578 
0579     /*
0580      * skip TERMINATE cqes...
0581      */
0582     if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) {
0583         ret = -EAGAIN;
0584         goto skip_cqe;
0585     }
0586 
0587     /*
0588      * Special cqe for drain WR completions...
0589      */
0590     if (DRAIN_CQE(hw_cqe)) {
0591         *cookie = CQE_DRAIN_COOKIE(hw_cqe);
0592         *cqe = *hw_cqe;
0593         goto skip_cqe;
0594     }
0595 
0596     /*
0597      * Gotta tweak READ completions:
0598      *  1) the cqe doesn't contain the sq_wptr from the wr.
0599      *  2) opcode not reflected from the wr.
0600      *  3) read_len not reflected from the wr.
0601      *  4) cq_type is RQ_TYPE not SQ_TYPE.
0602      */
0603     if (RQ_TYPE(hw_cqe) && (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP)) {
0604 
0605         /* If we have reached here because of async
0606          * event or other error, and have egress error
0607          * then drop
0608          */
0609         if (CQE_TYPE(hw_cqe) == 1) {
0610             if (CQE_STATUS(hw_cqe))
0611                 t4_set_wq_in_error(wq, 0);
0612             ret = -EAGAIN;
0613             goto skip_cqe;
0614         }
0615 
0616         /* If this is an unsolicited read response, then the read
0617          * was generated by the kernel driver as part of peer-2-peer
0618          * connection setup.  So ignore the completion.
0619          */
0620         if (CQE_WRID_STAG(hw_cqe) == 1) {
0621             if (CQE_STATUS(hw_cqe))
0622                 t4_set_wq_in_error(wq, 0);
0623             ret = -EAGAIN;
0624             goto skip_cqe;
0625         }
0626 
0627         /*
0628          * Eat completions for unsignaled read WRs.
0629          */
0630         if (!wq->sq.oldest_read->signaled) {
0631             advance_oldest_read(wq);
0632             ret = -EAGAIN;
0633             goto skip_cqe;
0634         }
0635 
0636         /*
0637          * Don't write to the HWCQ, so create a new read req CQE
0638          * in local memory.
0639          */
0640         create_read_req_cqe(wq, hw_cqe, &read_cqe);
0641         hw_cqe = &read_cqe;
0642         advance_oldest_read(wq);
0643     }
0644 
0645     if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) {
0646         *cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH);
0647         t4_set_wq_in_error(wq, 0);
0648     }
0649 
0650     /*
0651      * RECV completion.
0652      */
0653     if (RQ_TYPE(hw_cqe)) {
0654 
0655         /*
0656          * HW only validates 4 bits of MSN.  So we must validate that
0657          * the MSN in the SEND is the next expected MSN.  If its not,
0658          * then we complete this with T4_ERR_MSN and mark the wq in
0659          * error.
0660          */
0661         if (unlikely(!CQE_STATUS(hw_cqe) &&
0662                  CQE_WRID_MSN(hw_cqe) != wq->rq.msn)) {
0663             t4_set_wq_in_error(wq, 0);
0664             hw_cqe->header |= cpu_to_be32(CQE_STATUS_V(T4_ERR_MSN));
0665         }
0666         goto proc_cqe;
0667     }
0668 
0669     /*
0670      * If we get here its a send completion.
0671      *
0672      * Handle out of order completion. These get stuffed
0673      * in the SW SQ. Then the SW SQ is walked to move any
0674      * now in-order completions into the SW CQ.  This handles
0675      * 2 cases:
0676      *  1) reaping unsignaled WRs when the first subsequent
0677      *     signaled WR is completed.
0678      *  2) out of order read completions.
0679      */
0680     if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
0681         struct t4_swsqe *swsqe;
0682 
0683         pr_debug("out of order completion going in sw_sq at idx %u\n",
0684              CQE_WRID_SQ_IDX(hw_cqe));
0685         swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
0686         swsqe->cqe = *hw_cqe;
0687         swsqe->complete = 1;
0688         ret = -EAGAIN;
0689         goto flush_wq;
0690     }
0691 
0692 proc_cqe:
0693     *cqe = *hw_cqe;
0694 
0695     /*
0696      * Reap the associated WR(s) that are freed up with this
0697      * completion.
0698      */
0699     if (SQ_TYPE(hw_cqe)) {
0700         int idx = CQE_WRID_SQ_IDX(hw_cqe);
0701 
0702         /*
0703         * Account for any unsignaled completions completed by
0704         * this signaled completion.  In this case, cidx points
0705         * to the first unsignaled one, and idx points to the
0706         * signaled one.  So adjust in_use based on this delta.
0707         * if this is not completing any unsigned wrs, then the
0708         * delta will be 0. Handle wrapping also!
0709         */
0710         if (idx < wq->sq.cidx)
0711             wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
0712         else
0713             wq->sq.in_use -= idx - wq->sq.cidx;
0714 
0715         wq->sq.cidx = (uint16_t)idx;
0716         pr_debug("completing sq idx %u\n", wq->sq.cidx);
0717         *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
0718         if (c4iw_wr_log)
0719             c4iw_log_wr_stats(wq, hw_cqe);
0720         t4_sq_consume(wq);
0721     } else {
0722         if (!srq) {
0723             pr_debug("completing rq idx %u\n", wq->rq.cidx);
0724             *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
0725             if (c4iw_wr_log)
0726                 c4iw_log_wr_stats(wq, hw_cqe);
0727             t4_rq_consume(wq);
0728         } else {
0729             *cookie = reap_srq_cqe(hw_cqe, srq);
0730         }
0731         wq->rq.msn++;
0732         goto skip_cqe;
0733     }
0734 
0735 flush_wq:
0736     /*
0737      * Flush any completed cqes that are now in-order.
0738      */
0739     flush_completed_wrs(wq, cq);
0740 
0741 skip_cqe:
0742     if (SW_CQE(hw_cqe)) {
0743         pr_debug("cq %p cqid 0x%x skip sw cqe cidx %u\n",
0744              cq, cq->cqid, cq->sw_cidx);
0745         t4_swcq_consume(cq);
0746     } else {
0747         pr_debug("cq %p cqid 0x%x skip hw cqe cidx %u\n",
0748              cq, cq->cqid, cq->cidx);
0749         t4_hwcq_consume(cq);
0750     }
0751     return ret;
0752 }
0753 
0754 static int __c4iw_poll_cq_one(struct c4iw_cq *chp, struct c4iw_qp *qhp,
0755                   struct ib_wc *wc, struct c4iw_srq *srq)
0756 {
0757     struct t4_cqe cqe;
0758     struct t4_wq *wq = qhp ? &qhp->wq : NULL;
0759     u32 credit = 0;
0760     u8 cqe_flushed;
0761     u64 cookie = 0;
0762     int ret;
0763 
0764     ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit,
0765               srq ? &srq->wq : NULL);
0766     if (ret)
0767         goto out;
0768 
0769     wc->wr_id = cookie;
0770     wc->qp = qhp ? &qhp->ibqp : NULL;
0771     wc->vendor_err = CQE_STATUS(&cqe);
0772     wc->wc_flags = 0;
0773 
0774     /*
0775      * Simulate a SRQ_LIMIT_REACHED HW notification if required.
0776      */
0777     if (srq && !(srq->flags & T4_SRQ_LIMIT_SUPPORT) && srq->armed &&
0778         srq->wq.in_use < srq->srq_limit)
0779         c4iw_dispatch_srq_limit_reached_event(srq);
0780 
0781     pr_debug("qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x lo 0x%x cookie 0x%llx\n",
0782          CQE_QPID(&cqe),
0783          CQE_TYPE(&cqe), CQE_OPCODE(&cqe),
0784          CQE_STATUS(&cqe), CQE_LEN(&cqe),
0785          CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe),
0786          (unsigned long long)cookie);
0787 
0788     if (CQE_TYPE(&cqe) == 0) {
0789         if (!CQE_STATUS(&cqe))
0790             wc->byte_len = CQE_LEN(&cqe);
0791         else
0792             wc->byte_len = 0;
0793 
0794         switch (CQE_OPCODE(&cqe)) {
0795         case FW_RI_SEND:
0796             wc->opcode = IB_WC_RECV;
0797             break;
0798         case FW_RI_SEND_WITH_INV:
0799         case FW_RI_SEND_WITH_SE_INV:
0800             wc->opcode = IB_WC_RECV;
0801             wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe);
0802             wc->wc_flags |= IB_WC_WITH_INVALIDATE;
0803             c4iw_invalidate_mr(qhp->rhp, wc->ex.invalidate_rkey);
0804             break;
0805         case FW_RI_WRITE_IMMEDIATE:
0806             wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
0807             wc->ex.imm_data = CQE_IMM_DATA(&cqe);
0808             wc->wc_flags |= IB_WC_WITH_IMM;
0809             break;
0810         default:
0811             pr_err("Unexpected opcode %d in the CQE received for QPID=0x%0x\n",
0812                    CQE_OPCODE(&cqe), CQE_QPID(&cqe));
0813             ret = -EINVAL;
0814             goto out;
0815         }
0816     } else {
0817         switch (CQE_OPCODE(&cqe)) {
0818         case FW_RI_WRITE_IMMEDIATE:
0819         case FW_RI_RDMA_WRITE:
0820             wc->opcode = IB_WC_RDMA_WRITE;
0821             break;
0822         case FW_RI_READ_REQ:
0823             wc->opcode = IB_WC_RDMA_READ;
0824             wc->byte_len = CQE_LEN(&cqe);
0825             break;
0826         case FW_RI_SEND_WITH_INV:
0827         case FW_RI_SEND_WITH_SE_INV:
0828             wc->opcode = IB_WC_SEND;
0829             wc->wc_flags |= IB_WC_WITH_INVALIDATE;
0830             break;
0831         case FW_RI_SEND:
0832         case FW_RI_SEND_WITH_SE:
0833             wc->opcode = IB_WC_SEND;
0834             break;
0835 
0836         case FW_RI_LOCAL_INV:
0837             wc->opcode = IB_WC_LOCAL_INV;
0838             break;
0839         case FW_RI_FAST_REGISTER:
0840             wc->opcode = IB_WC_REG_MR;
0841 
0842             /* Invalidate the MR if the fastreg failed */
0843             if (CQE_STATUS(&cqe) != T4_ERR_SUCCESS)
0844                 c4iw_invalidate_mr(qhp->rhp,
0845                            CQE_WRID_FR_STAG(&cqe));
0846             break;
0847         default:
0848             pr_err("Unexpected opcode %d in the CQE received for QPID=0x%0x\n",
0849                    CQE_OPCODE(&cqe), CQE_QPID(&cqe));
0850             ret = -EINVAL;
0851             goto out;
0852         }
0853     }
0854 
0855     if (cqe_flushed)
0856         wc->status = IB_WC_WR_FLUSH_ERR;
0857     else {
0858 
0859         switch (CQE_STATUS(&cqe)) {
0860         case T4_ERR_SUCCESS:
0861             wc->status = IB_WC_SUCCESS;
0862             break;
0863         case T4_ERR_STAG:
0864             wc->status = IB_WC_LOC_ACCESS_ERR;
0865             break;
0866         case T4_ERR_PDID:
0867             wc->status = IB_WC_LOC_PROT_ERR;
0868             break;
0869         case T4_ERR_QPID:
0870         case T4_ERR_ACCESS:
0871             wc->status = IB_WC_LOC_ACCESS_ERR;
0872             break;
0873         case T4_ERR_WRAP:
0874             wc->status = IB_WC_GENERAL_ERR;
0875             break;
0876         case T4_ERR_BOUND:
0877             wc->status = IB_WC_LOC_LEN_ERR;
0878             break;
0879         case T4_ERR_INVALIDATE_SHARED_MR:
0880         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
0881             wc->status = IB_WC_MW_BIND_ERR;
0882             break;
0883         case T4_ERR_CRC:
0884         case T4_ERR_MARKER:
0885         case T4_ERR_PDU_LEN_ERR:
0886         case T4_ERR_OUT_OF_RQE:
0887         case T4_ERR_DDP_VERSION:
0888         case T4_ERR_RDMA_VERSION:
0889         case T4_ERR_DDP_QUEUE_NUM:
0890         case T4_ERR_MSN:
0891         case T4_ERR_TBIT:
0892         case T4_ERR_MO:
0893         case T4_ERR_MSN_RANGE:
0894         case T4_ERR_IRD_OVERFLOW:
0895         case T4_ERR_OPCODE:
0896         case T4_ERR_INTERNAL_ERR:
0897             wc->status = IB_WC_FATAL_ERR;
0898             break;
0899         case T4_ERR_SWFLUSH:
0900             wc->status = IB_WC_WR_FLUSH_ERR;
0901             break;
0902         default:
0903             pr_err("Unexpected cqe_status 0x%x for QPID=0x%0x\n",
0904                    CQE_STATUS(&cqe), CQE_QPID(&cqe));
0905             wc->status = IB_WC_FATAL_ERR;
0906         }
0907     }
0908 out:
0909     return ret;
0910 }
0911 
0912 /*
0913  * Get one cq entry from c4iw and map it to openib.
0914  *
0915  * Returns:
0916  *  0           cqe returned
0917  *  -ENODATA        EMPTY;
0918  *  -EAGAIN         caller must try again
0919  *  any other -errno    fatal error
0920  */
0921 static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
0922 {
0923     struct c4iw_srq *srq = NULL;
0924     struct c4iw_qp *qhp = NULL;
0925     struct t4_cqe *rd_cqe;
0926     int ret;
0927 
0928     ret = t4_next_cqe(&chp->cq, &rd_cqe);
0929 
0930     if (ret)
0931         return ret;
0932 
0933     qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe));
0934     if (qhp) {
0935         spin_lock(&qhp->lock);
0936         srq = qhp->srq;
0937         if (srq)
0938             spin_lock(&srq->lock);
0939         ret = __c4iw_poll_cq_one(chp, qhp, wc, srq);
0940         spin_unlock(&qhp->lock);
0941         if (srq)
0942             spin_unlock(&srq->lock);
0943     } else {
0944         ret = __c4iw_poll_cq_one(chp, NULL, wc, NULL);
0945     }
0946     return ret;
0947 }
0948 
0949 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
0950 {
0951     struct c4iw_cq *chp;
0952     unsigned long flags;
0953     int npolled;
0954     int err = 0;
0955 
0956     chp = to_c4iw_cq(ibcq);
0957 
0958     spin_lock_irqsave(&chp->lock, flags);
0959     for (npolled = 0; npolled < num_entries; ++npolled) {
0960         do {
0961             err = c4iw_poll_cq_one(chp, wc + npolled);
0962         } while (err == -EAGAIN);
0963         if (err)
0964             break;
0965     }
0966     spin_unlock_irqrestore(&chp->lock, flags);
0967     return !err || err == -ENODATA ? npolled : err;
0968 }
0969 
0970 void c4iw_cq_rem_ref(struct c4iw_cq *chp)
0971 {
0972     if (refcount_dec_and_test(&chp->refcnt))
0973         complete(&chp->cq_rel_comp);
0974 }
0975 
0976 int c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
0977 {
0978     struct c4iw_cq *chp;
0979     struct c4iw_ucontext *ucontext;
0980 
0981     pr_debug("ib_cq %p\n", ib_cq);
0982     chp = to_c4iw_cq(ib_cq);
0983 
0984     xa_erase_irq(&chp->rhp->cqs, chp->cq.cqid);
0985     c4iw_cq_rem_ref(chp);
0986     wait_for_completion(&chp->cq_rel_comp);
0987 
0988     ucontext = rdma_udata_to_drv_context(udata, struct c4iw_ucontext,
0989                          ibucontext);
0990     destroy_cq(&chp->rhp->rdev, &chp->cq,
0991            ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx,
0992            chp->destroy_skb, chp->wr_waitp);
0993     c4iw_put_wr_wait(chp->wr_waitp);
0994     return 0;
0995 }
0996 
0997 int c4iw_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
0998            struct ib_udata *udata)
0999 {
1000     struct ib_device *ibdev = ibcq->device;
1001     int entries = attr->cqe;
1002     int vector = attr->comp_vector;
1003     struct c4iw_dev *rhp = to_c4iw_dev(ibcq->device);
1004     struct c4iw_cq *chp = to_c4iw_cq(ibcq);
1005     struct c4iw_create_cq ucmd;
1006     struct c4iw_create_cq_resp uresp;
1007     int ret, wr_len;
1008     size_t memsize, hwentries;
1009     struct c4iw_mm_entry *mm, *mm2;
1010     struct c4iw_ucontext *ucontext = rdma_udata_to_drv_context(
1011         udata, struct c4iw_ucontext, ibucontext);
1012 
1013     pr_debug("ib_dev %p entries %d\n", ibdev, entries);
1014     if (attr->flags)
1015         return -EOPNOTSUPP;
1016 
1017     if (entries < 1 || entries > ibdev->attrs.max_cqe)
1018         return -EINVAL;
1019 
1020     if (vector >= rhp->rdev.lldi.nciq)
1021         return -EINVAL;
1022 
1023     if (udata) {
1024         if (udata->inlen < sizeof(ucmd))
1025             ucontext->is_32b_cqe = 1;
1026     }
1027 
1028     chp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
1029     if (!chp->wr_waitp) {
1030         ret = -ENOMEM;
1031         goto err_free_chp;
1032     }
1033     c4iw_init_wr_wait(chp->wr_waitp);
1034 
1035     wr_len = sizeof(struct fw_ri_res_wr) + sizeof(struct fw_ri_res);
1036     chp->destroy_skb = alloc_skb(wr_len, GFP_KERNEL);
1037     if (!chp->destroy_skb) {
1038         ret = -ENOMEM;
1039         goto err_free_wr_wait;
1040     }
1041 
1042     /* account for the status page. */
1043     entries++;
1044 
1045     /* IQ needs one extra entry to differentiate full vs empty. */
1046     entries++;
1047 
1048     /*
1049      * entries must be multiple of 16 for HW.
1050      */
1051     entries = roundup(entries, 16);
1052 
1053     /*
1054      * Make actual HW queue 2x to avoid cdix_inc overflows.
1055      */
1056     hwentries = min(entries * 2, rhp->rdev.hw_queue.t4_max_iq_size);
1057 
1058     /*
1059      * Make HW queue at least 64 entries so GTS updates aren't too
1060      * frequent.
1061      */
1062     if (hwentries < 64)
1063         hwentries = 64;
1064 
1065     memsize = hwentries * ((ucontext && ucontext->is_32b_cqe) ?
1066             (sizeof(*chp->cq.queue) / 2) : sizeof(*chp->cq.queue));
1067 
1068     /*
1069      * memsize must be a multiple of the page size if its a user cq.
1070      */
1071     if (udata)
1072         memsize = roundup(memsize, PAGE_SIZE);
1073 
1074     chp->cq.size = hwentries;
1075     chp->cq.memsize = memsize;
1076     chp->cq.vector = vector;
1077 
1078     ret = create_cq(&rhp->rdev, &chp->cq,
1079             ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
1080             chp->wr_waitp);
1081     if (ret)
1082         goto err_free_skb;
1083 
1084     chp->rhp = rhp;
1085     chp->cq.size--;             /* status page */
1086     chp->ibcq.cqe = entries - 2;
1087     spin_lock_init(&chp->lock);
1088     spin_lock_init(&chp->comp_handler_lock);
1089     refcount_set(&chp->refcnt, 1);
1090     init_completion(&chp->cq_rel_comp);
1091     ret = xa_insert_irq(&rhp->cqs, chp->cq.cqid, chp, GFP_KERNEL);
1092     if (ret)
1093         goto err_destroy_cq;
1094 
1095     if (ucontext) {
1096         ret = -ENOMEM;
1097         mm = kmalloc(sizeof(*mm), GFP_KERNEL);
1098         if (!mm)
1099             goto err_remove_handle;
1100         mm2 = kmalloc(sizeof(*mm2), GFP_KERNEL);
1101         if (!mm2)
1102             goto err_free_mm;
1103 
1104         memset(&uresp, 0, sizeof(uresp));
1105         uresp.qid_mask = rhp->rdev.cqmask;
1106         uresp.cqid = chp->cq.cqid;
1107         uresp.size = chp->cq.size;
1108         uresp.memsize = chp->cq.memsize;
1109         spin_lock(&ucontext->mmap_lock);
1110         uresp.key = ucontext->key;
1111         ucontext->key += PAGE_SIZE;
1112         uresp.gts_key = ucontext->key;
1113         ucontext->key += PAGE_SIZE;
1114         /* communicate to the userspace that
1115          * kernel driver supports 64B CQE
1116          */
1117         uresp.flags |= C4IW_64B_CQE;
1118 
1119         spin_unlock(&ucontext->mmap_lock);
1120         ret = ib_copy_to_udata(udata, &uresp,
1121                        ucontext->is_32b_cqe ?
1122                        sizeof(uresp) - sizeof(uresp.flags) :
1123                        sizeof(uresp));
1124         if (ret)
1125             goto err_free_mm2;
1126 
1127         mm->key = uresp.key;
1128         mm->addr = virt_to_phys(chp->cq.queue);
1129         mm->len = chp->cq.memsize;
1130         insert_mmap(ucontext, mm);
1131 
1132         mm2->key = uresp.gts_key;
1133         mm2->addr = chp->cq.bar2_pa;
1134         mm2->len = PAGE_SIZE;
1135         insert_mmap(ucontext, mm2);
1136     }
1137 
1138     pr_debug("cqid 0x%0x chp %p size %u memsize %zu, dma_addr %pad\n",
1139          chp->cq.cqid, chp, chp->cq.size, chp->cq.memsize,
1140          &chp->cq.dma_addr);
1141     return 0;
1142 err_free_mm2:
1143     kfree(mm2);
1144 err_free_mm:
1145     kfree(mm);
1146 err_remove_handle:
1147     xa_erase_irq(&rhp->cqs, chp->cq.cqid);
1148 err_destroy_cq:
1149     destroy_cq(&chp->rhp->rdev, &chp->cq,
1150            ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
1151            chp->destroy_skb, chp->wr_waitp);
1152 err_free_skb:
1153     kfree_skb(chp->destroy_skb);
1154 err_free_wr_wait:
1155     c4iw_put_wr_wait(chp->wr_waitp);
1156 err_free_chp:
1157     return ret;
1158 }
1159 
1160 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
1161 {
1162     struct c4iw_cq *chp;
1163     int ret = 0;
1164     unsigned long flag;
1165 
1166     chp = to_c4iw_cq(ibcq);
1167     spin_lock_irqsave(&chp->lock, flag);
1168     t4_arm_cq(&chp->cq,
1169           (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED);
1170     if (flags & IB_CQ_REPORT_MISSED_EVENTS)
1171         ret = t4_cq_notempty(&chp->cq);
1172     spin_unlock_irqrestore(&chp->lock, flag);
1173     return ret;
1174 }
1175 
1176 void c4iw_flush_srqidx(struct c4iw_qp *qhp, u32 srqidx)
1177 {
1178     struct c4iw_cq *rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1179     unsigned long flag;
1180 
1181     /* locking heirarchy: cq lock first, then qp lock. */
1182     spin_lock_irqsave(&rchp->lock, flag);
1183     spin_lock(&qhp->lock);
1184 
1185     /* create a SRQ RECV CQE for srqidx */
1186     insert_recv_cqe(&qhp->wq, &rchp->cq, srqidx);
1187 
1188     spin_unlock(&qhp->lock);
1189     spin_unlock_irqrestore(&rchp->lock, flag);
1190 }
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