hw/bnxt_re/qplib_res.h

0001 /*
0002  * Broadcom NetXtreme-E RoCE driver.
0003  *
0004  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
0005  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
0006  *
0007  * This software is available to you under a choice of one of two
0008  * licenses.  You may choose to be licensed under the terms of the GNU
0009  * General Public License (GPL) Version 2, available from the file
0010  * COPYING in the main directory of this source tree, or the
0011  * BSD license below:
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  *
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in
0021  *    the documentation and/or other materials provided with the
0022  *    distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
0026  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
0027  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
0028  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
0031  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
0032  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
0033  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
0034  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0035  *
0036  * Description: QPLib resource manager (header)
0037  */
0038
0039 #ifndef __BNXT_QPLIB_RES_H__
0040 #define __BNXT_QPLIB_RES_H__
0041
0042 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
0043
0044 #define CHIP_NUM_57508      0x1750
0045 #define CHIP_NUM_57504      0x1751
0046 #define CHIP_NUM_57502      0x1752
0047
0048 struct bnxt_qplib_drv_modes {
0049     u8  wqe_mode;
0050     /* Other modes to follow here */
0051 };
0052
0053 struct bnxt_qplib_chip_ctx {
0054     u16 chip_num;
0055     u8  chip_rev;
0056     u8  chip_metal;
0057     u16 hw_stats_size;
0058     struct bnxt_qplib_drv_modes modes;
0059 };
0060
0061 #define PTR_CNT_PER_PG      (PAGE_SIZE / sizeof(void *))
0062 #define PTR_MAX_IDX_PER_PG  (PTR_CNT_PER_PG - 1)
0063 #define PTR_PG(x)       (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
0064 #define PTR_IDX(x)      ((x) & PTR_MAX_IDX_PER_PG)
0065
0066 #define HWQ_CMP(idx, hwq)   ((idx) & ((hwq)->max_elements - 1))
0067
0068 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
0069                 ((HWQ_CMP(hwq->prod, hwq)\
0070                 - HWQ_CMP(hwq->cons, hwq))\
0071                 & (hwq->max_elements - 1)))
0072 enum bnxt_qplib_hwq_type {
0073     HWQ_TYPE_CTX,
0074     HWQ_TYPE_QUEUE,
0075     HWQ_TYPE_L2_CMPL,
0076     HWQ_TYPE_MR
0077 };
0078
0079 #define MAX_PBL_LVL_0_PGS       1
0080 #define MAX_PBL_LVL_1_PGS       512
0081 #define MAX_PBL_LVL_1_PGS_SHIFT     9
0082 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
0083 #define MAX_PBL_LVL_2_PGS       (256 * 512)
0084 #define MAX_PDL_LVL_SHIFT               9
0085
0086 enum bnxt_qplib_pbl_lvl {
0087     PBL_LVL_0,
0088     PBL_LVL_1,
0089     PBL_LVL_2,
0090     PBL_LVL_MAX
0091 };
0092
0093 #define ROCE_PG_SIZE_4K     (4 * 1024)
0094 #define ROCE_PG_SIZE_8K     (8 * 1024)
0095 #define ROCE_PG_SIZE_64K    (64 * 1024)
0096 #define ROCE_PG_SIZE_2M     (2 * 1024 * 1024)
0097 #define ROCE_PG_SIZE_8M     (8 * 1024 * 1024)
0098 #define ROCE_PG_SIZE_1G     (1024 * 1024 * 1024)
0099
0100 enum bnxt_qplib_hwrm_pg_size {
0101     BNXT_QPLIB_HWRM_PG_SIZE_4K  = 0,
0102     BNXT_QPLIB_HWRM_PG_SIZE_8K  = 1,
0103     BNXT_QPLIB_HWRM_PG_SIZE_64K = 2,
0104     BNXT_QPLIB_HWRM_PG_SIZE_2M  = 3,
0105     BNXT_QPLIB_HWRM_PG_SIZE_8M  = 4,
0106     BNXT_QPLIB_HWRM_PG_SIZE_1G  = 5,
0107 };
0108
0109 struct bnxt_qplib_reg_desc {
0110     u8      bar_id;
0111     resource_size_t bar_base;
0112     void __iomem    *bar_reg;
0113     size_t      len;
0114 };
0115
0116 struct bnxt_qplib_pbl {
0117     u32             pg_count;
0118     u32             pg_size;
0119     void                **pg_arr;
0120     dma_addr_t          *pg_map_arr;
0121 };
0122
0123 struct bnxt_qplib_sg_info {
0124     struct ib_umem          *umem;
0125     u32             npages;
0126     u32             pgshft;
0127     u32             pgsize;
0128     bool                nopte;
0129 };
0130
0131 struct bnxt_qplib_hwq_attr {
0132     struct bnxt_qplib_res       *res;
0133     struct bnxt_qplib_sg_info   *sginfo;
0134     enum bnxt_qplib_hwq_type    type;
0135     u32             depth;
0136     u32             stride;
0137     u32             aux_stride;
0138     u32             aux_depth;
0139 };
0140
0141 struct bnxt_qplib_hwq {
0142     struct pci_dev          *pdev;
0143     /* lock to protect qplib_hwq */
0144     spinlock_t          lock;
0145     struct bnxt_qplib_pbl       pbl[PBL_LVL_MAX + 1];
0146     enum bnxt_qplib_pbl_lvl     level;      /* 0, 1, or 2 */
0147     /* ptr for easy access to the PBL entries */
0148     void                **pbl_ptr;
0149     /* ptr for easy access to the dma_addr */
0150     dma_addr_t          *pbl_dma_ptr;
0151     u32             max_elements;
0152     u32             depth;
0153     u16             element_size;   /* Size of each entry */
0154     u16             qe_ppg; /* queue entry per page */
0155
0156     u32             prod;       /* raw */
0157     u32             cons;       /* raw */
0158     u8              cp_bit;
0159     u8              is_user;
0160     u64             *pad_pg;
0161     u32             pad_stride;
0162     u32             pad_pgofft;
0163 };
0164
0165 struct bnxt_qplib_db_info {
0166     void __iomem        *db;
0167     void __iomem        *priv_db;
0168     struct bnxt_qplib_hwq   *hwq;
0169     u32         xid;
0170     u32         max_slot;
0171 };
0172
0173 /* Tables */
0174 struct bnxt_qplib_pd_tbl {
0175     unsigned long           *tbl;
0176     u32             max;
0177 };
0178
0179 struct bnxt_qplib_sgid_tbl {
0180     struct bnxt_qplib_gid_info  *tbl;
0181     u16             *hw_id;
0182     u16             max;
0183     u16             active;
0184     void                *ctx;
0185     u8              *vlan;
0186 };
0187
0188 struct bnxt_qplib_dpi {
0189     u32             dpi;
0190     void __iomem            *dbr;
0191     u64             umdbr;
0192 };
0193
0194 struct bnxt_qplib_dpi_tbl {
0195     void                **app_tbl;
0196     unsigned long           *tbl;
0197     u16             max;
0198     void __iomem            *dbr_bar_reg_iomem;
0199     u64             unmapped_dbr;
0200 };
0201
0202 struct bnxt_qplib_stats {
0203     dma_addr_t          dma_map;
0204     void                *dma;
0205     u32             size;
0206     u32             fw_id;
0207 };
0208
0209 struct bnxt_qplib_vf_res {
0210     u32 max_qp_per_vf;
0211     u32 max_mrw_per_vf;
0212     u32 max_srq_per_vf;
0213     u32 max_cq_per_vf;
0214     u32 max_gid_per_vf;
0215 };
0216
0217 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE    448
0218 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE   64
0219 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE    64
0220 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE   128
0221
0222 #define MAX_TQM_ALLOC_REQ               48
0223 #define MAX_TQM_ALLOC_BLK_SIZE          8
0224 struct bnxt_qplib_tqm_ctx {
0225     struct bnxt_qplib_hwq           pde;
0226     u8                              pde_level; /* Original level */
0227     struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
0228     u8                              qcount[MAX_TQM_ALLOC_REQ];
0229 };
0230
0231 struct bnxt_qplib_ctx {
0232     u32             qpc_count;
0233     struct bnxt_qplib_hwq       qpc_tbl;
0234     u32             mrw_count;
0235     struct bnxt_qplib_hwq       mrw_tbl;
0236     u32             srqc_count;
0237     struct bnxt_qplib_hwq       srqc_tbl;
0238     u32             cq_count;
0239     struct bnxt_qplib_hwq       cq_tbl;
0240     struct bnxt_qplib_hwq       tim_tbl;
0241     struct bnxt_qplib_tqm_ctx   tqm_ctx;
0242     struct bnxt_qplib_stats     stats;
0243     struct bnxt_qplib_vf_res    vf_res;
0244     u64             hwrm_intf_ver;
0245 };
0246
0247 struct bnxt_qplib_res {
0248     struct pci_dev          *pdev;
0249     struct bnxt_qplib_chip_ctx  *cctx;
0250     struct bnxt_qplib_dev_attr      *dattr;
0251     struct net_device       *netdev;
0252     struct bnxt_qplib_rcfw      *rcfw;
0253     struct bnxt_qplib_pd_tbl    pd_tbl;
0254     struct bnxt_qplib_sgid_tbl  sgid_tbl;
0255     struct bnxt_qplib_dpi_tbl   dpi_tbl;
0256     bool                prio;
0257     bool                            is_vf;
0258 };
0259
0260 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
0261 {
0262     return (cctx->chip_num == CHIP_NUM_57508 ||
0263         cctx->chip_num == CHIP_NUM_57504 ||
0264         cctx->chip_num == CHIP_NUM_57502);
0265 }
0266
0267 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
0268 {
0269     return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
0270                     HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
0271 }
0272
0273 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
0274 {
0275     return bnxt_qplib_is_chip_gen_p5(cctx) ?
0276            RING_ALLOC_REQ_RING_TYPE_NQ :
0277            RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
0278 }
0279
0280 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
0281 {
0282     u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
0283     struct bnxt_qplib_pbl *pbl;
0284
0285     pbl = &hwq->pbl[PBL_LVL_0];
0286     switch (pbl->pg_size) {
0287     case ROCE_PG_SIZE_4K:
0288         pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
0289         break;
0290     case ROCE_PG_SIZE_8K:
0291         pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
0292         break;
0293     case ROCE_PG_SIZE_64K:
0294         pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
0295         break;
0296     case ROCE_PG_SIZE_2M:
0297         pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
0298         break;
0299     case ROCE_PG_SIZE_8M:
0300         pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
0301         break;
0302     case ROCE_PG_SIZE_1G:
0303         pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
0304         break;
0305     default:
0306         break;
0307     }
0308
0309     return pg_size;
0310 }
0311
0312 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
0313                       u32 indx, u64 *pg)
0314 {
0315     u32 pg_num, pg_idx;
0316
0317     pg_num = (indx / hwq->qe_ppg);
0318     pg_idx = (indx % hwq->qe_ppg);
0319     if (pg)
0320         *pg = (u64)&hwq->pbl_ptr[pg_num];
0321     return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
0322 }
0323
0324 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
0325 {
0326     idx += hwq->prod;
0327     if (idx >= hwq->depth)
0328         idx -= hwq->depth;
0329     return bnxt_qplib_get_qe(hwq, idx, NULL);
0330 }
0331
0332 #define to_bnxt_qplib(ptr, type, member)    \
0333     container_of(ptr, type, member)
0334
0335 struct bnxt_qplib_pd;
0336 struct bnxt_qplib_dev_attr;
0337
0338 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
0339              struct bnxt_qplib_hwq *hwq);
0340 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
0341                   struct bnxt_qplib_hwq_attr *hwq_attr);
0342 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
0343             struct bnxt_qplib_pd *pd);
0344 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
0345               struct bnxt_qplib_pd_tbl *pd_tbl,
0346               struct bnxt_qplib_pd *pd);
0347 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
0348              struct bnxt_qplib_dpi     *dpi,
0349              void                      *app);
0350 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
0351                struct bnxt_qplib_dpi_tbl *dpi_tbl,
0352                struct bnxt_qplib_dpi *dpi);
0353 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
0354 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
0355 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
0356 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
0357              struct net_device *netdev,
0358              struct bnxt_qplib_dev_attr *dev_attr);
0359 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
0360              struct bnxt_qplib_ctx *ctx);
0361 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
0362              struct bnxt_qplib_ctx *ctx,
0363              bool virt_fn, bool is_p5);
0364 int bnxt_qplib_determine_atomics(struct pci_dev *dev);
0365
0366 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
0367 {
0368     hwq->prod = (hwq->prod + cnt) % hwq->depth;
0369 }
0370
0371 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
0372                         u32 cnt)
0373 {
0374     hwq->cons = (hwq->cons + cnt) % hwq->depth;
0375 }
0376
0377 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
0378                     bool arm)
0379 {
0380     u32 key;
0381
0382     key = info->hwq->cons & (info->hwq->max_elements - 1);
0383     key |= (CMPL_DOORBELL_IDX_VALID |
0384         (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
0385     if (!arm)
0386         key |= CMPL_DOORBELL_MASK;
0387     writel(key, info->db);
0388 }
0389
0390 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
0391                       u32 type)
0392 {
0393     u64 key = 0;
0394
0395     key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
0396     key <<= 32;
0397     key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
0398         DBC_DBC_INDEX_MASK;
0399     writeq(key, info->db);
0400 }
0401
0402 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
0403                        u32 type)
0404 {
0405     u64 key = 0;
0406
0407     key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
0408     key <<= 32;
0409     key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
0410     writeq(key, info->db);
0411 }
0412
0413 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
0414                        u32 type)
0415 {
0416     u64 key = 0;
0417
0418     key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
0419     key <<= 32;
0420     writeq(key, info->priv_db);
0421 }
0422
0423 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
0424                      u32 th)
0425 {
0426     u64 key = 0;
0427
0428     key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
0429     key <<= 32;
0430     key |=  th & DBC_DBC_INDEX_MASK;
0431     writeq(key, info->priv_db);
0432 }
0433
0434 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
0435                      struct bnxt_qplib_chip_ctx *cctx,
0436                      bool arm)
0437 {
0438     u32 type;
0439
0440     type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
0441     if (bnxt_qplib_is_chip_gen_p5(cctx))
0442         bnxt_qplib_ring_db(info, type);
0443     else
0444         bnxt_qplib_ring_db32(info, arm);
0445 }
0446
0447 static inline bool _is_ext_stats_supported(u16 dev_cap_flags)
0448 {
0449     return dev_cap_flags &
0450         CREQ_QUERY_FUNC_RESP_SB_EXT_STATS;
0451 }
0452 #endif /* __BNXT_QPLIB_RES_H__ */