hw/bnxt_re/qplib_rcfw.h

0001 /*
0002  * Broadcom NetXtreme-E RoCE driver.
0003  *
0004  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
0005  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
0006  *
0007  * This software is available to you under a choice of one of two
0008  * licenses.  You may choose to be licensed under the terms of the GNU
0009  * General Public License (GPL) Version 2, available from the file
0010  * COPYING in the main directory of this source tree, or the
0011  * BSD license below:
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  *
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in
0021  *    the documentation and/or other materials provided with the
0022  *    distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
0026  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
0027  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
0028  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
0031  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
0032  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
0033  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
0034  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0035  *
0036  * Description: RDMA Controller HW interface (header)
0037  */
0038
0039 #ifndef __BNXT_QPLIB_RCFW_H__
0040 #define __BNXT_QPLIB_RCFW_H__
0041
0042 #define RCFW_CMDQ_TRIG_VAL      1
0043 #define RCFW_COMM_PCI_BAR_REGION    0
0044 #define RCFW_COMM_CONS_PCI_BAR_REGION   2
0045 #define RCFW_COMM_BASE_OFFSET       0x600
0046 #define RCFW_PF_COMM_PROD_OFFSET    0xc
0047 #define RCFW_VF_COMM_PROD_OFFSET    0xc
0048 #define RCFW_COMM_TRIG_OFFSET       0x100
0049 #define RCFW_COMM_SIZE          0x104
0050
0051 #define RCFW_DBR_PCI_BAR_REGION     2
0052 #define RCFW_DBR_BASE_PAGE_SHIFT    12
0053
0054 #define RCFW_CMD_PREP(req, CMD, cmd_flags)              \
0055     do {                                \
0056         memset(&(req), 0, sizeof((req)));           \
0057         (req).opcode = CMDQ_BASE_OPCODE_##CMD;          \
0058         (req).cmd_size = sizeof((req));             \
0059         (req).flags = cpu_to_le16(cmd_flags);           \
0060     } while (0)
0061
0062 #define RCFW_CMD_WAIT_TIME_MS       20000 /* 20 Seconds timeout */
0063
0064 /* Cmdq contains a fix number of a 16-Byte slots */
0065 struct bnxt_qplib_cmdqe {
0066     u8      data[16];
0067 };
0068
0069 /* CMDQ elements */
0070 #define BNXT_QPLIB_CMDQE_MAX_CNT_256    256
0071 #define BNXT_QPLIB_CMDQE_MAX_CNT_8192   8192
0072 #define BNXT_QPLIB_CMDQE_UNITS      sizeof(struct bnxt_qplib_cmdqe)
0073 #define BNXT_QPLIB_CMDQE_BYTES(depth)   ((depth) * BNXT_QPLIB_CMDQE_UNITS)
0074
0075 static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
0076 {
0077     u32 npages;
0078
0079     npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
0080     if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
0081         npages++;
0082     return npages;
0083 }
0084
0085 static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
0086 {
0087     return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
0088 }
0089
0090 /* Set the cmd_size to a factor of CMDQE unit */
0091 static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req)
0092 {
0093     req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) /
0094              BNXT_QPLIB_CMDQE_UNITS;
0095 }
0096
0097 #define RCFW_MAX_COOKIE_VALUE       0x7FFF
0098 #define RCFW_CMD_IS_BLOCKING        0x8000
0099 #define RCFW_BLOCKED_CMD_WAIT_COUNT 20000000UL /* 20 sec */
0100
0101 #define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
0102
0103 /* Crsq buf is 1024-Byte */
0104 struct bnxt_qplib_crsbe {
0105     u8          data[1024];
0106 };
0107
0108 /* CREQ */
0109 /* Allocate 1 per QP for async error notification for now */
0110 #define BNXT_QPLIB_CREQE_MAX_CNT    (64 * 1024)
0111 #define BNXT_QPLIB_CREQE_UNITS      16  /* 16-Bytes per prod unit */
0112 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)           \
0113     (!!((hdr)->v & CREQ_BASE_V) ==              \
0114        !((raw_cons) & (cp_bit)))
0115 #define CREQ_ENTRY_POLL_BUDGET      0x100
0116
0117 /* HWQ */
0118 typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *);
0119
0120 struct bnxt_qplib_crsqe {
0121     struct creq_qp_event    *resp;
0122     u32         req_size;
0123 };
0124
0125 struct bnxt_qplib_rcfw_sbuf {
0126     void *sb;
0127     dma_addr_t dma_addr;
0128     u32 size;
0129 };
0130
0131 struct bnxt_qplib_qp_node {
0132     u32 qp_id;              /* QP id */
0133     void *qp_handle;        /* ptr to qplib_qp */
0134 };
0135
0136 #define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
0137
0138 #define FIRMWARE_INITIALIZED_FLAG   (0)
0139 #define FIRMWARE_FIRST_FLAG     (31)
0140 #define FIRMWARE_TIMED_OUT      (3)
0141 #define ERR_DEVICE_DETACHED             (4)
0142
0143 struct bnxt_qplib_cmdq_mbox {
0144     struct bnxt_qplib_reg_desc  reg;
0145     void __iomem            *prod;
0146     void __iomem            *db;
0147 };
0148
0149 struct bnxt_qplib_cmdq_ctx {
0150     struct bnxt_qplib_hwq       hwq;
0151     struct bnxt_qplib_cmdq_mbox cmdq_mbox;
0152     wait_queue_head_t       waitq;
0153     unsigned long           flags;
0154     unsigned long           *cmdq_bitmap;
0155     u32             seq_num;
0156 };
0157
0158 struct bnxt_qplib_creq_db {
0159     struct bnxt_qplib_reg_desc  reg;
0160     struct bnxt_qplib_db_info   dbinfo;
0161 };
0162
0163 struct bnxt_qplib_creq_stat {
0164     u64 creq_qp_event_processed;
0165     u64 creq_func_event_processed;
0166 };
0167
0168 struct bnxt_qplib_creq_ctx {
0169     struct bnxt_qplib_hwq       hwq;
0170     struct bnxt_qplib_creq_db   creq_db;
0171     struct bnxt_qplib_creq_stat stats;
0172     struct tasklet_struct       creq_tasklet;
0173     aeq_handler_t           aeq_handler;
0174     u16             ring_id;
0175     int             msix_vec;
0176     bool                requested; /*irq handler installed */
0177 };
0178
0179 /* RCFW Communication Channels */
0180 struct bnxt_qplib_rcfw {
0181     struct pci_dev      *pdev;
0182     struct bnxt_qplib_res   *res;
0183     struct bnxt_qplib_cmdq_ctx  cmdq;
0184     struct bnxt_qplib_creq_ctx  creq;
0185     struct bnxt_qplib_crsqe     *crsqe_tbl;
0186     int qp_tbl_size;
0187     struct bnxt_qplib_qp_node *qp_tbl;
0188     u64 oos_prev;
0189     u32 init_oos_stats;
0190     u32 cmdq_depth;
0191 };
0192
0193 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
0194 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
0195                   struct bnxt_qplib_rcfw *rcfw,
0196                   struct bnxt_qplib_ctx *ctx,
0197                   int qp_tbl_sz);
0198 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
0199 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
0200 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
0201                   bool need_init);
0202 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
0203                    int msix_vector,
0204                    int cp_bar_reg_off, int virt_fn,
0205                    aeq_handler_t aeq_handler);
0206
0207 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
0208                 struct bnxt_qplib_rcfw *rcfw,
0209                 u32 size);
0210 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
0211                    struct bnxt_qplib_rcfw_sbuf *sbuf);
0212 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
0213                  struct cmdq_base *req, struct creq_base *resp,
0214                  void *sbuf, u8 is_block);
0215
0216 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
0217 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
0218              struct bnxt_qplib_ctx *ctx, int is_virtfn);
0219 void bnxt_qplib_mark_qp_error(void *qp_handle);
0220 static inline u32 map_qp_id_to_tbl_indx(u32 qid, struct bnxt_qplib_rcfw *rcfw)
0221 {
0222     /* Last index of the qp_tbl is for QP1 ie. qp_tbl_size - 1*/
0223     return (qid == 1) ? rcfw->qp_tbl_size - 1 : qid % rcfw->qp_tbl_size - 2;
0224 }
0225 #endif /* __BNXT_QPLIB_RCFW_H__ */