hw/bnxt_re/qplib_fp.h

0001 /*
0002  * Broadcom NetXtreme-E RoCE driver.
0003  *
0004  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
0005  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
0006  *
0007  * This software is available to you under a choice of one of two
0008  * licenses.  You may choose to be licensed under the terms of the GNU
0009  * General Public License (GPL) Version 2, available from the file
0010  * COPYING in the main directory of this source tree, or the
0011  * BSD license below:
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  *
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in
0021  *    the documentation and/or other materials provided with the
0022  *    distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
0026  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
0027  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
0028  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
0031  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
0032  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
0033  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
0034  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0035  *
0036  * Description: Fast Path Operators (header)
0037  */
0038
0039 #ifndef __BNXT_QPLIB_FP_H__
0040 #define __BNXT_QPLIB_FP_H__
0041
0042 #include <rdma/bnxt_re-abi.h>
0043
0044 /* Few helper structures temporarily defined here
0045  * should get rid of these when roce_hsi.h is updated
0046  * in original code base
0047  */
0048 struct sq_ud_ext_hdr {
0049     __le32 dst_qp;
0050     __le32 avid;
0051     __le64 rsvd;
0052 };
0053
0054 struct sq_raw_ext_hdr {
0055     __le32 cfa_meta;
0056     __le32 rsvd0;
0057     __le64 rsvd1;
0058 };
0059
0060 struct sq_rdma_ext_hdr {
0061     __le64 remote_va;
0062     __le32 remote_key;
0063     __le32 rsvd;
0064 };
0065
0066 struct sq_atomic_ext_hdr {
0067     __le64 swap_data;
0068     __le64 cmp_data;
0069 };
0070
0071 struct sq_fr_pmr_ext_hdr {
0072     __le64 pblptr;
0073     __le64 va;
0074 };
0075
0076 struct sq_bind_ext_hdr {
0077     __le64 va;
0078     __le32 length_lo;
0079     __le32 length_hi;
0080 };
0081
0082 struct rq_ext_hdr {
0083     __le64 rsvd1;
0084     __le64 rsvd2;
0085 };
0086
0087 /* Helper structures end */
0088
0089 struct bnxt_qplib_srq {
0090     struct bnxt_qplib_pd        *pd;
0091     struct bnxt_qplib_dpi       *dpi;
0092     struct bnxt_qplib_db_info   dbinfo;
0093     u64             srq_handle;
0094     u32             id;
0095     u16             wqe_size;
0096     u32             max_wqe;
0097     u32             max_sge;
0098     u32             threshold;
0099     bool                arm_req;
0100     struct bnxt_qplib_cq        *cq;
0101     struct bnxt_qplib_hwq       hwq;
0102     struct bnxt_qplib_swq       *swq;
0103     int             start_idx;
0104     int             last_idx;
0105     struct bnxt_qplib_sg_info   sg_info;
0106     u16             eventq_hw_ring_id;
0107     spinlock_t          lock; /* protect SRQE link list */
0108 };
0109
0110 struct bnxt_qplib_sge {
0111     u64             addr;
0112     u32             lkey;
0113     u32             size;
0114 };
0115
0116 #define BNXT_QPLIB_QP_MAX_SGL   6
0117 struct bnxt_qplib_swq {
0118     u64             wr_id;
0119     int             next_idx;
0120     u8              type;
0121     u8              flags;
0122     u32             start_psn;
0123     u32             next_psn;
0124     u32             slot_idx;
0125     u8              slots;
0126     struct sq_psn_search        *psn_search;
0127     struct sq_psn_search_ext    *psn_ext;
0128 };
0129
0130 struct bnxt_qplib_swqe {
0131     /* General */
0132 #define BNXT_QPLIB_FENCE_WRID   0x46454E43  /* "FENC" */
0133     u64             wr_id;
0134     u8              reqs_type;
0135     u8              type;
0136 #define BNXT_QPLIB_SWQE_TYPE_SEND           0
0137 #define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM      1
0138 #define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV      2
0139 #define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE         4
0140 #define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM    5
0141 #define BNXT_QPLIB_SWQE_TYPE_RDMA_READ          6
0142 #define BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP     8
0143 #define BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD   11
0144 #define BNXT_QPLIB_SWQE_TYPE_LOCAL_INV          12
0145 #define BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR        13
0146 #define BNXT_QPLIB_SWQE_TYPE_REG_MR         13
0147 #define BNXT_QPLIB_SWQE_TYPE_BIND_MW            14
0148 #define BNXT_QPLIB_SWQE_TYPE_RECV           128
0149 #define BNXT_QPLIB_SWQE_TYPE_RECV_RDMA_IMM      129
0150     u8              flags;
0151 #define BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP       BIT(0)
0152 #define BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE       BIT(1)
0153 #define BNXT_QPLIB_SWQE_FLAGS_UC_FENCE          BIT(2)
0154 #define BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT     BIT(3)
0155 #define BNXT_QPLIB_SWQE_FLAGS_INLINE            BIT(4)
0156     struct bnxt_qplib_sge       sg_list[BNXT_QPLIB_QP_MAX_SGL];
0157     int             num_sge;
0158     /* Max inline data is 96 bytes */
0159     u32             inline_len;
0160 #define BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH       96
0161     u8      inline_data[BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH];
0162
0163     union {
0164         /* Send, with imm, inval key */
0165         struct {
0166             union {
0167                 __be32  imm_data;
0168                 u32 inv_key;
0169             };
0170             u32     q_key;
0171             u32     dst_qp;
0172             u16     avid;
0173         } send;
0174
0175         /* Send Raw Ethernet and QP1 */
0176         struct {
0177             u16     lflags;
0178             u16     cfa_action;
0179             u32     cfa_meta;
0180         } rawqp1;
0181
0182         /* RDMA write, with imm, read */
0183         struct {
0184             union {
0185                 __be32  imm_data;
0186                 u32 inv_key;
0187             };
0188             u64     remote_va;
0189             u32     r_key;
0190         } rdma;
0191
0192         /* Atomic cmp/swap, fetch/add */
0193         struct {
0194             u64     remote_va;
0195             u32     r_key;
0196             u64     swap_data;
0197             u64     cmp_data;
0198         } atomic;
0199
0200         /* Local Invalidate */
0201         struct {
0202             u32     inv_l_key;
0203         } local_inv;
0204
0205         /* FR-PMR */
0206         struct {
0207             u8      access_cntl;
0208             u8      pg_sz_log;
0209             bool        zero_based;
0210             u32     l_key;
0211             u32     length;
0212             u8      pbl_pg_sz_log;
0213 #define BNXT_QPLIB_SWQE_PAGE_SIZE_4K            0
0214 #define BNXT_QPLIB_SWQE_PAGE_SIZE_8K            1
0215 #define BNXT_QPLIB_SWQE_PAGE_SIZE_64K           4
0216 #define BNXT_QPLIB_SWQE_PAGE_SIZE_256K          6
0217 #define BNXT_QPLIB_SWQE_PAGE_SIZE_1M            8
0218 #define BNXT_QPLIB_SWQE_PAGE_SIZE_2M            9
0219 #define BNXT_QPLIB_SWQE_PAGE_SIZE_4M            10
0220 #define BNXT_QPLIB_SWQE_PAGE_SIZE_1G            18
0221             u8      levels;
0222 #define PAGE_SHIFT_4K   12
0223             __le64      *pbl_ptr;
0224             dma_addr_t  pbl_dma_ptr;
0225             u64     *page_list;
0226             u16     page_list_len;
0227             u64     va;
0228         } frmr;
0229
0230         /* Bind */
0231         struct {
0232             u8      access_cntl;
0233 #define BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE     BIT(0)
0234 #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ     BIT(1)
0235 #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE    BIT(2)
0236 #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC   BIT(3)
0237 #define BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND     BIT(4)
0238             bool        zero_based;
0239             u8      mw_type;
0240             u32     parent_l_key;
0241             u32     r_key;
0242             u64     va;
0243             u32     length;
0244         } bind;
0245     };
0246 };
0247
0248 struct bnxt_qplib_q {
0249     struct bnxt_qplib_hwq       hwq;
0250     struct bnxt_qplib_swq       *swq;
0251     struct bnxt_qplib_db_info   dbinfo;
0252     struct bnxt_qplib_sg_info   sg_info;
0253     u32             max_wqe;
0254     u16             wqe_size;
0255     u16             q_full_delta;
0256     u16             max_sge;
0257     u32             psn;
0258     bool                condition;
0259     bool                single;
0260     bool                send_phantom;
0261     u32             phantom_wqe_cnt;
0262     u32             phantom_cqe_cnt;
0263     u32             next_cq_cons;
0264     bool                flushed;
0265     u32             swq_start;
0266     u32             swq_last;
0267 };
0268
0269 struct bnxt_qplib_qp {
0270     struct bnxt_qplib_pd        *pd;
0271     struct bnxt_qplib_dpi       *dpi;
0272     struct bnxt_qplib_chip_ctx  *cctx;
0273     u64             qp_handle;
0274 #define BNXT_QPLIB_QP_ID_INVALID        0xFFFFFFFF
0275     u32             id;
0276     u8              type;
0277     u8              sig_type;
0278     u8              wqe_mode;
0279     u8              state;
0280     u8              cur_qp_state;
0281     u64             modify_flags;
0282     u32             max_inline_data;
0283     u32             mtu;
0284     u8              path_mtu;
0285     bool                en_sqd_async_notify;
0286     u16             pkey_index;
0287     u32             qkey;
0288     u32             dest_qp_id;
0289     u8              access;
0290     u8              timeout;
0291     u8              retry_cnt;
0292     u8              rnr_retry;
0293     u64             wqe_cnt;
0294     u32             min_rnr_timer;
0295     u32             max_rd_atomic;
0296     u32             max_dest_rd_atomic;
0297     u32             dest_qpn;
0298     u8              smac[6];
0299     u16             vlan_id;
0300     u8              nw_type;
0301     struct bnxt_qplib_ah        ah;
0302
0303 #define BTH_PSN_MASK            ((1 << 24) - 1)
0304     /* SQ */
0305     struct bnxt_qplib_q     sq;
0306     /* RQ */
0307     struct bnxt_qplib_q     rq;
0308     /* SRQ */
0309     struct bnxt_qplib_srq       *srq;
0310     /* CQ */
0311     struct bnxt_qplib_cq        *scq;
0312     struct bnxt_qplib_cq        *rcq;
0313     /* IRRQ and ORRQ */
0314     struct bnxt_qplib_hwq       irrq;
0315     struct bnxt_qplib_hwq       orrq;
0316     /* Header buffer for QP1 */
0317     int             sq_hdr_buf_size;
0318     int             rq_hdr_buf_size;
0319 /*
0320  * Buffer space for ETH(14), IP or GRH(40), UDP header(8)
0321  * and ib_bth + ib_deth (20).
0322  * Max required is 82 when RoCE V2 is enabled
0323  */
0324 #define BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2   86
0325     /* Ethernet header  =  14 */
0326     /* ib_grh       =  40 (provided by MAD) */
0327     /* ib_bth + ib_deth =  20 */
0328     /* MAD          = 256 (provided by MAD) */
0329     /* iCRC         =   4 */
0330 #define BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE  14
0331 #define BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2   512
0332 #define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4    20
0333 #define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6    40
0334 #define BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE    20
0335     void                *sq_hdr_buf;
0336     dma_addr_t          sq_hdr_buf_map;
0337     void                *rq_hdr_buf;
0338     dma_addr_t          rq_hdr_buf_map;
0339     struct list_head        sq_flush;
0340     struct list_head        rq_flush;
0341 };
0342
0343 #define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE   sizeof(struct cq_base)
0344
0345 #define CQE_CNT_PER_PG      (PAGE_SIZE / BNXT_QPLIB_MAX_CQE_ENTRY_SIZE)
0346 #define CQE_MAX_IDX_PER_PG  (CQE_CNT_PER_PG - 1)
0347 #define CQE_PG(x)       (((x) & ~CQE_MAX_IDX_PER_PG) / CQE_CNT_PER_PG)
0348 #define CQE_IDX(x)      ((x) & CQE_MAX_IDX_PER_PG)
0349
0350 #define ROCE_CQE_CMP_V          0
0351 #define CQE_CMP_VALID(hdr, raw_cons, cp_bit)            \
0352     (!!((hdr)->cqe_type_toggle & CQ_BASE_TOGGLE) ==     \
0353        !((raw_cons) & (cp_bit)))
0354
0355 static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *que,
0356                      u8 slots)
0357 {
0358     struct bnxt_qplib_hwq *hwq;
0359     int avail;
0360
0361     hwq = &que->hwq;
0362     /* False full is possible, retrying post-send makes sense */
0363     avail = hwq->cons - hwq->prod;
0364     if (hwq->cons <= hwq->prod)
0365         avail += hwq->depth;
0366     return avail <= slots;
0367 }
0368
0369 struct bnxt_qplib_cqe {
0370     u8              status;
0371     u8              type;
0372     u8              opcode;
0373     u32             length;
0374     u16             cfa_meta;
0375     u64             wr_id;
0376     union {
0377         __be32          immdata;
0378         u32         invrkey;
0379     };
0380     u64             qp_handle;
0381     u64             mr_handle;
0382     u16             flags;
0383     u8              smac[6];
0384     u32             src_qp;
0385     u16             raweth_qp1_flags;
0386     u16             raweth_qp1_errors;
0387     u16             raweth_qp1_cfa_code;
0388     u32             raweth_qp1_flags2;
0389     u32             raweth_qp1_metadata;
0390     u8              raweth_qp1_payload_offset;
0391     u16             pkey_index;
0392 };
0393
0394 #define BNXT_QPLIB_QUEUE_START_PERIOD       0x01
0395 struct bnxt_qplib_cq {
0396     struct bnxt_qplib_dpi       *dpi;
0397     struct bnxt_qplib_db_info   dbinfo;
0398     u32             max_wqe;
0399     u32             id;
0400     u16             count;
0401     u16             period;
0402     struct bnxt_qplib_hwq       hwq;
0403     u32             cnq_hw_ring_id;
0404     struct bnxt_qplib_nq        *nq;
0405     bool                resize_in_progress;
0406     struct bnxt_qplib_sg_info   sg_info;
0407     u64             cq_handle;
0408
0409 #define CQ_RESIZE_WAIT_TIME_MS      500
0410     unsigned long           flags;
0411 #define CQ_FLAGS_RESIZE_IN_PROG     1
0412     wait_queue_head_t       waitq;
0413     struct list_head        sqf_head, rqf_head;
0414     atomic_t            arm_state;
0415     spinlock_t          compl_lock; /* synch CQ handlers */
0416 /* Locking Notes:
0417  * QP can move to error state from modify_qp, async error event or error
0418  * CQE as part of poll_cq. When QP is moved to error state, it gets added
0419  * to two flush lists, one each for SQ and RQ.
0420  * Each flush list is protected by qplib_cq->flush_lock. Both scq and rcq
0421  * flush_locks should be acquired when QP is moved to error. The control path
0422  * operations(modify_qp and async error events) are synchronized with poll_cq
0423  * using upper level CQ locks (bnxt_re_cq->cq_lock) of both SCQ and RCQ.
0424  * The qplib_cq->flush_lock is required to synchronize two instances of poll_cq
0425  * of the same QP while manipulating the flush list.
0426  */
0427     spinlock_t          flush_lock; /* QP flush management */
0428     u16             cnq_events;
0429 };
0430
0431 #define BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE sizeof(struct xrrq_irrq)
0432 #define BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE sizeof(struct xrrq_orrq)
0433 #define IRD_LIMIT_TO_IRRQ_SLOTS(x)  (2 * (x) + 2)
0434 #define IRRQ_SLOTS_TO_IRD_LIMIT(s)  (((s) >> 1) - 1)
0435 #define ORD_LIMIT_TO_ORRQ_SLOTS(x)  ((x) + 1)
0436 #define ORRQ_SLOTS_TO_ORD_LIMIT(s)  ((s) - 1)
0437
0438 #define BNXT_QPLIB_MAX_NQE_ENTRY_SIZE   sizeof(struct nq_base)
0439
0440 #define NQE_CNT_PER_PG      (PAGE_SIZE / BNXT_QPLIB_MAX_NQE_ENTRY_SIZE)
0441 #define NQE_MAX_IDX_PER_PG  (NQE_CNT_PER_PG - 1)
0442 #define NQE_PG(x)       (((x) & ~NQE_MAX_IDX_PER_PG) / NQE_CNT_PER_PG)
0443 #define NQE_IDX(x)      ((x) & NQE_MAX_IDX_PER_PG)
0444
0445 #define NQE_CMP_VALID(hdr, raw_cons, cp_bit)            \
0446     (!!(le32_to_cpu((hdr)->info63_v[0]) & NQ_BASE_V) == \
0447        !((raw_cons) & (cp_bit)))
0448
0449 #define BNXT_QPLIB_NQE_MAX_CNT      (128 * 1024)
0450
0451 #define NQ_CONS_PCI_BAR_REGION      2
0452 #define NQ_DB_KEY_CP            (0x2 << CMPL_DOORBELL_KEY_SFT)
0453 #define NQ_DB_IDX_VALID         CMPL_DOORBELL_IDX_VALID
0454 #define NQ_DB_IRQ_DIS           CMPL_DOORBELL_MASK
0455 #define NQ_DB_CP_FLAGS_REARM        (NQ_DB_KEY_CP |     \
0456                      NQ_DB_IDX_VALID)
0457 #define NQ_DB_CP_FLAGS          (NQ_DB_KEY_CP    |  \
0458                      NQ_DB_IDX_VALID |  \
0459                      NQ_DB_IRQ_DIS)
0460
0461 struct bnxt_qplib_nq_db {
0462     struct bnxt_qplib_reg_desc  reg;
0463     struct bnxt_qplib_db_info   dbinfo;
0464 };
0465
0466 typedef int (*cqn_handler_t)(struct bnxt_qplib_nq *nq,
0467         struct bnxt_qplib_cq *cq);
0468 typedef int (*srqn_handler_t)(struct bnxt_qplib_nq *nq,
0469         struct bnxt_qplib_srq *srq, u8 event);
0470
0471 struct bnxt_qplib_nq {
0472     struct pci_dev          *pdev;
0473     struct bnxt_qplib_res       *res;
0474     char                name[32];
0475     struct bnxt_qplib_hwq       hwq;
0476     struct bnxt_qplib_nq_db     nq_db;
0477     u16             ring_id;
0478     int             msix_vec;
0479     cpumask_t           mask;
0480     struct tasklet_struct       nq_tasklet;
0481     bool                requested;
0482     int             budget;
0483
0484     cqn_handler_t           cqn_handler;
0485     srqn_handler_t          srqn_handler;
0486     struct workqueue_struct     *cqn_wq;
0487 };
0488
0489 struct bnxt_qplib_nq_work {
0490     struct work_struct      work;
0491     struct bnxt_qplib_nq    *nq;
0492     struct bnxt_qplib_cq    *cq;
0493 };
0494
0495 void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill);
0496 void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq);
0497 int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
0498                 int msix_vector, bool need_init);
0499 int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
0500              int nq_idx, int msix_vector, int bar_reg_offset,
0501              cqn_handler_t cqn_handler,
0502              srqn_handler_t srq_handler);
0503 int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,
0504               struct bnxt_qplib_srq *srq);
0505 int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res,
0506               struct bnxt_qplib_srq *srq);
0507 int bnxt_qplib_query_srq(struct bnxt_qplib_res *res,
0508              struct bnxt_qplib_srq *srq);
0509 void bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res,
0510                 struct bnxt_qplib_srq *srq);
0511 int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,
0512                  struct bnxt_qplib_swqe *wqe);
0513 int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
0514 int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
0515 int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
0516 int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
0517 int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
0518 void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp);
0519 void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
0520                 struct bnxt_qplib_qp *qp);
0521 void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
0522                 struct bnxt_qplib_sge *sge);
0523 void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,
0524                 struct bnxt_qplib_sge *sge);
0525 u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp);
0526 dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp,
0527                         u32 index);
0528 void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp);
0529 int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
0530              struct bnxt_qplib_swqe *wqe);
0531 void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp);
0532 int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,
0533              struct bnxt_qplib_swqe *wqe);
0534 int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
0535 int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
0536 int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
0537                int num, struct bnxt_qplib_qp **qp);
0538 bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq);
0539 void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type);
0540 void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq);
0541 int bnxt_qplib_alloc_nq(struct bnxt_qplib_res *res, struct bnxt_qplib_nq *nq);
0542 void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp);
0543 void bnxt_qplib_acquire_cq_locks(struct bnxt_qplib_qp *qp,
0544                  unsigned long *flags);
0545 void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp,
0546                  unsigned long *flags);
0547 int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq,
0548                   struct bnxt_qplib_cqe *cqe,
0549                   int num_cqes);
0550 void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp);
0551
0552 static inline void *bnxt_qplib_get_swqe(struct bnxt_qplib_q *que, u32 *swq_idx)
0553 {
0554     u32 idx;
0555
0556     idx = que->swq_start;
0557     if (swq_idx)
0558         *swq_idx = idx;
0559     return &que->swq[idx];
0560 }
0561
0562 static inline void bnxt_qplib_swq_mod_start(struct bnxt_qplib_q *que, u32 idx)
0563 {
0564     que->swq_start = que->swq[idx].next_idx;
0565 }
0566
0567 static inline u32 bnxt_qplib_get_depth(struct bnxt_qplib_q *que)
0568 {
0569     return (que->wqe_size * que->max_wqe) / sizeof(struct sq_sge);
0570 }
0571
0572 static inline u32 bnxt_qplib_set_sq_size(struct bnxt_qplib_q *que, u8 wqe_mode)
0573 {
0574     return (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
0575         que->max_wqe : bnxt_qplib_get_depth(que);
0576 }
0577
0578 static inline u32 bnxt_qplib_set_sq_max_slot(u8 wqe_mode)
0579 {
0580     return (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
0581         sizeof(struct sq_send) / sizeof(struct sq_sge) : 1;
0582 }
0583
0584 static inline u32 bnxt_qplib_set_rq_max_slot(u32 wqe_size)
0585 {
0586     return (wqe_size / sizeof(struct sq_sge));
0587 }
0588
0589 static inline u16 __xlate_qfd(u16 delta, u16 wqe_bytes)
0590 {
0591     /* For Cu/Wh delta = 128, stride = 16, wqe_bytes = 128
0592      * For Gen-p5 B/C mode delta = 0, stride = 16, wqe_bytes = 128.
0593      * For Gen-p5 delta = 0, stride = 16, 32 <= wqe_bytes <= 512.
0594      * when 8916 is disabled.
0595      */
0596     return (delta * wqe_bytes) / sizeof(struct sq_sge);
0597 }
0598
0599 static inline u16 bnxt_qplib_calc_ilsize(struct bnxt_qplib_swqe *wqe, u16 max)
0600 {
0601     u16 size = 0;
0602     int indx;
0603
0604     for (indx = 0; indx < wqe->num_sge; indx++)
0605         size += wqe->sg_list[indx].size;
0606     if (size > max)
0607         size = max;
0608
0609     return size;
0610 }
0611 #endif /* __BNXT_QPLIB_FP_H__ */