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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2016
0004  *
0005  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
0006  *
0007  */
0008 
0009 #include <linux/iio/iio.h>
0010 #include <linux/iio/sysfs.h>
0011 #include <linux/iio/timer/stm32-timer-trigger.h>
0012 #include <linux/iio/trigger.h>
0013 #include <linux/mfd/stm32-timers.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/property.h>
0018 
0019 #define MAX_TRIGGERS 7
0020 #define MAX_VALIDS 5
0021 
0022 /* List the triggers created by each timer */
0023 static const void *triggers_table[][MAX_TRIGGERS] = {
0024     { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
0025     { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
0026     { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
0027     { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
0028     { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
0029     { TIM6_TRGO,},
0030     { TIM7_TRGO,},
0031     { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
0032     { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
0033     { TIM10_OC1,},
0034     { TIM11_OC1,},
0035     { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
0036     { TIM13_OC1,},
0037     { TIM14_OC1,},
0038     { TIM15_TRGO,},
0039     { TIM16_OC1,},
0040     { TIM17_OC1,},
0041 };
0042 
0043 /* List the triggers accepted by each timer */
0044 static const void *valids_table[][MAX_VALIDS] = {
0045     { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
0046     { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
0047     { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
0048     { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
0049     { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
0050     { }, /* timer 6 */
0051     { }, /* timer 7 */
0052     { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
0053     { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
0054     { }, /* timer 10 */
0055     { }, /* timer 11 */
0056     { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
0057 };
0058 
0059 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
0060     { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
0061     { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
0062     { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
0063     { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
0064     { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
0065     { }, /* timer 6 */
0066     { }, /* timer 7 */
0067     { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
0068     { }, /* timer 9 */
0069     { }, /* timer 10 */
0070     { }, /* timer 11 */
0071     { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
0072     { }, /* timer 13 */
0073     { }, /* timer 14 */
0074     { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
0075     { }, /* timer 16 */
0076     { }, /* timer 17 */
0077 };
0078 
0079 struct stm32_timer_trigger_regs {
0080     u32 cr1;
0081     u32 cr2;
0082     u32 psc;
0083     u32 arr;
0084     u32 cnt;
0085     u32 smcr;
0086 };
0087 
0088 struct stm32_timer_trigger {
0089     struct device *dev;
0090     struct regmap *regmap;
0091     struct clk *clk;
0092     bool enabled;
0093     u32 max_arr;
0094     const void *triggers;
0095     const void *valids;
0096     bool has_trgo2;
0097     struct mutex lock; /* concurrent sysfs configuration */
0098     struct list_head tr_list;
0099     struct stm32_timer_trigger_regs bak;
0100 };
0101 
0102 struct stm32_timer_trigger_cfg {
0103     const void *(*valids_table)[MAX_VALIDS];
0104     const unsigned int num_valids_table;
0105 };
0106 
0107 static bool stm32_timer_is_trgo2_name(const char *name)
0108 {
0109     return !!strstr(name, "trgo2");
0110 }
0111 
0112 static bool stm32_timer_is_trgo_name(const char *name)
0113 {
0114     return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
0115 }
0116 
0117 static int stm32_timer_start(struct stm32_timer_trigger *priv,
0118                  struct iio_trigger *trig,
0119                  unsigned int frequency)
0120 {
0121     unsigned long long prd, div;
0122     int prescaler = 0;
0123     u32 ccer;
0124 
0125     /* Period and prescaler values depends of clock rate */
0126     div = (unsigned long long)clk_get_rate(priv->clk);
0127 
0128     do_div(div, frequency);
0129 
0130     prd = div;
0131 
0132     /*
0133      * Increase prescaler value until we get a result that fit
0134      * with auto reload register maximum value.
0135      */
0136     while (div > priv->max_arr) {
0137         prescaler++;
0138         div = prd;
0139         do_div(div, (prescaler + 1));
0140     }
0141     prd = div;
0142 
0143     if (prescaler > MAX_TIM_PSC) {
0144         dev_err(priv->dev, "prescaler exceeds the maximum value\n");
0145         return -EINVAL;
0146     }
0147 
0148     /* Check if nobody else use the timer */
0149     regmap_read(priv->regmap, TIM_CCER, &ccer);
0150     if (ccer & TIM_CCER_CCXE)
0151         return -EBUSY;
0152 
0153     mutex_lock(&priv->lock);
0154     if (!priv->enabled) {
0155         priv->enabled = true;
0156         clk_enable(priv->clk);
0157     }
0158 
0159     regmap_write(priv->regmap, TIM_PSC, prescaler);
0160     regmap_write(priv->regmap, TIM_ARR, prd - 1);
0161     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
0162 
0163     /* Force master mode to update mode */
0164     if (stm32_timer_is_trgo2_name(trig->name))
0165         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
0166                    0x2 << TIM_CR2_MMS2_SHIFT);
0167     else
0168         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
0169                    0x2 << TIM_CR2_MMS_SHIFT);
0170 
0171     /* Make sure that registers are updated */
0172     regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
0173 
0174     /* Enable controller */
0175     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
0176     mutex_unlock(&priv->lock);
0177 
0178     return 0;
0179 }
0180 
0181 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
0182                  struct iio_trigger *trig)
0183 {
0184     u32 ccer;
0185 
0186     regmap_read(priv->regmap, TIM_CCER, &ccer);
0187     if (ccer & TIM_CCER_CCXE)
0188         return;
0189 
0190     mutex_lock(&priv->lock);
0191     /* Stop timer */
0192     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
0193     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0194     regmap_write(priv->regmap, TIM_PSC, 0);
0195     regmap_write(priv->regmap, TIM_ARR, 0);
0196 
0197     /* Force disable master mode */
0198     if (stm32_timer_is_trgo2_name(trig->name))
0199         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
0200     else
0201         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
0202 
0203     /* Make sure that registers are updated */
0204     regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
0205 
0206     if (priv->enabled) {
0207         priv->enabled = false;
0208         clk_disable(priv->clk);
0209     }
0210     mutex_unlock(&priv->lock);
0211 }
0212 
0213 static ssize_t stm32_tt_store_frequency(struct device *dev,
0214                     struct device_attribute *attr,
0215                     const char *buf, size_t len)
0216 {
0217     struct iio_trigger *trig = to_iio_trigger(dev);
0218     struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
0219     unsigned int freq;
0220     int ret;
0221 
0222     ret = kstrtouint(buf, 10, &freq);
0223     if (ret)
0224         return ret;
0225 
0226     if (freq == 0) {
0227         stm32_timer_stop(priv, trig);
0228     } else {
0229         ret = stm32_timer_start(priv, trig, freq);
0230         if (ret)
0231             return ret;
0232     }
0233 
0234     return len;
0235 }
0236 
0237 static ssize_t stm32_tt_read_frequency(struct device *dev,
0238                        struct device_attribute *attr, char *buf)
0239 {
0240     struct iio_trigger *trig = to_iio_trigger(dev);
0241     struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
0242     u32 psc, arr, cr1;
0243     unsigned long long freq = 0;
0244 
0245     regmap_read(priv->regmap, TIM_CR1, &cr1);
0246     regmap_read(priv->regmap, TIM_PSC, &psc);
0247     regmap_read(priv->regmap, TIM_ARR, &arr);
0248 
0249     if (cr1 & TIM_CR1_CEN) {
0250         freq = (unsigned long long)clk_get_rate(priv->clk);
0251         do_div(freq, psc + 1);
0252         do_div(freq, arr + 1);
0253     }
0254 
0255     return sprintf(buf, "%d\n", (unsigned int)freq);
0256 }
0257 
0258 static IIO_DEV_ATTR_SAMP_FREQ(0660,
0259                   stm32_tt_read_frequency,
0260                   stm32_tt_store_frequency);
0261 
0262 #define MASTER_MODE_MAX     7
0263 #define MASTER_MODE2_MAX    15
0264 
0265 static char *master_mode_table[] = {
0266     "reset",
0267     "enable",
0268     "update",
0269     "compare_pulse",
0270     "OC1REF",
0271     "OC2REF",
0272     "OC3REF",
0273     "OC4REF",
0274     /* Master mode selection 2 only */
0275     "OC5REF",
0276     "OC6REF",
0277     "compare_pulse_OC4REF",
0278     "compare_pulse_OC6REF",
0279     "compare_pulse_OC4REF_r_or_OC6REF_r",
0280     "compare_pulse_OC4REF_r_or_OC6REF_f",
0281     "compare_pulse_OC5REF_r_or_OC6REF_r",
0282     "compare_pulse_OC5REF_r_or_OC6REF_f",
0283 };
0284 
0285 static ssize_t stm32_tt_show_master_mode(struct device *dev,
0286                      struct device_attribute *attr,
0287                      char *buf)
0288 {
0289     struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
0290     struct iio_trigger *trig = to_iio_trigger(dev);
0291     u32 cr2;
0292 
0293     regmap_read(priv->regmap, TIM_CR2, &cr2);
0294 
0295     if (stm32_timer_is_trgo2_name(trig->name))
0296         cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
0297     else
0298         cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
0299 
0300     return sysfs_emit(buf, "%s\n", master_mode_table[cr2]);
0301 }
0302 
0303 static ssize_t stm32_tt_store_master_mode(struct device *dev,
0304                       struct device_attribute *attr,
0305                       const char *buf, size_t len)
0306 {
0307     struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
0308     struct iio_trigger *trig = to_iio_trigger(dev);
0309     u32 mask, shift, master_mode_max;
0310     int i;
0311 
0312     if (stm32_timer_is_trgo2_name(trig->name)) {
0313         mask = TIM_CR2_MMS2;
0314         shift = TIM_CR2_MMS2_SHIFT;
0315         master_mode_max = MASTER_MODE2_MAX;
0316     } else {
0317         mask = TIM_CR2_MMS;
0318         shift = TIM_CR2_MMS_SHIFT;
0319         master_mode_max = MASTER_MODE_MAX;
0320     }
0321 
0322     for (i = 0; i <= master_mode_max; i++) {
0323         if (!strncmp(master_mode_table[i], buf,
0324                  strlen(master_mode_table[i]))) {
0325             mutex_lock(&priv->lock);
0326             if (!priv->enabled) {
0327                 /* Clock should be enabled first */
0328                 priv->enabled = true;
0329                 clk_enable(priv->clk);
0330             }
0331             regmap_update_bits(priv->regmap, TIM_CR2, mask,
0332                        i << shift);
0333             mutex_unlock(&priv->lock);
0334             return len;
0335         }
0336     }
0337 
0338     return -EINVAL;
0339 }
0340 
0341 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
0342                            struct device_attribute *attr,
0343                            char *buf)
0344 {
0345     struct iio_trigger *trig = to_iio_trigger(dev);
0346     unsigned int i, master_mode_max;
0347     size_t len = 0;
0348 
0349     if (stm32_timer_is_trgo2_name(trig->name))
0350         master_mode_max = MASTER_MODE2_MAX;
0351     else
0352         master_mode_max = MASTER_MODE_MAX;
0353 
0354     for (i = 0; i <= master_mode_max; i++)
0355         len += scnprintf(buf + len, PAGE_SIZE - len,
0356             "%s ", master_mode_table[i]);
0357 
0358     /* replace trailing space by newline */
0359     buf[len - 1] = '\n';
0360 
0361     return len;
0362 }
0363 
0364 static IIO_DEVICE_ATTR(master_mode_available, 0444,
0365                stm32_tt_show_master_mode_avail, NULL, 0);
0366 
0367 static IIO_DEVICE_ATTR(master_mode, 0660,
0368                stm32_tt_show_master_mode,
0369                stm32_tt_store_master_mode,
0370                0);
0371 
0372 static struct attribute *stm32_trigger_attrs[] = {
0373     &iio_dev_attr_sampling_frequency.dev_attr.attr,
0374     &iio_dev_attr_master_mode.dev_attr.attr,
0375     &iio_dev_attr_master_mode_available.dev_attr.attr,
0376     NULL,
0377 };
0378 
0379 static const struct attribute_group stm32_trigger_attr_group = {
0380     .attrs = stm32_trigger_attrs,
0381 };
0382 
0383 static const struct attribute_group *stm32_trigger_attr_groups[] = {
0384     &stm32_trigger_attr_group,
0385     NULL,
0386 };
0387 
0388 static const struct iio_trigger_ops timer_trigger_ops = {
0389 };
0390 
0391 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv)
0392 {
0393     struct iio_trigger *tr;
0394 
0395     list_for_each_entry(tr, &priv->tr_list, alloc_list)
0396         iio_trigger_unregister(tr);
0397 }
0398 
0399 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv)
0400 {
0401     int ret;
0402     const char * const *cur = priv->triggers;
0403 
0404     INIT_LIST_HEAD(&priv->tr_list);
0405 
0406     while (cur && *cur) {
0407         struct iio_trigger *trig;
0408         bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
0409         bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
0410 
0411         if (cur_is_trgo2 && !priv->has_trgo2) {
0412             cur++;
0413             continue;
0414         }
0415 
0416         trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
0417         if  (!trig)
0418             return -ENOMEM;
0419 
0420         trig->dev.parent = priv->dev->parent;
0421         trig->ops = &timer_trigger_ops;
0422 
0423         /*
0424          * sampling frequency and master mode attributes
0425          * should only be available on trgo/trgo2 triggers
0426          */
0427         if (cur_is_trgo || cur_is_trgo2)
0428             trig->dev.groups = stm32_trigger_attr_groups;
0429 
0430         iio_trigger_set_drvdata(trig, priv);
0431 
0432         ret = iio_trigger_register(trig);
0433         if (ret) {
0434             stm32_unregister_iio_triggers(priv);
0435             return ret;
0436         }
0437 
0438         list_add_tail(&trig->alloc_list, &priv->tr_list);
0439         cur++;
0440     }
0441 
0442     return 0;
0443 }
0444 
0445 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
0446                   struct iio_chan_spec const *chan,
0447                   int *val, int *val2, long mask)
0448 {
0449     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0450     u32 dat;
0451 
0452     switch (mask) {
0453     case IIO_CHAN_INFO_RAW:
0454         regmap_read(priv->regmap, TIM_CNT, &dat);
0455         *val = dat;
0456         return IIO_VAL_INT;
0457 
0458     case IIO_CHAN_INFO_ENABLE:
0459         regmap_read(priv->regmap, TIM_CR1, &dat);
0460         *val = (dat & TIM_CR1_CEN) ? 1 : 0;
0461         return IIO_VAL_INT;
0462 
0463     case IIO_CHAN_INFO_SCALE:
0464         regmap_read(priv->regmap, TIM_SMCR, &dat);
0465         dat &= TIM_SMCR_SMS;
0466 
0467         *val = 1;
0468         *val2 = 0;
0469 
0470         /* in quadrature case scale = 0.25 */
0471         if (dat == 3)
0472             *val2 = 2;
0473 
0474         return IIO_VAL_FRACTIONAL_LOG2;
0475     }
0476 
0477     return -EINVAL;
0478 }
0479 
0480 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
0481                    struct iio_chan_spec const *chan,
0482                    int val, int val2, long mask)
0483 {
0484     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0485 
0486     switch (mask) {
0487     case IIO_CHAN_INFO_RAW:
0488         return regmap_write(priv->regmap, TIM_CNT, val);
0489 
0490     case IIO_CHAN_INFO_SCALE:
0491         /* fixed scale */
0492         return -EINVAL;
0493 
0494     case IIO_CHAN_INFO_ENABLE:
0495         mutex_lock(&priv->lock);
0496         if (val) {
0497             if (!priv->enabled) {
0498                 priv->enabled = true;
0499                 clk_enable(priv->clk);
0500             }
0501             regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
0502                        TIM_CR1_CEN);
0503         } else {
0504             regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
0505                        0);
0506             if (priv->enabled) {
0507                 priv->enabled = false;
0508                 clk_disable(priv->clk);
0509             }
0510         }
0511         mutex_unlock(&priv->lock);
0512         return 0;
0513     }
0514 
0515     return -EINVAL;
0516 }
0517 
0518 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
0519                       struct iio_trigger *trig)
0520 {
0521     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0522     const char * const *cur = priv->valids;
0523     unsigned int i = 0;
0524 
0525     if (!is_stm32_timer_trigger(trig))
0526         return -EINVAL;
0527 
0528     while (cur && *cur) {
0529         if (!strncmp(trig->name, *cur, strlen(trig->name))) {
0530             regmap_update_bits(priv->regmap,
0531                        TIM_SMCR, TIM_SMCR_TS,
0532                        i << TIM_SMCR_TS_SHIFT);
0533             return 0;
0534         }
0535         cur++;
0536         i++;
0537     }
0538 
0539     return -EINVAL;
0540 }
0541 
0542 static const struct iio_info stm32_trigger_info = {
0543     .validate_trigger = stm32_counter_validate_trigger,
0544     .read_raw = stm32_counter_read_raw,
0545     .write_raw = stm32_counter_write_raw
0546 };
0547 
0548 static const char *const stm32_trigger_modes[] = {
0549     "trigger",
0550 };
0551 
0552 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
0553                   const struct iio_chan_spec *chan,
0554                   unsigned int mode)
0555 {
0556     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0557 
0558     regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
0559 
0560     return 0;
0561 }
0562 
0563 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
0564                   const struct iio_chan_spec *chan)
0565 {
0566     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0567     u32 smcr;
0568 
0569     regmap_read(priv->regmap, TIM_SMCR, &smcr);
0570 
0571     return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
0572 }
0573 
0574 static const struct iio_enum stm32_trigger_mode_enum = {
0575     .items = stm32_trigger_modes,
0576     .num_items = ARRAY_SIZE(stm32_trigger_modes),
0577     .set = stm32_set_trigger_mode,
0578     .get = stm32_get_trigger_mode
0579 };
0580 
0581 static const char *const stm32_enable_modes[] = {
0582     "always",
0583     "gated",
0584     "triggered",
0585 };
0586 
0587 static int stm32_enable_mode2sms(int mode)
0588 {
0589     switch (mode) {
0590     case 0:
0591         return 0;
0592     case 1:
0593         return 5;
0594     case 2:
0595         return 6;
0596     }
0597 
0598     return -EINVAL;
0599 }
0600 
0601 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
0602                  const struct iio_chan_spec *chan,
0603                  unsigned int mode)
0604 {
0605     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0606     int sms = stm32_enable_mode2sms(mode);
0607 
0608     if (sms < 0)
0609         return sms;
0610     /*
0611      * Triggered mode sets CEN bit automatically by hardware. So, first
0612      * enable counter clock, so it can use it. Keeps it in sync with CEN.
0613      */
0614     mutex_lock(&priv->lock);
0615     if (sms == 6 && !priv->enabled) {
0616         clk_enable(priv->clk);
0617         priv->enabled = true;
0618     }
0619     mutex_unlock(&priv->lock);
0620 
0621     regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
0622 
0623     return 0;
0624 }
0625 
0626 static int stm32_sms2enable_mode(int mode)
0627 {
0628     switch (mode) {
0629     case 0:
0630         return 0;
0631     case 5:
0632         return 1;
0633     case 6:
0634         return 2;
0635     }
0636 
0637     return -EINVAL;
0638 }
0639 
0640 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
0641                  const struct iio_chan_spec *chan)
0642 {
0643     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0644     u32 smcr;
0645 
0646     regmap_read(priv->regmap, TIM_SMCR, &smcr);
0647     smcr &= TIM_SMCR_SMS;
0648 
0649     return stm32_sms2enable_mode(smcr);
0650 }
0651 
0652 static const struct iio_enum stm32_enable_mode_enum = {
0653     .items = stm32_enable_modes,
0654     .num_items = ARRAY_SIZE(stm32_enable_modes),
0655     .set = stm32_set_enable_mode,
0656     .get = stm32_get_enable_mode
0657 };
0658 
0659 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
0660                       uintptr_t private,
0661                       const struct iio_chan_spec *chan,
0662                       char *buf)
0663 {
0664     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0665     u32 arr;
0666 
0667     regmap_read(priv->regmap, TIM_ARR, &arr);
0668 
0669     return snprintf(buf, PAGE_SIZE, "%u\n", arr);
0670 }
0671 
0672 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
0673                       uintptr_t private,
0674                       const struct iio_chan_spec *chan,
0675                       const char *buf, size_t len)
0676 {
0677     struct stm32_timer_trigger *priv = iio_priv(indio_dev);
0678     unsigned int preset;
0679     int ret;
0680 
0681     ret = kstrtouint(buf, 0, &preset);
0682     if (ret)
0683         return ret;
0684 
0685     /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
0686     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
0687     regmap_write(priv->regmap, TIM_ARR, preset);
0688 
0689     return len;
0690 }
0691 
0692 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
0693     {
0694         .name = "preset",
0695         .shared = IIO_SEPARATE,
0696         .read = stm32_count_get_preset,
0697         .write = stm32_count_set_preset
0698     },
0699     IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
0700     IIO_ENUM_AVAILABLE("enable_mode", IIO_SHARED_BY_TYPE, &stm32_enable_mode_enum),
0701     IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
0702     IIO_ENUM_AVAILABLE("trigger_mode", IIO_SHARED_BY_TYPE, &stm32_trigger_mode_enum),
0703     {}
0704 };
0705 
0706 static const struct iio_chan_spec stm32_trigger_channel = {
0707     .type = IIO_COUNT,
0708     .channel = 0,
0709     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0710                   BIT(IIO_CHAN_INFO_ENABLE) |
0711                   BIT(IIO_CHAN_INFO_SCALE),
0712     .ext_info = stm32_trigger_count_info,
0713     .indexed = 1
0714 };
0715 
0716 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
0717 {
0718     struct iio_dev *indio_dev;
0719     int ret;
0720 
0721     indio_dev = devm_iio_device_alloc(dev,
0722                       sizeof(struct stm32_timer_trigger));
0723     if (!indio_dev)
0724         return NULL;
0725 
0726     indio_dev->name = dev_name(dev);
0727     indio_dev->info = &stm32_trigger_info;
0728     indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
0729     indio_dev->num_channels = 1;
0730     indio_dev->channels = &stm32_trigger_channel;
0731 
0732     ret = devm_iio_device_register(dev, indio_dev);
0733     if (ret)
0734         return NULL;
0735 
0736     return iio_priv(indio_dev);
0737 }
0738 
0739 /**
0740  * is_stm32_timer_trigger
0741  * @trig: trigger to be checked
0742  *
0743  * return true if the trigger is a valid stm32 iio timer trigger
0744  * either return false
0745  */
0746 bool is_stm32_timer_trigger(struct iio_trigger *trig)
0747 {
0748     return (trig->ops == &timer_trigger_ops);
0749 }
0750 EXPORT_SYMBOL(is_stm32_timer_trigger);
0751 
0752 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
0753 {
0754     u32 val;
0755 
0756     /*
0757      * Master mode selection 2 bits can only be written and read back when
0758      * timer supports it.
0759      */
0760     regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
0761     regmap_read(priv->regmap, TIM_CR2, &val);
0762     regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
0763     priv->has_trgo2 = !!val;
0764 }
0765 
0766 static int stm32_timer_trigger_probe(struct platform_device *pdev)
0767 {
0768     struct device *dev = &pdev->dev;
0769     struct stm32_timer_trigger *priv;
0770     struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
0771     const struct stm32_timer_trigger_cfg *cfg;
0772     unsigned int index;
0773     int ret;
0774 
0775     ret = device_property_read_u32(dev, "reg", &index);
0776     if (ret)
0777         return ret;
0778 
0779     cfg = device_get_match_data(dev);
0780 
0781     if (index >= ARRAY_SIZE(triggers_table) ||
0782         index >= cfg->num_valids_table)
0783         return -EINVAL;
0784 
0785     /* Create an IIO device only if we have triggers to be validated */
0786     if (*cfg->valids_table[index])
0787         priv = stm32_setup_counter_device(dev);
0788     else
0789         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0790 
0791     if (!priv)
0792         return -ENOMEM;
0793 
0794     priv->dev = dev;
0795     priv->regmap = ddata->regmap;
0796     priv->clk = ddata->clk;
0797     priv->max_arr = ddata->max_arr;
0798     priv->triggers = triggers_table[index];
0799     priv->valids = cfg->valids_table[index];
0800     stm32_timer_detect_trgo2(priv);
0801     mutex_init(&priv->lock);
0802 
0803     ret = stm32_register_iio_triggers(priv);
0804     if (ret)
0805         return ret;
0806 
0807     platform_set_drvdata(pdev, priv);
0808 
0809     return 0;
0810 }
0811 
0812 static int stm32_timer_trigger_remove(struct platform_device *pdev)
0813 {
0814     struct stm32_timer_trigger *priv = platform_get_drvdata(pdev);
0815     u32 val;
0816 
0817     /* Unregister triggers before everything can be safely turned off */
0818     stm32_unregister_iio_triggers(priv);
0819 
0820     /* Check if nobody else use the timer, then disable it */
0821     regmap_read(priv->regmap, TIM_CCER, &val);
0822     if (!(val & TIM_CCER_CCXE))
0823         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0824 
0825     if (priv->enabled)
0826         clk_disable(priv->clk);
0827 
0828     return 0;
0829 }
0830 
0831 static int stm32_timer_trigger_suspend(struct device *dev)
0832 {
0833     struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
0834 
0835     /* Only take care of enabled timer: don't disturb other MFD child */
0836     if (priv->enabled) {
0837         /* Backup registers that may get lost in low power mode */
0838         regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
0839         regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);
0840         regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);
0841         regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
0842         regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
0843         regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
0844 
0845         /* Disable the timer */
0846         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0847         clk_disable(priv->clk);
0848     }
0849 
0850     return 0;
0851 }
0852 
0853 static int stm32_timer_trigger_resume(struct device *dev)
0854 {
0855     struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
0856     int ret;
0857 
0858     if (priv->enabled) {
0859         ret = clk_enable(priv->clk);
0860         if (ret)
0861             return ret;
0862 
0863         /* restore master/slave modes */
0864         regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
0865         regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);
0866 
0867         /* restore sampling_frequency (trgo / trgo2 triggers) */
0868         regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);
0869         regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
0870         regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
0871 
0872         /* Also re-enables the timer */
0873         regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
0874     }
0875 
0876     return 0;
0877 }
0878 
0879 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops,
0880                 stm32_timer_trigger_suspend,
0881                 stm32_timer_trigger_resume);
0882 
0883 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
0884     .valids_table = valids_table,
0885     .num_valids_table = ARRAY_SIZE(valids_table),
0886 };
0887 
0888 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
0889     .valids_table = stm32h7_valids_table,
0890     .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
0891 };
0892 
0893 static const struct of_device_id stm32_trig_of_match[] = {
0894     {
0895         .compatible = "st,stm32-timer-trigger",
0896         .data = (void *)&stm32_timer_trg_cfg,
0897     }, {
0898         .compatible = "st,stm32h7-timer-trigger",
0899         .data = (void *)&stm32h7_timer_trg_cfg,
0900     },
0901     { /* end node */ },
0902 };
0903 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
0904 
0905 static struct platform_driver stm32_timer_trigger_driver = {
0906     .probe = stm32_timer_trigger_probe,
0907     .remove = stm32_timer_trigger_remove,
0908     .driver = {
0909         .name = "stm32-timer-trigger",
0910         .of_match_table = stm32_trig_of_match,
0911         .pm = pm_sleep_ptr(&stm32_timer_trigger_pm_ops),
0912     },
0913 };
0914 module_platform_driver(stm32_timer_trigger_driver);
0915 
0916 MODULE_ALIAS("platform:stm32-timer-trigger");
0917 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
0918 MODULE_LICENSE("GPL v2");
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