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0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/i2c.h>
0015 #include <linux/regmap.h>
0016 #include <linux/delay.h>
0017 #include <linux/acpi.h>
0018
0019 #include <linux/iio/iio.h>
0020 #include <linux/iio/buffer.h>
0021 #include <linux/iio/trigger.h>
0022 #include <linux/iio/trigger_consumer.h>
0023 #include <linux/iio/triggered_buffer.h>
0024 #include <linux/iio/sysfs.h>
0025 #include <linux/pm_runtime.h>
0026
0027 #define RPR0521_REG_SYSTEM_CTRL 0x40
0028 #define RPR0521_REG_MODE_CTRL 0x41
0029 #define RPR0521_REG_ALS_CTRL 0x42
0030 #define RPR0521_REG_PXS_CTRL 0x43
0031 #define RPR0521_REG_PXS_DATA 0x44
0032 #define RPR0521_REG_ALS_DATA0 0x46
0033 #define RPR0521_REG_ALS_DATA1 0x48
0034 #define RPR0521_REG_INTERRUPT 0x4A
0035 #define RPR0521_REG_PS_OFFSET_LSB 0x53
0036 #define RPR0521_REG_ID 0x92
0037
0038 #define RPR0521_MODE_ALS_MASK BIT(7)
0039 #define RPR0521_MODE_PXS_MASK BIT(6)
0040 #define RPR0521_MODE_MEAS_TIME_MASK GENMASK(3, 0)
0041 #define RPR0521_ALS_DATA0_GAIN_MASK GENMASK(5, 4)
0042 #define RPR0521_ALS_DATA0_GAIN_SHIFT 4
0043 #define RPR0521_ALS_DATA1_GAIN_MASK GENMASK(3, 2)
0044 #define RPR0521_ALS_DATA1_GAIN_SHIFT 2
0045 #define RPR0521_PXS_GAIN_MASK GENMASK(5, 4)
0046 #define RPR0521_PXS_GAIN_SHIFT 4
0047 #define RPR0521_PXS_PERSISTENCE_MASK GENMASK(3, 0)
0048 #define RPR0521_INTERRUPT_INT_TRIG_PS_MASK BIT(0)
0049 #define RPR0521_INTERRUPT_INT_TRIG_ALS_MASK BIT(1)
0050 #define RPR0521_INTERRUPT_INT_REASSERT_MASK BIT(3)
0051 #define RPR0521_INTERRUPT_ALS_INT_STATUS_MASK BIT(6)
0052 #define RPR0521_INTERRUPT_PS_INT_STATUS_MASK BIT(7)
0053
0054 #define RPR0521_MODE_ALS_ENABLE BIT(7)
0055 #define RPR0521_MODE_ALS_DISABLE 0x00
0056 #define RPR0521_MODE_PXS_ENABLE BIT(6)
0057 #define RPR0521_MODE_PXS_DISABLE 0x00
0058 #define RPR0521_PXS_PERSISTENCE_DRDY 0x00
0059
0060 #define RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE BIT(0)
0061 #define RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE 0x00
0062 #define RPR0521_INTERRUPT_INT_TRIG_ALS_ENABLE BIT(1)
0063 #define RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE 0x00
0064 #define RPR0521_INTERRUPT_INT_REASSERT_ENABLE BIT(3)
0065 #define RPR0521_INTERRUPT_INT_REASSERT_DISABLE 0x00
0066
0067 #define RPR0521_MANUFACT_ID 0xE0
0068 #define RPR0521_DEFAULT_MEAS_TIME 0x06
0069
0070 #define RPR0521_DRV_NAME "RPR0521"
0071 #define RPR0521_IRQ_NAME "rpr0521_event"
0072 #define RPR0521_REGMAP_NAME "rpr0521_regmap"
0073
0074 #define RPR0521_SLEEP_DELAY_MS 2000
0075
0076 #define RPR0521_ALS_SCALE_AVAIL "0.007812 0.015625 0.5 1"
0077 #define RPR0521_PXS_SCALE_AVAIL "0.125 0.5 1"
0078
0079 struct rpr0521_gain {
0080 int scale;
0081 int uscale;
0082 };
0083
0084 static const struct rpr0521_gain rpr0521_als_gain[4] = {
0085 {1, 0},
0086 {0, 500000},
0087 {0, 15625},
0088 {0, 7812},
0089 };
0090
0091 static const struct rpr0521_gain rpr0521_pxs_gain[3] = {
0092 {1, 0},
0093 {0, 500000},
0094 {0, 125000},
0095 };
0096
0097 enum rpr0521_channel {
0098 RPR0521_CHAN_PXS,
0099 RPR0521_CHAN_ALS_DATA0,
0100 RPR0521_CHAN_ALS_DATA1,
0101 };
0102
0103 struct rpr0521_reg_desc {
0104 u8 address;
0105 u8 device_mask;
0106 };
0107
0108 static const struct rpr0521_reg_desc rpr0521_data_reg[] = {
0109 [RPR0521_CHAN_PXS] = {
0110 .address = RPR0521_REG_PXS_DATA,
0111 .device_mask = RPR0521_MODE_PXS_MASK,
0112 },
0113 [RPR0521_CHAN_ALS_DATA0] = {
0114 .address = RPR0521_REG_ALS_DATA0,
0115 .device_mask = RPR0521_MODE_ALS_MASK,
0116 },
0117 [RPR0521_CHAN_ALS_DATA1] = {
0118 .address = RPR0521_REG_ALS_DATA1,
0119 .device_mask = RPR0521_MODE_ALS_MASK,
0120 },
0121 };
0122
0123 static const struct rpr0521_gain_info {
0124 u8 reg;
0125 u8 mask;
0126 u8 shift;
0127 const struct rpr0521_gain *gain;
0128 int size;
0129 } rpr0521_gain[] = {
0130 [RPR0521_CHAN_PXS] = {
0131 .reg = RPR0521_REG_PXS_CTRL,
0132 .mask = RPR0521_PXS_GAIN_MASK,
0133 .shift = RPR0521_PXS_GAIN_SHIFT,
0134 .gain = rpr0521_pxs_gain,
0135 .size = ARRAY_SIZE(rpr0521_pxs_gain),
0136 },
0137 [RPR0521_CHAN_ALS_DATA0] = {
0138 .reg = RPR0521_REG_ALS_CTRL,
0139 .mask = RPR0521_ALS_DATA0_GAIN_MASK,
0140 .shift = RPR0521_ALS_DATA0_GAIN_SHIFT,
0141 .gain = rpr0521_als_gain,
0142 .size = ARRAY_SIZE(rpr0521_als_gain),
0143 },
0144 [RPR0521_CHAN_ALS_DATA1] = {
0145 .reg = RPR0521_REG_ALS_CTRL,
0146 .mask = RPR0521_ALS_DATA1_GAIN_MASK,
0147 .shift = RPR0521_ALS_DATA1_GAIN_SHIFT,
0148 .gain = rpr0521_als_gain,
0149 .size = ARRAY_SIZE(rpr0521_als_gain),
0150 },
0151 };
0152
0153 struct rpr0521_samp_freq {
0154 int als_hz;
0155 int als_uhz;
0156 int pxs_hz;
0157 int pxs_uhz;
0158 };
0159
0160 static const struct rpr0521_samp_freq rpr0521_samp_freq_i[13] = {
0161
0162 {0, 0, 0, 0},
0163 {0, 0, 100, 0},
0164 {0, 0, 25, 0},
0165 {0, 0, 10, 0},
0166 {0, 0, 2, 500000},
0167 {10, 0, 20, 0},
0168 {10, 0, 10, 0},
0169 {10, 0, 2, 500000},
0170 {2, 500000, 20, 0},
0171 {2, 500000, 10, 0},
0172 {2, 500000, 0, 0},
0173 {2, 500000, 2, 500000},
0174 {20, 0, 20, 0}
0175 };
0176
0177 struct rpr0521_data {
0178 struct i2c_client *client;
0179
0180
0181 struct mutex lock;
0182
0183
0184 bool als_dev_en;
0185 bool pxs_dev_en;
0186
0187 struct iio_trigger *drdy_trigger0;
0188 s64 irq_timestamp;
0189
0190
0191 bool als_ps_need_en;
0192 bool pxs_ps_need_en;
0193 bool als_need_dis;
0194 bool pxs_need_dis;
0195
0196 struct regmap *regmap;
0197
0198
0199
0200
0201
0202
0203 struct {
0204 __le16 channels[3];
0205 u8 garbage;
0206 s64 ts __aligned(8);
0207 } scan;
0208 };
0209
0210 static IIO_CONST_ATTR(in_intensity_scale_available, RPR0521_ALS_SCALE_AVAIL);
0211 static IIO_CONST_ATTR(in_proximity_scale_available, RPR0521_PXS_SCALE_AVAIL);
0212
0213
0214
0215
0216
0217 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("2.5 10");
0218
0219 static struct attribute *rpr0521_attributes[] = {
0220 &iio_const_attr_in_intensity_scale_available.dev_attr.attr,
0221 &iio_const_attr_in_proximity_scale_available.dev_attr.attr,
0222 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
0223 NULL,
0224 };
0225
0226 static const struct attribute_group rpr0521_attribute_group = {
0227 .attrs = rpr0521_attributes,
0228 };
0229
0230
0231 enum rpr0521_scan_index_order {
0232 RPR0521_CHAN_INDEX_PXS,
0233 RPR0521_CHAN_INDEX_BOTH,
0234 RPR0521_CHAN_INDEX_IR,
0235 };
0236
0237 static const unsigned long rpr0521_available_scan_masks[] = {
0238 BIT(RPR0521_CHAN_INDEX_PXS) | BIT(RPR0521_CHAN_INDEX_BOTH) |
0239 BIT(RPR0521_CHAN_INDEX_IR),
0240 0
0241 };
0242
0243 static const struct iio_chan_spec rpr0521_channels[] = {
0244 {
0245 .type = IIO_PROXIMITY,
0246 .address = RPR0521_CHAN_PXS,
0247 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0248 BIT(IIO_CHAN_INFO_OFFSET) |
0249 BIT(IIO_CHAN_INFO_SCALE),
0250 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0251 .scan_index = RPR0521_CHAN_INDEX_PXS,
0252 .scan_type = {
0253 .sign = 'u',
0254 .realbits = 16,
0255 .storagebits = 16,
0256 .endianness = IIO_LE,
0257 },
0258 },
0259 {
0260 .type = IIO_INTENSITY,
0261 .modified = 1,
0262 .address = RPR0521_CHAN_ALS_DATA0,
0263 .channel2 = IIO_MOD_LIGHT_BOTH,
0264 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0265 BIT(IIO_CHAN_INFO_SCALE),
0266 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0267 .scan_index = RPR0521_CHAN_INDEX_BOTH,
0268 .scan_type = {
0269 .sign = 'u',
0270 .realbits = 16,
0271 .storagebits = 16,
0272 .endianness = IIO_LE,
0273 },
0274 },
0275 {
0276 .type = IIO_INTENSITY,
0277 .modified = 1,
0278 .address = RPR0521_CHAN_ALS_DATA1,
0279 .channel2 = IIO_MOD_LIGHT_IR,
0280 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0281 BIT(IIO_CHAN_INFO_SCALE),
0282 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0283 .scan_index = RPR0521_CHAN_INDEX_IR,
0284 .scan_type = {
0285 .sign = 'u',
0286 .realbits = 16,
0287 .storagebits = 16,
0288 .endianness = IIO_LE,
0289 },
0290 },
0291 };
0292
0293 static int rpr0521_als_enable(struct rpr0521_data *data, u8 status)
0294 {
0295 int ret;
0296
0297 ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
0298 RPR0521_MODE_ALS_MASK,
0299 status);
0300 if (ret < 0)
0301 return ret;
0302
0303 if (status & RPR0521_MODE_ALS_MASK)
0304 data->als_dev_en = true;
0305 else
0306 data->als_dev_en = false;
0307
0308 return 0;
0309 }
0310
0311 static int rpr0521_pxs_enable(struct rpr0521_data *data, u8 status)
0312 {
0313 int ret;
0314
0315 ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
0316 RPR0521_MODE_PXS_MASK,
0317 status);
0318 if (ret < 0)
0319 return ret;
0320
0321 if (status & RPR0521_MODE_PXS_MASK)
0322 data->pxs_dev_en = true;
0323 else
0324 data->pxs_dev_en = false;
0325
0326 return 0;
0327 }
0328
0329
0330
0331
0332
0333
0334
0335
0336
0337
0338
0339 static int rpr0521_set_power_state(struct rpr0521_data *data, bool on,
0340 u8 device_mask)
0341 {
0342 #ifdef CONFIG_PM
0343 int ret;
0344
0345 if (device_mask & RPR0521_MODE_ALS_MASK) {
0346 data->als_ps_need_en = on;
0347 data->als_need_dis = !on;
0348 }
0349
0350 if (device_mask & RPR0521_MODE_PXS_MASK) {
0351 data->pxs_ps_need_en = on;
0352 data->pxs_need_dis = !on;
0353 }
0354
0355
0356
0357
0358
0359
0360
0361
0362 if (on) {
0363 ret = pm_runtime_resume_and_get(&data->client->dev);
0364 } else {
0365 pm_runtime_mark_last_busy(&data->client->dev);
0366 ret = pm_runtime_put_autosuspend(&data->client->dev);
0367 }
0368 if (ret < 0) {
0369 dev_err(&data->client->dev,
0370 "Failed: rpr0521_set_power_state for %d, ret %d\n",
0371 on, ret);
0372 return ret;
0373 }
0374
0375 if (on) {
0376
0377 if (data->als_ps_need_en) {
0378 ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
0379 if (ret)
0380 return ret;
0381 data->als_ps_need_en = false;
0382 }
0383
0384 if (data->pxs_ps_need_en) {
0385 ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
0386 if (ret)
0387 return ret;
0388 data->pxs_ps_need_en = false;
0389 }
0390 }
0391 #endif
0392 return 0;
0393 }
0394
0395
0396 static inline bool rpr0521_is_triggered(struct rpr0521_data *data)
0397 {
0398 int ret;
0399 int reg;
0400
0401 ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, ®);
0402 if (ret < 0)
0403 return false;
0404 if (reg &
0405 (RPR0521_INTERRUPT_ALS_INT_STATUS_MASK |
0406 RPR0521_INTERRUPT_PS_INT_STATUS_MASK))
0407 return true;
0408 else
0409 return false;
0410 }
0411
0412
0413 static irqreturn_t rpr0521_drdy_irq_handler(int irq, void *private)
0414 {
0415 struct iio_dev *indio_dev = private;
0416 struct rpr0521_data *data = iio_priv(indio_dev);
0417
0418 data->irq_timestamp = iio_get_time_ns(indio_dev);
0419
0420
0421
0422
0423
0424
0425 return IRQ_WAKE_THREAD;
0426 }
0427
0428 static irqreturn_t rpr0521_drdy_irq_thread(int irq, void *private)
0429 {
0430 struct iio_dev *indio_dev = private;
0431 struct rpr0521_data *data = iio_priv(indio_dev);
0432
0433 if (rpr0521_is_triggered(data)) {
0434 iio_trigger_poll_chained(data->drdy_trigger0);
0435 return IRQ_HANDLED;
0436 }
0437
0438 return IRQ_NONE;
0439 }
0440
0441 static irqreturn_t rpr0521_trigger_consumer_store_time(int irq, void *p)
0442 {
0443 struct iio_poll_func *pf = p;
0444 struct iio_dev *indio_dev = pf->indio_dev;
0445
0446
0447 if (!iio_trigger_using_own(indio_dev))
0448 pf->timestamp = iio_get_time_ns(indio_dev);
0449
0450 return IRQ_WAKE_THREAD;
0451 }
0452
0453 static irqreturn_t rpr0521_trigger_consumer_handler(int irq, void *p)
0454 {
0455 struct iio_poll_func *pf = p;
0456 struct iio_dev *indio_dev = pf->indio_dev;
0457 struct rpr0521_data *data = iio_priv(indio_dev);
0458 int err;
0459
0460
0461 if (iio_trigger_using_own(indio_dev) && data->irq_timestamp) {
0462 pf->timestamp = data->irq_timestamp;
0463 data->irq_timestamp = 0;
0464 }
0465
0466 if (!pf->timestamp)
0467 pf->timestamp = iio_get_time_ns(indio_dev);
0468
0469 err = regmap_bulk_read(data->regmap, RPR0521_REG_PXS_DATA,
0470 data->scan.channels,
0471 (3 * 2) + 1);
0472 if (!err)
0473 iio_push_to_buffers_with_timestamp(indio_dev,
0474 &data->scan, pf->timestamp);
0475 else
0476 dev_err(&data->client->dev,
0477 "Trigger consumer can't read from sensor.\n");
0478 pf->timestamp = 0;
0479
0480 iio_trigger_notify_done(indio_dev->trig);
0481
0482 return IRQ_HANDLED;
0483 }
0484
0485 static int rpr0521_write_int_enable(struct rpr0521_data *data)
0486 {
0487 int err;
0488
0489
0490 err = regmap_update_bits(data->regmap, RPR0521_REG_PXS_CTRL,
0491 RPR0521_PXS_PERSISTENCE_MASK,
0492 RPR0521_PXS_PERSISTENCE_DRDY);
0493 if (err) {
0494 dev_err(&data->client->dev, "PS control reg write fail.\n");
0495 return -EBUSY;
0496 }
0497
0498
0499 err = regmap_write(data->regmap, RPR0521_REG_INTERRUPT,
0500 RPR0521_INTERRUPT_INT_REASSERT_DISABLE |
0501 RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE |
0502 RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE
0503 );
0504 if (err) {
0505 dev_err(&data->client->dev, "Interrupt setup write fail.\n");
0506 return -EBUSY;
0507 }
0508
0509 return 0;
0510 }
0511
0512 static int rpr0521_write_int_disable(struct rpr0521_data *data)
0513 {
0514
0515 return regmap_write(data->regmap, RPR0521_REG_INTERRUPT,
0516 RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE |
0517 RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE
0518 );
0519 }
0520
0521
0522
0523
0524
0525 static int rpr0521_pxs_drdy_set_state(struct iio_trigger *trigger,
0526 bool enable_drdy)
0527 {
0528 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trigger);
0529 struct rpr0521_data *data = iio_priv(indio_dev);
0530 int err;
0531
0532 if (enable_drdy)
0533 err = rpr0521_write_int_enable(data);
0534 else
0535 err = rpr0521_write_int_disable(data);
0536 if (err)
0537 dev_err(&data->client->dev, "rpr0521_pxs_drdy_set_state failed\n");
0538
0539 return err;
0540 }
0541
0542 static const struct iio_trigger_ops rpr0521_trigger_ops = {
0543 .set_trigger_state = rpr0521_pxs_drdy_set_state,
0544 };
0545
0546
0547 static int rpr0521_buffer_preenable(struct iio_dev *indio_dev)
0548 {
0549 int err;
0550 struct rpr0521_data *data = iio_priv(indio_dev);
0551
0552 mutex_lock(&data->lock);
0553 err = rpr0521_set_power_state(data, true,
0554 (RPR0521_MODE_PXS_MASK | RPR0521_MODE_ALS_MASK));
0555 mutex_unlock(&data->lock);
0556 if (err)
0557 dev_err(&data->client->dev, "_buffer_preenable fail\n");
0558
0559 return err;
0560 }
0561
0562 static int rpr0521_buffer_postdisable(struct iio_dev *indio_dev)
0563 {
0564 int err;
0565 struct rpr0521_data *data = iio_priv(indio_dev);
0566
0567 mutex_lock(&data->lock);
0568 err = rpr0521_set_power_state(data, false,
0569 (RPR0521_MODE_PXS_MASK | RPR0521_MODE_ALS_MASK));
0570 mutex_unlock(&data->lock);
0571 if (err)
0572 dev_err(&data->client->dev, "_buffer_postdisable fail\n");
0573
0574 return err;
0575 }
0576
0577 static const struct iio_buffer_setup_ops rpr0521_buffer_setup_ops = {
0578 .preenable = rpr0521_buffer_preenable,
0579 .postdisable = rpr0521_buffer_postdisable,
0580 };
0581
0582 static int rpr0521_get_gain(struct rpr0521_data *data, int chan,
0583 int *val, int *val2)
0584 {
0585 int ret, reg, idx;
0586
0587 ret = regmap_read(data->regmap, rpr0521_gain[chan].reg, ®);
0588 if (ret < 0)
0589 return ret;
0590
0591 idx = (rpr0521_gain[chan].mask & reg) >> rpr0521_gain[chan].shift;
0592 *val = rpr0521_gain[chan].gain[idx].scale;
0593 *val2 = rpr0521_gain[chan].gain[idx].uscale;
0594
0595 return 0;
0596 }
0597
0598 static int rpr0521_set_gain(struct rpr0521_data *data, int chan,
0599 int val, int val2)
0600 {
0601 int i, idx = -EINVAL;
0602
0603
0604 for (i = 0; i < rpr0521_gain[chan].size; i++)
0605 if (val == rpr0521_gain[chan].gain[i].scale &&
0606 val2 == rpr0521_gain[chan].gain[i].uscale) {
0607 idx = i;
0608 break;
0609 }
0610
0611 if (idx < 0)
0612 return idx;
0613
0614 return regmap_update_bits(data->regmap, rpr0521_gain[chan].reg,
0615 rpr0521_gain[chan].mask,
0616 idx << rpr0521_gain[chan].shift);
0617 }
0618
0619 static int rpr0521_read_samp_freq(struct rpr0521_data *data,
0620 enum iio_chan_type chan_type,
0621 int *val, int *val2)
0622 {
0623 int reg, ret;
0624
0625 ret = regmap_read(data->regmap, RPR0521_REG_MODE_CTRL, ®);
0626 if (ret < 0)
0627 return ret;
0628
0629 reg &= RPR0521_MODE_MEAS_TIME_MASK;
0630 if (reg >= ARRAY_SIZE(rpr0521_samp_freq_i))
0631 return -EINVAL;
0632
0633 switch (chan_type) {
0634 case IIO_INTENSITY:
0635 *val = rpr0521_samp_freq_i[reg].als_hz;
0636 *val2 = rpr0521_samp_freq_i[reg].als_uhz;
0637 return 0;
0638
0639 case IIO_PROXIMITY:
0640 *val = rpr0521_samp_freq_i[reg].pxs_hz;
0641 *val2 = rpr0521_samp_freq_i[reg].pxs_uhz;
0642 return 0;
0643
0644 default:
0645 return -EINVAL;
0646 }
0647 }
0648
0649 static int rpr0521_write_samp_freq_common(struct rpr0521_data *data,
0650 enum iio_chan_type chan_type,
0651 int val, int val2)
0652 {
0653 int i;
0654
0655
0656
0657
0658
0659 switch (val) {
0660 case 0:
0661 i = 0;
0662 break;
0663
0664 case 2:
0665 if (val2 != 500000)
0666 return -EINVAL;
0667
0668 i = 11;
0669 break;
0670
0671 case 10:
0672 i = 6;
0673 break;
0674
0675 default:
0676 return -EINVAL;
0677 }
0678
0679 return regmap_update_bits(data->regmap,
0680 RPR0521_REG_MODE_CTRL,
0681 RPR0521_MODE_MEAS_TIME_MASK,
0682 i);
0683 }
0684
0685 static int rpr0521_read_ps_offset(struct rpr0521_data *data, int *offset)
0686 {
0687 int ret;
0688 __le16 buffer;
0689
0690 ret = regmap_bulk_read(data->regmap,
0691 RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer));
0692
0693 if (ret < 0) {
0694 dev_err(&data->client->dev, "Failed to read PS OFFSET register\n");
0695 return ret;
0696 }
0697 *offset = le16_to_cpu(buffer);
0698
0699 return ret;
0700 }
0701
0702 static int rpr0521_write_ps_offset(struct rpr0521_data *data, int offset)
0703 {
0704 int ret;
0705 __le16 buffer;
0706
0707 buffer = cpu_to_le16(offset & 0x3ff);
0708 ret = regmap_raw_write(data->regmap,
0709 RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer));
0710
0711 if (ret < 0) {
0712 dev_err(&data->client->dev, "Failed to write PS OFFSET register\n");
0713 return ret;
0714 }
0715
0716 return ret;
0717 }
0718
0719 static int rpr0521_read_raw(struct iio_dev *indio_dev,
0720 struct iio_chan_spec const *chan, int *val,
0721 int *val2, long mask)
0722 {
0723 struct rpr0521_data *data = iio_priv(indio_dev);
0724 int ret;
0725 int busy;
0726 u8 device_mask;
0727 __le16 raw_data;
0728
0729 switch (mask) {
0730 case IIO_CHAN_INFO_RAW:
0731 if (chan->type != IIO_INTENSITY && chan->type != IIO_PROXIMITY)
0732 return -EINVAL;
0733
0734 busy = iio_device_claim_direct_mode(indio_dev);
0735 if (busy)
0736 return -EBUSY;
0737
0738 device_mask = rpr0521_data_reg[chan->address].device_mask;
0739
0740 mutex_lock(&data->lock);
0741 ret = rpr0521_set_power_state(data, true, device_mask);
0742 if (ret < 0)
0743 goto rpr0521_read_raw_out;
0744
0745 ret = regmap_bulk_read(data->regmap,
0746 rpr0521_data_reg[chan->address].address,
0747 &raw_data, sizeof(raw_data));
0748 if (ret < 0) {
0749 rpr0521_set_power_state(data, false, device_mask);
0750 goto rpr0521_read_raw_out;
0751 }
0752
0753 ret = rpr0521_set_power_state(data, false, device_mask);
0754
0755 rpr0521_read_raw_out:
0756 mutex_unlock(&data->lock);
0757 iio_device_release_direct_mode(indio_dev);
0758 if (ret < 0)
0759 return ret;
0760
0761 *val = le16_to_cpu(raw_data);
0762
0763 return IIO_VAL_INT;
0764
0765 case IIO_CHAN_INFO_SCALE:
0766 mutex_lock(&data->lock);
0767 ret = rpr0521_get_gain(data, chan->address, val, val2);
0768 mutex_unlock(&data->lock);
0769 if (ret < 0)
0770 return ret;
0771
0772 return IIO_VAL_INT_PLUS_MICRO;
0773
0774 case IIO_CHAN_INFO_SAMP_FREQ:
0775 mutex_lock(&data->lock);
0776 ret = rpr0521_read_samp_freq(data, chan->type, val, val2);
0777 mutex_unlock(&data->lock);
0778 if (ret < 0)
0779 return ret;
0780
0781 return IIO_VAL_INT_PLUS_MICRO;
0782
0783 case IIO_CHAN_INFO_OFFSET:
0784 mutex_lock(&data->lock);
0785 ret = rpr0521_read_ps_offset(data, val);
0786 mutex_unlock(&data->lock);
0787 if (ret < 0)
0788 return ret;
0789
0790 return IIO_VAL_INT;
0791
0792 default:
0793 return -EINVAL;
0794 }
0795 }
0796
0797 static int rpr0521_write_raw(struct iio_dev *indio_dev,
0798 struct iio_chan_spec const *chan, int val,
0799 int val2, long mask)
0800 {
0801 struct rpr0521_data *data = iio_priv(indio_dev);
0802 int ret;
0803
0804 switch (mask) {
0805 case IIO_CHAN_INFO_SCALE:
0806 mutex_lock(&data->lock);
0807 ret = rpr0521_set_gain(data, chan->address, val, val2);
0808 mutex_unlock(&data->lock);
0809
0810 return ret;
0811
0812 case IIO_CHAN_INFO_SAMP_FREQ:
0813 mutex_lock(&data->lock);
0814 ret = rpr0521_write_samp_freq_common(data, chan->type,
0815 val, val2);
0816 mutex_unlock(&data->lock);
0817
0818 return ret;
0819
0820 case IIO_CHAN_INFO_OFFSET:
0821 mutex_lock(&data->lock);
0822 ret = rpr0521_write_ps_offset(data, val);
0823 mutex_unlock(&data->lock);
0824
0825 return ret;
0826
0827 default:
0828 return -EINVAL;
0829 }
0830 }
0831
0832 static const struct iio_info rpr0521_info = {
0833 .read_raw = rpr0521_read_raw,
0834 .write_raw = rpr0521_write_raw,
0835 .attrs = &rpr0521_attribute_group,
0836 };
0837
0838 static int rpr0521_init(struct rpr0521_data *data)
0839 {
0840 int ret;
0841 int id;
0842
0843 ret = regmap_read(data->regmap, RPR0521_REG_ID, &id);
0844 if (ret < 0) {
0845 dev_err(&data->client->dev, "Failed to read REG_ID register\n");
0846 return ret;
0847 }
0848
0849 if (id != RPR0521_MANUFACT_ID) {
0850 dev_err(&data->client->dev, "Wrong id, got %x, expected %x\n",
0851 id, RPR0521_MANUFACT_ID);
0852 return -ENODEV;
0853 }
0854
0855
0856 ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
0857 RPR0521_MODE_MEAS_TIME_MASK,
0858 RPR0521_DEFAULT_MEAS_TIME);
0859 if (ret) {
0860 pr_err("regmap_update_bits returned %d\n", ret);
0861 return ret;
0862 }
0863
0864 #ifndef CONFIG_PM
0865 ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
0866 if (ret < 0)
0867 return ret;
0868 ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
0869 if (ret < 0)
0870 return ret;
0871 #endif
0872
0873 data->irq_timestamp = 0;
0874
0875 return 0;
0876 }
0877
0878 static int rpr0521_poweroff(struct rpr0521_data *data)
0879 {
0880 int ret;
0881 int tmp;
0882
0883 ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
0884 RPR0521_MODE_ALS_MASK |
0885 RPR0521_MODE_PXS_MASK,
0886 RPR0521_MODE_ALS_DISABLE |
0887 RPR0521_MODE_PXS_DISABLE);
0888 if (ret < 0)
0889 return ret;
0890
0891 data->als_dev_en = false;
0892 data->pxs_dev_en = false;
0893
0894
0895
0896
0897
0898 ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, &tmp);
0899 if (ret) {
0900 dev_err(&data->client->dev, "Failed to reset int pin.\n");
0901 return ret;
0902 }
0903
0904 return 0;
0905 }
0906
0907 static bool rpr0521_is_volatile_reg(struct device *dev, unsigned int reg)
0908 {
0909 switch (reg) {
0910 case RPR0521_REG_MODE_CTRL:
0911 case RPR0521_REG_ALS_CTRL:
0912 case RPR0521_REG_PXS_CTRL:
0913 return false;
0914 default:
0915 return true;
0916 }
0917 }
0918
0919 static const struct regmap_config rpr0521_regmap_config = {
0920 .name = RPR0521_REGMAP_NAME,
0921
0922 .reg_bits = 8,
0923 .val_bits = 8,
0924
0925 .max_register = RPR0521_REG_ID,
0926 .cache_type = REGCACHE_RBTREE,
0927 .volatile_reg = rpr0521_is_volatile_reg,
0928 };
0929
0930 static int rpr0521_probe(struct i2c_client *client,
0931 const struct i2c_device_id *id)
0932 {
0933 struct rpr0521_data *data;
0934 struct iio_dev *indio_dev;
0935 struct regmap *regmap;
0936 int ret;
0937
0938 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0939 if (!indio_dev)
0940 return -ENOMEM;
0941
0942 regmap = devm_regmap_init_i2c(client, &rpr0521_regmap_config);
0943 if (IS_ERR(regmap)) {
0944 dev_err(&client->dev, "regmap_init failed!\n");
0945 return PTR_ERR(regmap);
0946 }
0947
0948 data = iio_priv(indio_dev);
0949 i2c_set_clientdata(client, indio_dev);
0950 data->client = client;
0951 data->regmap = regmap;
0952
0953 mutex_init(&data->lock);
0954
0955 indio_dev->info = &rpr0521_info;
0956 indio_dev->name = RPR0521_DRV_NAME;
0957 indio_dev->channels = rpr0521_channels;
0958 indio_dev->num_channels = ARRAY_SIZE(rpr0521_channels);
0959 indio_dev->modes = INDIO_DIRECT_MODE;
0960
0961 ret = rpr0521_init(data);
0962 if (ret < 0) {
0963 dev_err(&client->dev, "rpr0521 chip init failed\n");
0964 return ret;
0965 }
0966
0967 ret = pm_runtime_set_active(&client->dev);
0968 if (ret < 0)
0969 goto err_poweroff;
0970
0971 pm_runtime_enable(&client->dev);
0972 pm_runtime_set_autosuspend_delay(&client->dev, RPR0521_SLEEP_DELAY_MS);
0973 pm_runtime_use_autosuspend(&client->dev);
0974
0975
0976
0977
0978
0979
0980
0981 if (client->irq) {
0982
0983 data->drdy_trigger0 = devm_iio_trigger_alloc(
0984 indio_dev->dev.parent,
0985 "%s-dev%d", indio_dev->name, iio_device_id(indio_dev));
0986 if (!data->drdy_trigger0) {
0987 ret = -ENOMEM;
0988 goto err_pm_disable;
0989 }
0990 data->drdy_trigger0->ops = &rpr0521_trigger_ops;
0991 indio_dev->available_scan_masks = rpr0521_available_scan_masks;
0992 iio_trigger_set_drvdata(data->drdy_trigger0, indio_dev);
0993
0994
0995 ret = devm_request_threaded_irq(&client->dev, client->irq,
0996 rpr0521_drdy_irq_handler, rpr0521_drdy_irq_thread,
0997 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0998 RPR0521_IRQ_NAME, indio_dev);
0999 if (ret < 0) {
1000 dev_err(&client->dev, "request irq %d for trigger0 failed\n",
1001 client->irq);
1002 goto err_pm_disable;
1003 }
1004
1005 ret = devm_iio_trigger_register(indio_dev->dev.parent,
1006 data->drdy_trigger0);
1007 if (ret) {
1008 dev_err(&client->dev, "iio trigger register failed\n");
1009 goto err_pm_disable;
1010 }
1011
1012
1013
1014
1015
1016
1017
1018 ret = devm_iio_triggered_buffer_setup(indio_dev->dev.parent,
1019 indio_dev,
1020 rpr0521_trigger_consumer_store_time,
1021 rpr0521_trigger_consumer_handler,
1022 &rpr0521_buffer_setup_ops);
1023 if (ret < 0) {
1024 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1025 goto err_pm_disable;
1026 }
1027 }
1028
1029 ret = iio_device_register(indio_dev);
1030 if (ret)
1031 goto err_pm_disable;
1032
1033 return 0;
1034
1035 err_pm_disable:
1036 pm_runtime_disable(&client->dev);
1037 pm_runtime_set_suspended(&client->dev);
1038 err_poweroff:
1039 rpr0521_poweroff(data);
1040
1041 return ret;
1042 }
1043
1044 static int rpr0521_remove(struct i2c_client *client)
1045 {
1046 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1047
1048 iio_device_unregister(indio_dev);
1049
1050 pm_runtime_disable(&client->dev);
1051 pm_runtime_set_suspended(&client->dev);
1052
1053 rpr0521_poweroff(iio_priv(indio_dev));
1054
1055 return 0;
1056 }
1057
1058 static int rpr0521_runtime_suspend(struct device *dev)
1059 {
1060 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1061 struct rpr0521_data *data = iio_priv(indio_dev);
1062 int ret;
1063
1064 mutex_lock(&data->lock);
1065
1066 if (!data->als_need_dis)
1067 data->als_ps_need_en = data->als_dev_en;
1068 if (!data->pxs_need_dis)
1069 data->pxs_ps_need_en = data->pxs_dev_en;
1070
1071
1072 ret = rpr0521_poweroff(data);
1073 regcache_mark_dirty(data->regmap);
1074 mutex_unlock(&data->lock);
1075
1076 return ret;
1077 }
1078
1079 static int rpr0521_runtime_resume(struct device *dev)
1080 {
1081 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1082 struct rpr0521_data *data = iio_priv(indio_dev);
1083 int ret;
1084
1085 regcache_sync(data->regmap);
1086 if (data->als_ps_need_en) {
1087 ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
1088 if (ret < 0)
1089 return ret;
1090 data->als_ps_need_en = false;
1091 }
1092
1093 if (data->pxs_ps_need_en) {
1094 ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
1095 if (ret < 0)
1096 return ret;
1097 data->pxs_ps_need_en = false;
1098 }
1099 msleep(100);
1100
1101 return 0;
1102 }
1103
1104 static const struct dev_pm_ops rpr0521_pm_ops = {
1105 RUNTIME_PM_OPS(rpr0521_runtime_suspend, rpr0521_runtime_resume, NULL)
1106 };
1107
1108 static const struct acpi_device_id rpr0521_acpi_match[] = {
1109 {"RPR0521", 0},
1110 { }
1111 };
1112 MODULE_DEVICE_TABLE(acpi, rpr0521_acpi_match);
1113
1114 static const struct i2c_device_id rpr0521_id[] = {
1115 {"rpr0521", 0},
1116 { }
1117 };
1118
1119 MODULE_DEVICE_TABLE(i2c, rpr0521_id);
1120
1121 static struct i2c_driver rpr0521_driver = {
1122 .driver = {
1123 .name = RPR0521_DRV_NAME,
1124 .pm = pm_ptr(&rpr0521_pm_ops),
1125 .acpi_match_table = ACPI_PTR(rpr0521_acpi_match),
1126 },
1127 .probe = rpr0521_probe,
1128 .remove = rpr0521_remove,
1129 .id_table = rpr0521_id,
1130 };
1131
1132 module_i2c_driver(rpr0521_driver);
1133
1134 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1135 MODULE_DESCRIPTION("RPR0521 ROHM Ambient Light and Proximity Sensor driver");
1136 MODULE_LICENSE("GPL v2");