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0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/i2c.h>
0015 #include <linux/regmap.h>
0016 #include <linux/util_macros.h>
0017 #include <linux/iio/iio.h>
0018 #include <linux/iio/sysfs.h>
0019 #include <linux/iio/buffer.h>
0020 #include <linux/iio/trigger_consumer.h>
0021 #include <linux/iio/triggered_buffer.h>
0022 #include <linux/acpi.h>
0023
0024 #define MAX44000_DRV_NAME "max44000"
0025
0026
0027 #define MAX44000_REG_STATUS 0x00
0028 #define MAX44000_REG_CFG_MAIN 0x01
0029 #define MAX44000_REG_CFG_RX 0x02
0030 #define MAX44000_REG_CFG_TX 0x03
0031 #define MAX44000_REG_ALS_DATA_HI 0x04
0032 #define MAX44000_REG_ALS_DATA_LO 0x05
0033 #define MAX44000_REG_PRX_DATA 0x16
0034 #define MAX44000_REG_ALS_UPTHR_HI 0x06
0035 #define MAX44000_REG_ALS_UPTHR_LO 0x07
0036 #define MAX44000_REG_ALS_LOTHR_HI 0x08
0037 #define MAX44000_REG_ALS_LOTHR_LO 0x09
0038 #define MAX44000_REG_PST 0x0a
0039 #define MAX44000_REG_PRX_IND 0x0b
0040 #define MAX44000_REG_PRX_THR 0x0c
0041 #define MAX44000_REG_TRIM_GAIN_GREEN 0x0f
0042 #define MAX44000_REG_TRIM_GAIN_IR 0x10
0043
0044
0045 #define MAX44000_CFG_ALSINTE 0x01
0046 #define MAX44000_CFG_PRXINTE 0x02
0047 #define MAX44000_CFG_MASK 0x1c
0048 #define MAX44000_CFG_MODE_SHUTDOWN 0x00
0049 #define MAX44000_CFG_MODE_ALS_GIR 0x04
0050 #define MAX44000_CFG_MODE_ALS_G 0x08
0051 #define MAX44000_CFG_MODE_ALS_IR 0x0c
0052 #define MAX44000_CFG_MODE_ALS_PRX 0x10
0053 #define MAX44000_CFG_MODE_PRX 0x14
0054 #define MAX44000_CFG_TRIM 0x20
0055
0056
0057
0058
0059
0060 #define MAX44000_REG_CFG_RX_DEFAULT 0xf0
0061
0062
0063 #define MAX44000_CFG_RX_ALSTIM_MASK 0x0c
0064 #define MAX44000_CFG_RX_ALSTIM_SHIFT 2
0065 #define MAX44000_CFG_RX_ALSPGA_MASK 0x03
0066 #define MAX44000_CFG_RX_ALSPGA_SHIFT 0
0067
0068
0069 #define MAX44000_LED_CURRENT_MASK 0xf
0070 #define MAX44000_LED_CURRENT_MAX 11
0071 #define MAX44000_LED_CURRENT_DEFAULT 6
0072
0073 #define MAX44000_ALSDATA_OVERFLOW 0x4000
0074
0075 struct max44000_data {
0076 struct mutex lock;
0077 struct regmap *regmap;
0078
0079 struct {
0080 u16 channels[2];
0081 s64 ts __aligned(8);
0082 } scan;
0083 };
0084
0085
0086 #define MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2 5
0087
0088
0089 static const int max44000_alspga_shift[] = {0, 2, 4, 7};
0090 #define MAX44000_ALSPGA_MAX_SHIFT 7
0091
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
0103
0104 #define MAX44000_ALSTIM_SHIFT(alstim) (2 * (alstim))
0105
0106
0107 static const int max44000_int_time_avail_ns_array[] = {
0108 100000000,
0109 25000000,
0110 6250000,
0111 1562500,
0112 };
0113 static const char max44000_int_time_avail_str[] =
0114 "0.100 "
0115 "0.025 "
0116 "0.00625 "
0117 "0.0015625";
0118
0119
0120 static const int max44000_scale_avail_ulux_array[] = {
0121 31250,
0122 125000,
0123 500000,
0124 4000000,
0125 };
0126 static const char max44000_scale_avail_str[] =
0127 "0.03125 "
0128 "0.125 "
0129 "0.5 "
0130 "4";
0131
0132 #define MAX44000_SCAN_INDEX_ALS 0
0133 #define MAX44000_SCAN_INDEX_PRX 1
0134
0135 static const struct iio_chan_spec max44000_channels[] = {
0136 {
0137 .type = IIO_LIGHT,
0138 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0139 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
0140 BIT(IIO_CHAN_INFO_INT_TIME),
0141 .scan_index = MAX44000_SCAN_INDEX_ALS,
0142 .scan_type = {
0143 .sign = 'u',
0144 .realbits = 14,
0145 .storagebits = 16,
0146 }
0147 },
0148 {
0149 .type = IIO_PROXIMITY,
0150 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0151 .scan_index = MAX44000_SCAN_INDEX_PRX,
0152 .scan_type = {
0153 .sign = 'u',
0154 .realbits = 8,
0155 .storagebits = 16,
0156 }
0157 },
0158 IIO_CHAN_SOFT_TIMESTAMP(2),
0159 {
0160 .type = IIO_CURRENT,
0161 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0162 BIT(IIO_CHAN_INFO_SCALE),
0163 .extend_name = "led",
0164 .output = 1,
0165 .scan_index = -1,
0166 },
0167 };
0168
0169 static int max44000_read_alstim(struct max44000_data *data)
0170 {
0171 unsigned int val;
0172 int ret;
0173
0174 ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val);
0175 if (ret < 0)
0176 return ret;
0177 return (val & MAX44000_CFG_RX_ALSTIM_MASK) >> MAX44000_CFG_RX_ALSTIM_SHIFT;
0178 }
0179
0180 static int max44000_write_alstim(struct max44000_data *data, int val)
0181 {
0182 return regmap_write_bits(data->regmap, MAX44000_REG_CFG_RX,
0183 MAX44000_CFG_RX_ALSTIM_MASK,
0184 val << MAX44000_CFG_RX_ALSTIM_SHIFT);
0185 }
0186
0187 static int max44000_read_alspga(struct max44000_data *data)
0188 {
0189 unsigned int val;
0190 int ret;
0191
0192 ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val);
0193 if (ret < 0)
0194 return ret;
0195 return (val & MAX44000_CFG_RX_ALSPGA_MASK) >> MAX44000_CFG_RX_ALSPGA_SHIFT;
0196 }
0197
0198 static int max44000_write_alspga(struct max44000_data *data, int val)
0199 {
0200 return regmap_write_bits(data->regmap, MAX44000_REG_CFG_RX,
0201 MAX44000_CFG_RX_ALSPGA_MASK,
0202 val << MAX44000_CFG_RX_ALSPGA_SHIFT);
0203 }
0204
0205 static int max44000_read_alsval(struct max44000_data *data)
0206 {
0207 u16 regval;
0208 __be16 val;
0209 int alstim, ret;
0210
0211 ret = regmap_bulk_read(data->regmap, MAX44000_REG_ALS_DATA_HI,
0212 &val, sizeof(val));
0213 if (ret < 0)
0214 return ret;
0215 alstim = ret = max44000_read_alstim(data);
0216 if (ret < 0)
0217 return ret;
0218
0219 regval = be16_to_cpu(val);
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230 if (regval & MAX44000_ALSDATA_OVERFLOW)
0231 return 0x3FFF;
0232
0233 return regval << MAX44000_ALSTIM_SHIFT(alstim);
0234 }
0235
0236 static int max44000_write_led_current_raw(struct max44000_data *data, int val)
0237 {
0238
0239 if (val < 0 || val > MAX44000_LED_CURRENT_MAX)
0240 return -ERANGE;
0241 if (val >= 8)
0242 val += 4;
0243 return regmap_write_bits(data->regmap, MAX44000_REG_CFG_TX,
0244 MAX44000_LED_CURRENT_MASK, val);
0245 }
0246
0247 static int max44000_read_led_current_raw(struct max44000_data *data)
0248 {
0249 unsigned int regval;
0250 int ret;
0251
0252 ret = regmap_read(data->regmap, MAX44000_REG_CFG_TX, ®val);
0253 if (ret < 0)
0254 return ret;
0255 regval &= MAX44000_LED_CURRENT_MASK;
0256 if (regval >= 8)
0257 regval -= 4;
0258 return regval;
0259 }
0260
0261 static int max44000_read_raw(struct iio_dev *indio_dev,
0262 struct iio_chan_spec const *chan,
0263 int *val, int *val2, long mask)
0264 {
0265 struct max44000_data *data = iio_priv(indio_dev);
0266 int alstim, alspga;
0267 unsigned int regval;
0268 int ret;
0269
0270 switch (mask) {
0271 case IIO_CHAN_INFO_RAW:
0272 switch (chan->type) {
0273 case IIO_LIGHT:
0274 mutex_lock(&data->lock);
0275 ret = max44000_read_alsval(data);
0276 mutex_unlock(&data->lock);
0277 if (ret < 0)
0278 return ret;
0279 *val = ret;
0280 return IIO_VAL_INT;
0281
0282 case IIO_PROXIMITY:
0283 mutex_lock(&data->lock);
0284 ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, ®val);
0285 mutex_unlock(&data->lock);
0286 if (ret < 0)
0287 return ret;
0288 *val = regval;
0289 return IIO_VAL_INT;
0290
0291 case IIO_CURRENT:
0292 mutex_lock(&data->lock);
0293 ret = max44000_read_led_current_raw(data);
0294 mutex_unlock(&data->lock);
0295 if (ret < 0)
0296 return ret;
0297 *val = ret;
0298 return IIO_VAL_INT;
0299
0300 default:
0301 return -EINVAL;
0302 }
0303
0304 case IIO_CHAN_INFO_SCALE:
0305 switch (chan->type) {
0306 case IIO_CURRENT:
0307
0308 *val = 10;
0309 return IIO_VAL_INT;
0310
0311 case IIO_LIGHT:
0312 mutex_lock(&data->lock);
0313 alspga = ret = max44000_read_alspga(data);
0314 mutex_unlock(&data->lock);
0315 if (ret < 0)
0316 return ret;
0317
0318
0319 *val = (1 << MAX44000_ALSPGA_MAX_SHIFT);
0320 *val2 = MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2
0321 + MAX44000_ALSPGA_MAX_SHIFT
0322 - max44000_alspga_shift[alspga];
0323 return IIO_VAL_FRACTIONAL_LOG2;
0324
0325 default:
0326 return -EINVAL;
0327 }
0328
0329 case IIO_CHAN_INFO_INT_TIME:
0330 mutex_lock(&data->lock);
0331 alstim = ret = max44000_read_alstim(data);
0332 mutex_unlock(&data->lock);
0333
0334 if (ret < 0)
0335 return ret;
0336 *val = 0;
0337 *val2 = max44000_int_time_avail_ns_array[alstim];
0338 return IIO_VAL_INT_PLUS_NANO;
0339
0340 default:
0341 return -EINVAL;
0342 }
0343 }
0344
0345 static int max44000_write_raw(struct iio_dev *indio_dev,
0346 struct iio_chan_spec const *chan,
0347 int val, int val2, long mask)
0348 {
0349 struct max44000_data *data = iio_priv(indio_dev);
0350 int ret;
0351
0352 if (mask == IIO_CHAN_INFO_RAW && chan->type == IIO_CURRENT) {
0353 mutex_lock(&data->lock);
0354 ret = max44000_write_led_current_raw(data, val);
0355 mutex_unlock(&data->lock);
0356 return ret;
0357 } else if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) {
0358 s64 valns = val * NSEC_PER_SEC + val2;
0359 int alstim = find_closest_descending(valns,
0360 max44000_int_time_avail_ns_array,
0361 ARRAY_SIZE(max44000_int_time_avail_ns_array));
0362 mutex_lock(&data->lock);
0363 ret = max44000_write_alstim(data, alstim);
0364 mutex_unlock(&data->lock);
0365 return ret;
0366 } else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT) {
0367 s64 valus = val * USEC_PER_SEC + val2;
0368 int alspga = find_closest(valus,
0369 max44000_scale_avail_ulux_array,
0370 ARRAY_SIZE(max44000_scale_avail_ulux_array));
0371 mutex_lock(&data->lock);
0372 ret = max44000_write_alspga(data, alspga);
0373 mutex_unlock(&data->lock);
0374 return ret;
0375 }
0376
0377 return -EINVAL;
0378 }
0379
0380 static int max44000_write_raw_get_fmt(struct iio_dev *indio_dev,
0381 struct iio_chan_spec const *chan,
0382 long mask)
0383 {
0384 if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT)
0385 return IIO_VAL_INT_PLUS_NANO;
0386 else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT)
0387 return IIO_VAL_INT_PLUS_MICRO;
0388 else
0389 return IIO_VAL_INT;
0390 }
0391
0392 static IIO_CONST_ATTR(illuminance_integration_time_available, max44000_int_time_avail_str);
0393 static IIO_CONST_ATTR(illuminance_scale_available, max44000_scale_avail_str);
0394
0395 static struct attribute *max44000_attributes[] = {
0396 &iio_const_attr_illuminance_integration_time_available.dev_attr.attr,
0397 &iio_const_attr_illuminance_scale_available.dev_attr.attr,
0398 NULL
0399 };
0400
0401 static const struct attribute_group max44000_attribute_group = {
0402 .attrs = max44000_attributes,
0403 };
0404
0405 static const struct iio_info max44000_info = {
0406 .read_raw = max44000_read_raw,
0407 .write_raw = max44000_write_raw,
0408 .write_raw_get_fmt = max44000_write_raw_get_fmt,
0409 .attrs = &max44000_attribute_group,
0410 };
0411
0412 static bool max44000_readable_reg(struct device *dev, unsigned int reg)
0413 {
0414 switch (reg) {
0415 case MAX44000_REG_STATUS:
0416 case MAX44000_REG_CFG_MAIN:
0417 case MAX44000_REG_CFG_RX:
0418 case MAX44000_REG_CFG_TX:
0419 case MAX44000_REG_ALS_DATA_HI:
0420 case MAX44000_REG_ALS_DATA_LO:
0421 case MAX44000_REG_PRX_DATA:
0422 case MAX44000_REG_ALS_UPTHR_HI:
0423 case MAX44000_REG_ALS_UPTHR_LO:
0424 case MAX44000_REG_ALS_LOTHR_HI:
0425 case MAX44000_REG_ALS_LOTHR_LO:
0426 case MAX44000_REG_PST:
0427 case MAX44000_REG_PRX_IND:
0428 case MAX44000_REG_PRX_THR:
0429 case MAX44000_REG_TRIM_GAIN_GREEN:
0430 case MAX44000_REG_TRIM_GAIN_IR:
0431 return true;
0432 default:
0433 return false;
0434 }
0435 }
0436
0437 static bool max44000_writeable_reg(struct device *dev, unsigned int reg)
0438 {
0439 switch (reg) {
0440 case MAX44000_REG_CFG_MAIN:
0441 case MAX44000_REG_CFG_RX:
0442 case MAX44000_REG_CFG_TX:
0443 case MAX44000_REG_ALS_UPTHR_HI:
0444 case MAX44000_REG_ALS_UPTHR_LO:
0445 case MAX44000_REG_ALS_LOTHR_HI:
0446 case MAX44000_REG_ALS_LOTHR_LO:
0447 case MAX44000_REG_PST:
0448 case MAX44000_REG_PRX_IND:
0449 case MAX44000_REG_PRX_THR:
0450 case MAX44000_REG_TRIM_GAIN_GREEN:
0451 case MAX44000_REG_TRIM_GAIN_IR:
0452 return true;
0453 default:
0454 return false;
0455 }
0456 }
0457
0458 static bool max44000_volatile_reg(struct device *dev, unsigned int reg)
0459 {
0460 switch (reg) {
0461 case MAX44000_REG_STATUS:
0462 case MAX44000_REG_ALS_DATA_HI:
0463 case MAX44000_REG_ALS_DATA_LO:
0464 case MAX44000_REG_PRX_DATA:
0465 return true;
0466 default:
0467 return false;
0468 }
0469 }
0470
0471 static bool max44000_precious_reg(struct device *dev, unsigned int reg)
0472 {
0473 return reg == MAX44000_REG_STATUS;
0474 }
0475
0476 static const struct regmap_config max44000_regmap_config = {
0477 .reg_bits = 8,
0478 .val_bits = 8,
0479
0480 .max_register = MAX44000_REG_PRX_DATA,
0481 .readable_reg = max44000_readable_reg,
0482 .writeable_reg = max44000_writeable_reg,
0483 .volatile_reg = max44000_volatile_reg,
0484 .precious_reg = max44000_precious_reg,
0485
0486 .use_single_read = true,
0487 .use_single_write = true,
0488 .cache_type = REGCACHE_RBTREE,
0489 };
0490
0491 static irqreturn_t max44000_trigger_handler(int irq, void *p)
0492 {
0493 struct iio_poll_func *pf = p;
0494 struct iio_dev *indio_dev = pf->indio_dev;
0495 struct max44000_data *data = iio_priv(indio_dev);
0496 int index = 0;
0497 unsigned int regval;
0498 int ret;
0499
0500 mutex_lock(&data->lock);
0501 if (test_bit(MAX44000_SCAN_INDEX_ALS, indio_dev->active_scan_mask)) {
0502 ret = max44000_read_alsval(data);
0503 if (ret < 0)
0504 goto out_unlock;
0505 data->scan.channels[index++] = ret;
0506 }
0507 if (test_bit(MAX44000_SCAN_INDEX_PRX, indio_dev->active_scan_mask)) {
0508 ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, ®val);
0509 if (ret < 0)
0510 goto out_unlock;
0511 data->scan.channels[index] = regval;
0512 }
0513 mutex_unlock(&data->lock);
0514
0515 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
0516 iio_get_time_ns(indio_dev));
0517 iio_trigger_notify_done(indio_dev->trig);
0518 return IRQ_HANDLED;
0519
0520 out_unlock:
0521 mutex_unlock(&data->lock);
0522 iio_trigger_notify_done(indio_dev->trig);
0523 return IRQ_HANDLED;
0524 }
0525
0526 static int max44000_probe(struct i2c_client *client,
0527 const struct i2c_device_id *id)
0528 {
0529 struct max44000_data *data;
0530 struct iio_dev *indio_dev;
0531 int ret, reg;
0532
0533 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0534 if (!indio_dev)
0535 return -ENOMEM;
0536 data = iio_priv(indio_dev);
0537 data->regmap = devm_regmap_init_i2c(client, &max44000_regmap_config);
0538 if (IS_ERR(data->regmap)) {
0539 dev_err(&client->dev, "regmap_init failed!\n");
0540 return PTR_ERR(data->regmap);
0541 }
0542
0543 mutex_init(&data->lock);
0544 indio_dev->info = &max44000_info;
0545 indio_dev->name = MAX44000_DRV_NAME;
0546 indio_dev->channels = max44000_channels;
0547 indio_dev->num_channels = ARRAY_SIZE(max44000_channels);
0548
0549
0550
0551
0552
0553
0554
0555
0556
0557
0558 ret = regmap_write(data->regmap, MAX44000_REG_CFG_RX,
0559 MAX44000_REG_CFG_RX_DEFAULT);
0560 if (ret < 0) {
0561 dev_err(&client->dev, "failed to write default CFG_RX: %d\n",
0562 ret);
0563 return ret;
0564 }
0565
0566
0567
0568
0569
0570 ret = max44000_write_led_current_raw(data, MAX44000_LED_CURRENT_DEFAULT);
0571 if (ret < 0) {
0572 dev_err(&client->dev, "failed to write init config: %d\n", ret);
0573 return ret;
0574 }
0575
0576
0577 reg = MAX44000_CFG_TRIM | MAX44000_CFG_MODE_ALS_PRX;
0578 ret = regmap_write(data->regmap, MAX44000_REG_CFG_MAIN, reg);
0579 if (ret < 0) {
0580 dev_err(&client->dev, "failed to write init config: %d\n", ret);
0581 return ret;
0582 }
0583
0584
0585 ret = regmap_read(data->regmap, MAX44000_REG_STATUS, ®);
0586 if (ret < 0) {
0587 dev_err(&client->dev, "failed to read init status: %d\n", ret);
0588 return ret;
0589 }
0590
0591 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
0592 max44000_trigger_handler, NULL);
0593 if (ret < 0) {
0594 dev_err(&client->dev, "iio triggered buffer setup failed\n");
0595 return ret;
0596 }
0597
0598 return devm_iio_device_register(&client->dev, indio_dev);
0599 }
0600
0601 static const struct i2c_device_id max44000_id[] = {
0602 {"max44000", 0},
0603 { }
0604 };
0605 MODULE_DEVICE_TABLE(i2c, max44000_id);
0606
0607 #ifdef CONFIG_ACPI
0608 static const struct acpi_device_id max44000_acpi_match[] = {
0609 {"MAX44000", 0},
0610 { }
0611 };
0612 MODULE_DEVICE_TABLE(acpi, max44000_acpi_match);
0613 #endif
0614
0615 static struct i2c_driver max44000_driver = {
0616 .driver = {
0617 .name = MAX44000_DRV_NAME,
0618 .acpi_match_table = ACPI_PTR(max44000_acpi_match),
0619 },
0620 .probe = max44000_probe,
0621 .id_table = max44000_id,
0622 };
0623
0624 module_i2c_driver(max44000_driver);
0625
0626 MODULE_AUTHOR("Crestez Dan Leonard <leonard.crestez@intel.com>");
0627 MODULE_DESCRIPTION("MAX44000 Ambient and Infrared Proximity Sensor");
0628 MODULE_LICENSE("GPL v2");