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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * adux1020.c - Support for Analog Devices ADUX1020 photometric sensor
0004  *
0005  * Copyright (C) 2019 Linaro Ltd.
0006  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0007  *
0008  * TODO: Triggered buffer support
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/delay.h>
0013 #include <linux/err.h>
0014 #include <linux/i2c.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/irq.h>
0018 #include <linux/module.h>
0019 #include <linux/mutex.h>
0020 #include <linux/regmap.h>
0021 
0022 #include <linux/iio/iio.h>
0023 #include <linux/iio/sysfs.h>
0024 #include <linux/iio/events.h>
0025 
0026 #define ADUX1020_REGMAP_NAME        "adux1020_regmap"
0027 #define ADUX1020_DRV_NAME       "adux1020"
0028 
0029 /* System registers */
0030 #define ADUX1020_REG_CHIP_ID        0x08
0031 #define ADUX1020_REG_SLAVE_ADDRESS  0x09
0032 
0033 #define ADUX1020_REG_SW_RESET       0x0f
0034 #define ADUX1020_REG_INT_ENABLE     0x1c
0035 #define ADUX1020_REG_INT_POLARITY   0x1d
0036 #define ADUX1020_REG_PROX_TH_ON1    0x2a
0037 #define ADUX1020_REG_PROX_TH_OFF1   0x2b
0038 #define ADUX1020_REG_PROX_TYPE      0x2f
0039 #define ADUX1020_REG_TEST_MODES_3   0x32
0040 #define ADUX1020_REG_FORCE_MODE     0x33
0041 #define ADUX1020_REG_FREQUENCY      0x40
0042 #define ADUX1020_REG_LED_CURRENT    0x41
0043 #define ADUX1020_REG_OP_MODE        0x45
0044 #define ADUX1020_REG_INT_MASK       0x48
0045 #define ADUX1020_REG_INT_STATUS     0x49
0046 #define ADUX1020_REG_DATA_BUFFER    0x60
0047 
0048 /* Chip ID bits */
0049 #define ADUX1020_CHIP_ID_MASK       GENMASK(11, 0)
0050 #define ADUX1020_CHIP_ID        0x03fc
0051 
0052 #define ADUX1020_SW_RESET       BIT(1)
0053 #define ADUX1020_FIFO_FLUSH     BIT(15)
0054 #define ADUX1020_OP_MODE_MASK       GENMASK(3, 0)
0055 #define ADUX1020_DATA_OUT_MODE_MASK GENMASK(7, 4)
0056 #define ADUX1020_DATA_OUT_PROX_I    FIELD_PREP(ADUX1020_DATA_OUT_MODE_MASK, 1)
0057 
0058 #define ADUX1020_MODE_INT_MASK      GENMASK(7, 0)
0059 #define ADUX1020_INT_ENABLE     0x2094
0060 #define ADUX1020_INT_DISABLE        0x2090
0061 #define ADUX1020_PROX_INT_ENABLE    0x00f0
0062 #define ADUX1020_PROX_ON1_INT       BIT(0)
0063 #define ADUX1020_PROX_OFF1_INT      BIT(1)
0064 #define ADUX1020_FIFO_INT_ENABLE    0x7f
0065 #define ADUX1020_MODE_INT_DISABLE   0xff
0066 #define ADUX1020_MODE_INT_STATUS_MASK   GENMASK(7, 0)
0067 #define ADUX1020_FIFO_STATUS_MASK   GENMASK(15, 8)
0068 #define ADUX1020_INT_CLEAR      0xff
0069 #define ADUX1020_PROX_TYPE      BIT(15)
0070 
0071 #define ADUX1020_INT_PROX_ON1       BIT(0)
0072 #define ADUX1020_INT_PROX_OFF1      BIT(1)
0073 
0074 #define ADUX1020_FORCE_CLOCK_ON     0x0f4f
0075 #define ADUX1020_FORCE_CLOCK_RESET  0x0040
0076 #define ADUX1020_ACTIVE_4_STATE     0x0008
0077 
0078 #define ADUX1020_PROX_FREQ_MASK     GENMASK(7, 4)
0079 #define ADUX1020_PROX_FREQ(x)       FIELD_PREP(ADUX1020_PROX_FREQ_MASK, x)
0080 
0081 #define ADUX1020_LED_CURRENT_MASK   GENMASK(3, 0)
0082 #define ADUX1020_LED_PIREF_EN       BIT(12)
0083 
0084 /* Operating modes */
0085 enum adux1020_op_modes {
0086     ADUX1020_MODE_STANDBY,
0087     ADUX1020_MODE_PROX_I,
0088     ADUX1020_MODE_PROX_XY,
0089     ADUX1020_MODE_GEST,
0090     ADUX1020_MODE_SAMPLE,
0091     ADUX1020_MODE_FORCE = 0x0e,
0092     ADUX1020_MODE_IDLE = 0x0f,
0093 };
0094 
0095 struct adux1020_data {
0096     struct i2c_client *client;
0097     struct iio_dev *indio_dev;
0098     struct mutex lock;
0099     struct regmap *regmap;
0100 };
0101 
0102 struct adux1020_mode_data {
0103     u8 bytes;
0104     u8 buf_len;
0105     u16 int_en;
0106 };
0107 
0108 static const struct adux1020_mode_data adux1020_modes[] = {
0109     [ADUX1020_MODE_PROX_I] = {
0110         .bytes = 2,
0111         .buf_len = 1,
0112         .int_en = ADUX1020_PROX_INT_ENABLE,
0113     },
0114 };
0115 
0116 static const struct regmap_config adux1020_regmap_config = {
0117     .name = ADUX1020_REGMAP_NAME,
0118     .reg_bits = 8,
0119     .val_bits = 16,
0120     .max_register = 0x6F,
0121     .cache_type = REGCACHE_NONE,
0122 };
0123 
0124 static const struct reg_sequence adux1020_def_conf[] = {
0125     { 0x000c, 0x000f },
0126     { 0x0010, 0x1010 },
0127     { 0x0011, 0x004c },
0128     { 0x0012, 0x5f0c },
0129     { 0x0013, 0xada5 },
0130     { 0x0014, 0x0080 },
0131     { 0x0015, 0x0000 },
0132     { 0x0016, 0x0600 },
0133     { 0x0017, 0x0000 },
0134     { 0x0018, 0x2693 },
0135     { 0x0019, 0x0004 },
0136     { 0x001a, 0x4280 },
0137     { 0x001b, 0x0060 },
0138     { 0x001c, 0x2094 },
0139     { 0x001d, 0x0020 },
0140     { 0x001e, 0x0001 },
0141     { 0x001f, 0x0100 },
0142     { 0x0020, 0x0320 },
0143     { 0x0021, 0x0A13 },
0144     { 0x0022, 0x0320 },
0145     { 0x0023, 0x0113 },
0146     { 0x0024, 0x0000 },
0147     { 0x0025, 0x2412 },
0148     { 0x0026, 0x2412 },
0149     { 0x0027, 0x0022 },
0150     { 0x0028, 0x0000 },
0151     { 0x0029, 0x0300 },
0152     { 0x002a, 0x0700 },
0153     { 0x002b, 0x0600 },
0154     { 0x002c, 0x6000 },
0155     { 0x002d, 0x4000 },
0156     { 0x002e, 0x0000 },
0157     { 0x002f, 0x0000 },
0158     { 0x0030, 0x0000 },
0159     { 0x0031, 0x0000 },
0160     { 0x0032, 0x0040 },
0161     { 0x0033, 0x0008 },
0162     { 0x0034, 0xE400 },
0163     { 0x0038, 0x8080 },
0164     { 0x0039, 0x8080 },
0165     { 0x003a, 0x2000 },
0166     { 0x003b, 0x1f00 },
0167     { 0x003c, 0x2000 },
0168     { 0x003d, 0x2000 },
0169     { 0x003e, 0x0000 },
0170     { 0x0040, 0x8069 },
0171     { 0x0041, 0x1f2f },
0172     { 0x0042, 0x4000 },
0173     { 0x0043, 0x0000 },
0174     { 0x0044, 0x0008 },
0175     { 0x0046, 0x0000 },
0176     { 0x0048, 0x00ef },
0177     { 0x0049, 0x0000 },
0178     { 0x0045, 0x0000 },
0179 };
0180 
0181 static const int adux1020_rates[][2] = {
0182     { 0, 100000 },
0183     { 0, 200000 },
0184     { 0, 500000 },
0185     { 1, 0 },
0186     { 2, 0 },
0187     { 5, 0 },
0188     { 10, 0 },
0189     { 20, 0 },
0190     { 50, 0 },
0191     { 100, 0 },
0192     { 190, 0 },
0193     { 450, 0 },
0194     { 820, 0 },
0195     { 1400, 0 },
0196 };
0197 
0198 static const int adux1020_led_currents[][2] = {
0199     { 0, 25000 },
0200     { 0, 40000 },
0201     { 0, 55000 },
0202     { 0, 70000 },
0203     { 0, 85000 },
0204     { 0, 100000 },
0205     { 0, 115000 },
0206     { 0, 130000 },
0207     { 0, 145000 },
0208     { 0, 160000 },
0209     { 0, 175000 },
0210     { 0, 190000 },
0211     { 0, 205000 },
0212     { 0, 220000 },
0213     { 0, 235000 },
0214     { 0, 250000 },
0215 };
0216 
0217 static int adux1020_flush_fifo(struct adux1020_data *data)
0218 {
0219     int ret;
0220 
0221     /* Force Idle mode */
0222     ret = regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE,
0223                ADUX1020_ACTIVE_4_STATE);
0224     if (ret < 0)
0225         return ret;
0226 
0227     ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
0228                  ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE);
0229     if (ret < 0)
0230         return ret;
0231 
0232     ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
0233                  ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE);
0234     if (ret < 0)
0235         return ret;
0236 
0237     /* Flush FIFO */
0238     ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
0239                ADUX1020_FORCE_CLOCK_ON);
0240     if (ret < 0)
0241         return ret;
0242 
0243     ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
0244                ADUX1020_FIFO_FLUSH);
0245     if (ret < 0)
0246         return ret;
0247 
0248     return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
0249                 ADUX1020_FORCE_CLOCK_RESET);
0250 }
0251 
0252 static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len)
0253 {
0254     unsigned int regval;
0255     int i, ret;
0256 
0257     /* Enable 32MHz clock */
0258     ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
0259                ADUX1020_FORCE_CLOCK_ON);
0260     if (ret < 0)
0261         return ret;
0262 
0263     for (i = 0; i < buf_len; i++) {
0264         ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER,
0265                   &regval);
0266         if (ret < 0)
0267             return ret;
0268 
0269         buf[i] = regval;
0270     }
0271 
0272     /* Set 32MHz clock to be controlled by internal state machine */
0273     return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
0274                 ADUX1020_FORCE_CLOCK_RESET);
0275 }
0276 
0277 static int adux1020_set_mode(struct adux1020_data *data,
0278                  enum adux1020_op_modes mode)
0279 {
0280     int ret;
0281 
0282     /* Switch to standby mode before changing the mode */
0283     ret = regmap_write(data->regmap, ADUX1020_REG_OP_MODE,
0284                ADUX1020_MODE_STANDBY);
0285     if (ret < 0)
0286         return ret;
0287 
0288     /* Set data out and switch to the desired mode */
0289     switch (mode) {
0290     case ADUX1020_MODE_PROX_I:
0291         ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
0292                      ADUX1020_DATA_OUT_MODE_MASK,
0293                      ADUX1020_DATA_OUT_PROX_I);
0294         if (ret < 0)
0295             return ret;
0296 
0297         ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
0298                      ADUX1020_OP_MODE_MASK,
0299                      ADUX1020_MODE_PROX_I);
0300         if (ret < 0)
0301             return ret;
0302         break;
0303     default:
0304         return -EINVAL;
0305     }
0306 
0307     return 0;
0308 }
0309 
0310 static int adux1020_measure(struct adux1020_data *data,
0311                 enum adux1020_op_modes mode,
0312                 u16 *val)
0313 {
0314     unsigned int status;
0315     int ret, tries = 50;
0316 
0317     /* Disable INT pin as polling is going to be used */
0318     ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
0319                ADUX1020_INT_DISABLE);
0320     if (ret < 0)
0321         return ret;
0322 
0323     /* Enable mode interrupt */
0324     ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
0325                  ADUX1020_MODE_INT_MASK,
0326                  adux1020_modes[mode].int_en);
0327     if (ret < 0)
0328         return ret;
0329 
0330     while (tries--) {
0331         ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS,
0332                   &status);
0333         if (ret < 0)
0334             return ret;
0335 
0336         status &= ADUX1020_FIFO_STATUS_MASK;
0337         if (status >= adux1020_modes[mode].bytes)
0338             break;
0339         msleep(20);
0340     }
0341 
0342     if (tries < 0)
0343         return -EIO;
0344 
0345     ret = adux1020_read_fifo(data, val, adux1020_modes[mode].buf_len);
0346     if (ret < 0)
0347         return ret;
0348 
0349     /* Clear mode interrupt */
0350     ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
0351                (~adux1020_modes[mode].int_en));
0352     if (ret < 0)
0353         return ret;
0354 
0355     /* Disable mode interrupts */
0356     return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
0357                   ADUX1020_MODE_INT_MASK,
0358                   ADUX1020_MODE_INT_DISABLE);
0359 }
0360 
0361 static int adux1020_read_raw(struct iio_dev *indio_dev,
0362                  struct iio_chan_spec const *chan,
0363                  int *val, int *val2, long mask)
0364 {
0365     struct adux1020_data *data = iio_priv(indio_dev);
0366     u16 buf[3];
0367     int ret = -EINVAL;
0368     unsigned int regval;
0369 
0370     mutex_lock(&data->lock);
0371 
0372     switch (mask) {
0373     case IIO_CHAN_INFO_RAW:
0374         switch (chan->type) {
0375         case IIO_PROXIMITY:
0376             ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
0377             if (ret < 0)
0378                 goto fail;
0379 
0380             ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, buf);
0381             if (ret < 0)
0382                 goto fail;
0383 
0384             *val = buf[0];
0385             ret = IIO_VAL_INT;
0386             break;
0387         default:
0388             break;
0389         }
0390         break;
0391     case IIO_CHAN_INFO_PROCESSED:
0392         switch (chan->type) {
0393         case IIO_CURRENT:
0394             ret = regmap_read(data->regmap,
0395                       ADUX1020_REG_LED_CURRENT, &regval);
0396             if (ret < 0)
0397                 goto fail;
0398 
0399             regval = regval & ADUX1020_LED_CURRENT_MASK;
0400 
0401             *val = adux1020_led_currents[regval][0];
0402             *val2 = adux1020_led_currents[regval][1];
0403 
0404             ret = IIO_VAL_INT_PLUS_MICRO;
0405             break;
0406         default:
0407             break;
0408         }
0409         break;
0410     case IIO_CHAN_INFO_SAMP_FREQ:
0411         switch (chan->type) {
0412         case IIO_PROXIMITY:
0413             ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY,
0414                       &regval);
0415             if (ret < 0)
0416                 goto fail;
0417 
0418             regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);
0419 
0420             *val = adux1020_rates[regval][0];
0421             *val2 = adux1020_rates[regval][1];
0422 
0423             ret = IIO_VAL_INT_PLUS_MICRO;
0424             break;
0425         default:
0426             break;
0427         }
0428         break;
0429     default:
0430         break;
0431     }
0432 
0433 fail:
0434     mutex_unlock(&data->lock);
0435 
0436     return ret;
0437 };
0438 
0439 static inline int adux1020_find_index(const int array[][2], int count, int val,
0440                       int val2)
0441 {
0442     int i;
0443 
0444     for (i = 0; i < count; i++)
0445         if (val == array[i][0] && val2 == array[i][1])
0446             return i;
0447 
0448     return -EINVAL;
0449 }
0450 
0451 static int adux1020_write_raw(struct iio_dev *indio_dev,
0452                   struct iio_chan_spec const *chan,
0453                   int val, int val2, long mask)
0454 {
0455     struct adux1020_data *data = iio_priv(indio_dev);
0456     int i, ret = -EINVAL;
0457 
0458     mutex_lock(&data->lock);
0459 
0460     switch (mask) {
0461     case IIO_CHAN_INFO_SAMP_FREQ:
0462         if (chan->type == IIO_PROXIMITY) {
0463             i = adux1020_find_index(adux1020_rates,
0464                         ARRAY_SIZE(adux1020_rates),
0465                         val, val2);
0466             if (i < 0) {
0467                 ret = i;
0468                 goto fail;
0469             }
0470 
0471             ret = regmap_update_bits(data->regmap,
0472                          ADUX1020_REG_FREQUENCY,
0473                          ADUX1020_PROX_FREQ_MASK,
0474                          ADUX1020_PROX_FREQ(i));
0475         }
0476         break;
0477     case IIO_CHAN_INFO_PROCESSED:
0478         if (chan->type == IIO_CURRENT) {
0479             i = adux1020_find_index(adux1020_led_currents,
0480                     ARRAY_SIZE(adux1020_led_currents),
0481                     val, val2);
0482             if (i < 0) {
0483                 ret = i;
0484                 goto fail;
0485             }
0486 
0487             ret = regmap_update_bits(data->regmap,
0488                          ADUX1020_REG_LED_CURRENT,
0489                          ADUX1020_LED_CURRENT_MASK, i);
0490         }
0491         break;
0492     default:
0493         break;
0494     }
0495 
0496 fail:
0497     mutex_unlock(&data->lock);
0498 
0499     return ret;
0500 }
0501 
0502 static int adux1020_write_event_config(struct iio_dev *indio_dev,
0503                        const struct iio_chan_spec *chan,
0504                        enum iio_event_type type,
0505                        enum iio_event_direction dir, int state)
0506 {
0507     struct adux1020_data *data = iio_priv(indio_dev);
0508     int ret, mask;
0509 
0510     mutex_lock(&data->lock);
0511 
0512     ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
0513                ADUX1020_INT_ENABLE);
0514     if (ret < 0)
0515         goto fail;
0516 
0517     ret = regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0);
0518     if (ret < 0)
0519         goto fail;
0520 
0521     switch (chan->type) {
0522     case IIO_PROXIMITY:
0523         if (dir == IIO_EV_DIR_RISING)
0524             mask = ADUX1020_PROX_ON1_INT;
0525         else
0526             mask = ADUX1020_PROX_OFF1_INT;
0527 
0528         if (state)
0529             state = 0;
0530         else
0531             state = mask;
0532 
0533         ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
0534                      mask, state);
0535         if (ret < 0)
0536             goto fail;
0537 
0538         /*
0539          * Trigger proximity interrupt when the intensity is above
0540          * or below threshold
0541          */
0542         ret = regmap_update_bits(data->regmap, ADUX1020_REG_PROX_TYPE,
0543                      ADUX1020_PROX_TYPE,
0544                      ADUX1020_PROX_TYPE);
0545         if (ret < 0)
0546             goto fail;
0547 
0548         /* Set proximity mode */
0549         ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
0550         break;
0551     default:
0552         ret = -EINVAL;
0553         break;
0554     }
0555 
0556 fail:
0557     mutex_unlock(&data->lock);
0558 
0559     return ret;
0560 }
0561 
0562 static int adux1020_read_event_config(struct iio_dev *indio_dev,
0563                       const struct iio_chan_spec *chan,
0564                       enum iio_event_type type,
0565                       enum iio_event_direction dir)
0566 {
0567     struct adux1020_data *data = iio_priv(indio_dev);
0568     int ret, mask;
0569     unsigned int regval;
0570 
0571     switch (chan->type) {
0572     case IIO_PROXIMITY:
0573         if (dir == IIO_EV_DIR_RISING)
0574             mask = ADUX1020_PROX_ON1_INT;
0575         else
0576             mask = ADUX1020_PROX_OFF1_INT;
0577         break;
0578     default:
0579         return -EINVAL;
0580     }
0581 
0582     ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, &regval);
0583     if (ret < 0)
0584         return ret;
0585 
0586     return !(regval & mask);
0587 }
0588 
0589 static int adux1020_read_thresh(struct iio_dev *indio_dev,
0590                 const struct iio_chan_spec *chan,
0591                 enum iio_event_type type,
0592                 enum iio_event_direction dir,
0593                 enum iio_event_info info, int *val, int *val2)
0594 {
0595     struct adux1020_data *data = iio_priv(indio_dev);
0596     u8 reg;
0597     int ret;
0598     unsigned int regval;
0599 
0600     switch (chan->type) {
0601     case IIO_PROXIMITY:
0602         if (dir == IIO_EV_DIR_RISING)
0603             reg = ADUX1020_REG_PROX_TH_ON1;
0604         else
0605             reg = ADUX1020_REG_PROX_TH_OFF1;
0606         break;
0607     default:
0608         return -EINVAL;
0609     }
0610 
0611     ret = regmap_read(data->regmap, reg, &regval);
0612     if (ret < 0)
0613         return ret;
0614 
0615     *val = regval;
0616 
0617     return IIO_VAL_INT;
0618 }
0619 
0620 static int adux1020_write_thresh(struct iio_dev *indio_dev,
0621                  const struct iio_chan_spec *chan,
0622                  enum iio_event_type type,
0623                  enum iio_event_direction dir,
0624                  enum iio_event_info info, int val, int val2)
0625 {
0626     struct adux1020_data *data = iio_priv(indio_dev);
0627     u8 reg;
0628 
0629     switch (chan->type) {
0630     case IIO_PROXIMITY:
0631         if (dir == IIO_EV_DIR_RISING)
0632             reg = ADUX1020_REG_PROX_TH_ON1;
0633         else
0634             reg = ADUX1020_REG_PROX_TH_OFF1;
0635         break;
0636     default:
0637         return -EINVAL;
0638     }
0639 
0640     /* Full scale threshold value is 0-65535  */
0641     if (val < 0 || val > 65535)
0642         return -EINVAL;
0643 
0644     return regmap_write(data->regmap, reg, val);
0645 }
0646 
0647 static const struct iio_event_spec adux1020_proximity_event[] = {
0648     {
0649         .type = IIO_EV_TYPE_THRESH,
0650         .dir = IIO_EV_DIR_RISING,
0651         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0652             BIT(IIO_EV_INFO_ENABLE),
0653     },
0654     {
0655         .type = IIO_EV_TYPE_THRESH,
0656         .dir = IIO_EV_DIR_FALLING,
0657         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0658             BIT(IIO_EV_INFO_ENABLE),
0659     },
0660 };
0661 
0662 static const struct iio_chan_spec adux1020_channels[] = {
0663     {
0664         .type = IIO_PROXIMITY,
0665         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0666                       BIT(IIO_CHAN_INFO_SAMP_FREQ),
0667         .event_spec = adux1020_proximity_event,
0668         .num_event_specs = ARRAY_SIZE(adux1020_proximity_event),
0669     },
0670     {
0671         .type = IIO_CURRENT,
0672         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
0673         .extend_name = "led",
0674         .output = 1,
0675     },
0676 };
0677 
0678 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
0679               "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
0680 
0681 static struct attribute *adux1020_attributes[] = {
0682     &iio_const_attr_sampling_frequency_available.dev_attr.attr,
0683     NULL
0684 };
0685 
0686 static const struct attribute_group adux1020_attribute_group = {
0687     .attrs = adux1020_attributes,
0688 };
0689 
0690 static const struct iio_info adux1020_info = {
0691     .attrs = &adux1020_attribute_group,
0692     .read_raw = adux1020_read_raw,
0693     .write_raw = adux1020_write_raw,
0694     .read_event_config = adux1020_read_event_config,
0695     .write_event_config = adux1020_write_event_config,
0696     .read_event_value = adux1020_read_thresh,
0697     .write_event_value = adux1020_write_thresh,
0698 };
0699 
0700 static irqreturn_t adux1020_interrupt_handler(int irq, void *private)
0701 {
0702     struct iio_dev *indio_dev = private;
0703     struct adux1020_data *data = iio_priv(indio_dev);
0704     int ret, status;
0705 
0706     ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status);
0707     if (ret < 0)
0708         return IRQ_HANDLED;
0709 
0710     status &= ADUX1020_MODE_INT_STATUS_MASK;
0711 
0712     if (status & ADUX1020_INT_PROX_ON1) {
0713         iio_push_event(indio_dev,
0714                    IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
0715                             IIO_EV_TYPE_THRESH,
0716                             IIO_EV_DIR_RISING),
0717                    iio_get_time_ns(indio_dev));
0718     }
0719 
0720     if (status & ADUX1020_INT_PROX_OFF1) {
0721         iio_push_event(indio_dev,
0722                    IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
0723                             IIO_EV_TYPE_THRESH,
0724                             IIO_EV_DIR_FALLING),
0725                    iio_get_time_ns(indio_dev));
0726     }
0727 
0728     regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS,
0729                ADUX1020_MODE_INT_MASK, ADUX1020_INT_CLEAR);
0730 
0731     return IRQ_HANDLED;
0732 }
0733 
0734 static int adux1020_chip_init(struct adux1020_data *data)
0735 {
0736     struct i2c_client *client = data->client;
0737     int ret;
0738     unsigned int val;
0739 
0740     ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val);
0741     if (ret < 0)
0742         return ret;
0743 
0744     if ((val & ADUX1020_CHIP_ID_MASK) != ADUX1020_CHIP_ID) {
0745         dev_err(&client->dev, "invalid chip id 0x%04x\n", val);
0746         return -ENODEV;
0747     }
0748 
0749     dev_dbg(&client->dev, "Detected ADUX1020 with chip id: 0x%04x\n", val);
0750 
0751     ret = regmap_update_bits(data->regmap, ADUX1020_REG_SW_RESET,
0752                  ADUX1020_SW_RESET, ADUX1020_SW_RESET);
0753     if (ret < 0)
0754         return ret;
0755 
0756     /* Load default configuration */
0757     ret = regmap_multi_reg_write(data->regmap, adux1020_def_conf,
0758                      ARRAY_SIZE(adux1020_def_conf));
0759     if (ret < 0)
0760         return ret;
0761 
0762     ret = adux1020_flush_fifo(data);
0763     if (ret < 0)
0764         return ret;
0765 
0766     /* Use LED_IREF for proximity mode */
0767     ret = regmap_update_bits(data->regmap, ADUX1020_REG_LED_CURRENT,
0768                  ADUX1020_LED_PIREF_EN, 0);
0769     if (ret < 0)
0770         return ret;
0771 
0772     /* Mask all interrupts */
0773     return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
0774                ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE);
0775 }
0776 
0777 static int adux1020_probe(struct i2c_client *client,
0778               const struct i2c_device_id *id)
0779 {
0780     struct adux1020_data *data;
0781     struct iio_dev *indio_dev;
0782     int ret;
0783 
0784     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0785     if (!indio_dev)
0786         return -ENOMEM;
0787 
0788     indio_dev->info = &adux1020_info;
0789     indio_dev->name = ADUX1020_DRV_NAME;
0790     indio_dev->channels = adux1020_channels;
0791     indio_dev->num_channels = ARRAY_SIZE(adux1020_channels);
0792     indio_dev->modes = INDIO_DIRECT_MODE;
0793 
0794     data = iio_priv(indio_dev);
0795 
0796     data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config);
0797     if (IS_ERR(data->regmap)) {
0798         dev_err(&client->dev, "regmap initialization failed.\n");
0799         return PTR_ERR(data->regmap);
0800     }
0801 
0802     data->client = client;
0803     data->indio_dev = indio_dev;
0804     mutex_init(&data->lock);
0805 
0806     ret = adux1020_chip_init(data);
0807     if (ret)
0808         return ret;
0809 
0810     if (client->irq) {
0811         ret = devm_request_threaded_irq(&client->dev, client->irq,
0812                     NULL, adux1020_interrupt_handler,
0813                     IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
0814                     ADUX1020_DRV_NAME, indio_dev);
0815         if (ret) {
0816             dev_err(&client->dev, "irq request error %d\n", -ret);
0817             return ret;
0818         }
0819     }
0820 
0821     return devm_iio_device_register(&client->dev, indio_dev);
0822 }
0823 
0824 static const struct i2c_device_id adux1020_id[] = {
0825     { "adux1020", 0 },
0826     {}
0827 };
0828 MODULE_DEVICE_TABLE(i2c, adux1020_id);
0829 
0830 static const struct of_device_id adux1020_of_match[] = {
0831     { .compatible = "adi,adux1020" },
0832     { }
0833 };
0834 MODULE_DEVICE_TABLE(of, adux1020_of_match);
0835 
0836 static struct i2c_driver adux1020_driver = {
0837     .driver = {
0838         .name   = ADUX1020_DRV_NAME,
0839         .of_match_table = adux1020_of_match,
0840     },
0841     .probe      = adux1020_probe,
0842     .id_table   = adux1020_id,
0843 };
0844 module_i2c_driver(adux1020_driver);
0845 
0846 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
0847 MODULE_DESCRIPTION("ADUX1020 photometric sensor");
0848 MODULE_LICENSE("GPL");
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