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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADIS16480 and similar IMUs driver
0004  *
0005  * Copyright 2012 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/bitfield.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/irq.h>
0012 #include <linux/math.h>
0013 #include <linux/device.h>
0014 #include <linux/kernel.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/mod_devicetable.h>
0017 #include <linux/module.h>
0018 #include <linux/lcm.h>
0019 #include <linux/property.h>
0020 #include <linux/swab.h>
0021 #include <linux/crc32.h>
0022 
0023 #include <linux/iio/iio.h>
0024 #include <linux/iio/buffer.h>
0025 #include <linux/iio/imu/adis.h>
0026 #include <linux/iio/trigger_consumer.h>
0027 
0028 #include <linux/debugfs.h>
0029 
0030 #define ADIS16480_PAGE_SIZE 0x80
0031 
0032 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
0033 
0034 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */
0035 #define ADIS16480_REG_SEQ_CNT           ADIS16480_REG(0x00, 0x06)
0036 #define ADIS16480_REG_SYS_E_FLA         ADIS16480_REG(0x00, 0x08)
0037 #define ADIS16480_REG_DIAG_STS          ADIS16480_REG(0x00, 0x0A)
0038 #define ADIS16480_REG_ALM_STS           ADIS16480_REG(0x00, 0x0C)
0039 #define ADIS16480_REG_TEMP_OUT          ADIS16480_REG(0x00, 0x0E)
0040 #define ADIS16480_REG_X_GYRO_OUT        ADIS16480_REG(0x00, 0x10)
0041 #define ADIS16480_REG_Y_GYRO_OUT        ADIS16480_REG(0x00, 0x14)
0042 #define ADIS16480_REG_Z_GYRO_OUT        ADIS16480_REG(0x00, 0x18)
0043 #define ADIS16480_REG_X_ACCEL_OUT       ADIS16480_REG(0x00, 0x1C)
0044 #define ADIS16480_REG_Y_ACCEL_OUT       ADIS16480_REG(0x00, 0x20)
0045 #define ADIS16480_REG_Z_ACCEL_OUT       ADIS16480_REG(0x00, 0x24)
0046 #define ADIS16480_REG_X_MAGN_OUT        ADIS16480_REG(0x00, 0x28)
0047 #define ADIS16480_REG_Y_MAGN_OUT        ADIS16480_REG(0x00, 0x2A)
0048 #define ADIS16480_REG_Z_MAGN_OUT        ADIS16480_REG(0x00, 0x2C)
0049 #define ADIS16480_REG_BAROM_OUT         ADIS16480_REG(0x00, 0x2E)
0050 #define ADIS16480_REG_X_DELTAANG_OUT        ADIS16480_REG(0x00, 0x40)
0051 #define ADIS16480_REG_Y_DELTAANG_OUT        ADIS16480_REG(0x00, 0x44)
0052 #define ADIS16480_REG_Z_DELTAANG_OUT        ADIS16480_REG(0x00, 0x48)
0053 #define ADIS16480_REG_X_DELTAVEL_OUT        ADIS16480_REG(0x00, 0x4C)
0054 #define ADIS16480_REG_Y_DELTAVEL_OUT        ADIS16480_REG(0x00, 0x50)
0055 #define ADIS16480_REG_Z_DELTAVEL_OUT        ADIS16480_REG(0x00, 0x54)
0056 #define ADIS16480_REG_PROD_ID           ADIS16480_REG(0x00, 0x7E)
0057 
0058 #define ADIS16480_REG_X_GYRO_SCALE      ADIS16480_REG(0x02, 0x04)
0059 #define ADIS16480_REG_Y_GYRO_SCALE      ADIS16480_REG(0x02, 0x06)
0060 #define ADIS16480_REG_Z_GYRO_SCALE      ADIS16480_REG(0x02, 0x08)
0061 #define ADIS16480_REG_X_ACCEL_SCALE     ADIS16480_REG(0x02, 0x0A)
0062 #define ADIS16480_REG_Y_ACCEL_SCALE     ADIS16480_REG(0x02, 0x0C)
0063 #define ADIS16480_REG_Z_ACCEL_SCALE     ADIS16480_REG(0x02, 0x0E)
0064 #define ADIS16480_REG_X_GYRO_BIAS       ADIS16480_REG(0x02, 0x10)
0065 #define ADIS16480_REG_Y_GYRO_BIAS       ADIS16480_REG(0x02, 0x14)
0066 #define ADIS16480_REG_Z_GYRO_BIAS       ADIS16480_REG(0x02, 0x18)
0067 #define ADIS16480_REG_X_ACCEL_BIAS      ADIS16480_REG(0x02, 0x1C)
0068 #define ADIS16480_REG_Y_ACCEL_BIAS      ADIS16480_REG(0x02, 0x20)
0069 #define ADIS16480_REG_Z_ACCEL_BIAS      ADIS16480_REG(0x02, 0x24)
0070 #define ADIS16480_REG_X_HARD_IRON       ADIS16480_REG(0x02, 0x28)
0071 #define ADIS16480_REG_Y_HARD_IRON       ADIS16480_REG(0x02, 0x2A)
0072 #define ADIS16480_REG_Z_HARD_IRON       ADIS16480_REG(0x02, 0x2C)
0073 #define ADIS16480_REG_BAROM_BIAS        ADIS16480_REG(0x02, 0x40)
0074 #define ADIS16480_REG_FLASH_CNT         ADIS16480_REG(0x02, 0x7C)
0075 
0076 #define ADIS16480_REG_GLOB_CMD          ADIS16480_REG(0x03, 0x02)
0077 #define ADIS16480_REG_FNCTIO_CTRL       ADIS16480_REG(0x03, 0x06)
0078 #define ADIS16480_REG_GPIO_CTRL         ADIS16480_REG(0x03, 0x08)
0079 #define ADIS16480_REG_CONFIG            ADIS16480_REG(0x03, 0x0A)
0080 #define ADIS16480_REG_DEC_RATE          ADIS16480_REG(0x03, 0x0C)
0081 #define ADIS16480_REG_SLP_CNT           ADIS16480_REG(0x03, 0x10)
0082 #define ADIS16480_REG_FILTER_BNK0       ADIS16480_REG(0x03, 0x16)
0083 #define ADIS16480_REG_FILTER_BNK1       ADIS16480_REG(0x03, 0x18)
0084 #define ADIS16480_REG_ALM_CNFG0         ADIS16480_REG(0x03, 0x20)
0085 #define ADIS16480_REG_ALM_CNFG1         ADIS16480_REG(0x03, 0x22)
0086 #define ADIS16480_REG_ALM_CNFG2         ADIS16480_REG(0x03, 0x24)
0087 #define ADIS16480_REG_XG_ALM_MAGN       ADIS16480_REG(0x03, 0x28)
0088 #define ADIS16480_REG_YG_ALM_MAGN       ADIS16480_REG(0x03, 0x2A)
0089 #define ADIS16480_REG_ZG_ALM_MAGN       ADIS16480_REG(0x03, 0x2C)
0090 #define ADIS16480_REG_XA_ALM_MAGN       ADIS16480_REG(0x03, 0x2E)
0091 #define ADIS16480_REG_YA_ALM_MAGN       ADIS16480_REG(0x03, 0x30)
0092 #define ADIS16480_REG_ZA_ALM_MAGN       ADIS16480_REG(0x03, 0x32)
0093 #define ADIS16480_REG_XM_ALM_MAGN       ADIS16480_REG(0x03, 0x34)
0094 #define ADIS16480_REG_YM_ALM_MAGN       ADIS16480_REG(0x03, 0x36)
0095 #define ADIS16480_REG_ZM_ALM_MAGN       ADIS16480_REG(0x03, 0x38)
0096 #define ADIS16480_REG_BR_ALM_MAGN       ADIS16480_REG(0x03, 0x3A)
0097 #define ADIS16480_REG_FIRM_REV          ADIS16480_REG(0x03, 0x78)
0098 #define ADIS16480_REG_FIRM_DM           ADIS16480_REG(0x03, 0x7A)
0099 #define ADIS16480_REG_FIRM_Y            ADIS16480_REG(0x03, 0x7C)
0100 
0101 /*
0102  * External clock scaling in PPS mode.
0103  * Available only for ADIS1649x devices
0104  */
0105 #define ADIS16495_REG_SYNC_SCALE        ADIS16480_REG(0x03, 0x10)
0106 #define ADIS16495_REG_BURST_CMD         ADIS16480_REG(0x00, 0x7C)
0107 #define ADIS16495_BURST_ID          0xA5A5
0108 /* total number of segments in burst */
0109 #define ADIS16495_BURST_MAX_DATA        20
0110 /* spi max speed in burst mode */
0111 #define ADIS16495_BURST_MAX_SPEED              6000000
0112 
0113 #define ADIS16480_REG_SERIAL_NUM        ADIS16480_REG(0x04, 0x20)
0114 
0115 /* Each filter coefficent bank spans two pages */
0116 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
0117         ADIS16480_REG((page) + 1, (x) - 60 + 8))
0118 #define ADIS16480_FIR_COEF_A(x)         ADIS16480_FIR_COEF(0x05, (x))
0119 #define ADIS16480_FIR_COEF_B(x)         ADIS16480_FIR_COEF(0x07, (x))
0120 #define ADIS16480_FIR_COEF_C(x)         ADIS16480_FIR_COEF(0x09, (x))
0121 #define ADIS16480_FIR_COEF_D(x)         ADIS16480_FIR_COEF(0x0B, (x))
0122 
0123 /* ADIS16480_REG_FNCTIO_CTRL */
0124 #define ADIS16480_DRDY_SEL_MSK      GENMASK(1, 0)
0125 #define ADIS16480_DRDY_SEL(x)       FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
0126 #define ADIS16480_DRDY_POL_MSK      BIT(2)
0127 #define ADIS16480_DRDY_POL(x)       FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
0128 #define ADIS16480_DRDY_EN_MSK       BIT(3)
0129 #define ADIS16480_DRDY_EN(x)        FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
0130 #define ADIS16480_SYNC_SEL_MSK      GENMASK(5, 4)
0131 #define ADIS16480_SYNC_SEL(x)       FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
0132 #define ADIS16480_SYNC_EN_MSK       BIT(7)
0133 #define ADIS16480_SYNC_EN(x)        FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
0134 #define ADIS16480_SYNC_MODE_MSK     BIT(8)
0135 #define ADIS16480_SYNC_MODE(x)      FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
0136 
0137 struct adis16480_chip_info {
0138     unsigned int num_channels;
0139     const struct iio_chan_spec *channels;
0140     unsigned int gyro_max_val;
0141     unsigned int gyro_max_scale;
0142     unsigned int accel_max_val;
0143     unsigned int accel_max_scale;
0144     unsigned int temp_scale;
0145     unsigned int int_clk;
0146     unsigned int max_dec_rate;
0147     const unsigned int *filter_freqs;
0148     bool has_pps_clk_mode;
0149     bool has_sleep_cnt;
0150     const struct adis_data adis_data;
0151 };
0152 
0153 enum adis16480_int_pin {
0154     ADIS16480_PIN_DIO1,
0155     ADIS16480_PIN_DIO2,
0156     ADIS16480_PIN_DIO3,
0157     ADIS16480_PIN_DIO4
0158 };
0159 
0160 enum adis16480_clock_mode {
0161     ADIS16480_CLK_SYNC,
0162     ADIS16480_CLK_PPS,
0163     ADIS16480_CLK_INT
0164 };
0165 
0166 struct adis16480 {
0167     const struct adis16480_chip_info *chip_info;
0168 
0169     struct adis adis;
0170     struct clk *ext_clk;
0171     enum adis16480_clock_mode clk_mode;
0172     unsigned int clk_freq;
0173     /* Alignment needed for the timestamp */
0174     __be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8);
0175 };
0176 
0177 static const char * const adis16480_int_pin_names[4] = {
0178     [ADIS16480_PIN_DIO1] = "DIO1",
0179     [ADIS16480_PIN_DIO2] = "DIO2",
0180     [ADIS16480_PIN_DIO3] = "DIO3",
0181     [ADIS16480_PIN_DIO4] = "DIO4",
0182 };
0183 
0184 static bool low_rate_allow;
0185 module_param(low_rate_allow, bool, 0444);
0186 MODULE_PARM_DESC(low_rate_allow,
0187          "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)");
0188 
0189 #ifdef CONFIG_DEBUG_FS
0190 
0191 static ssize_t adis16480_show_firmware_revision(struct file *file,
0192         char __user *userbuf, size_t count, loff_t *ppos)
0193 {
0194     struct adis16480 *adis16480 = file->private_data;
0195     char buf[7];
0196     size_t len;
0197     u16 rev;
0198     int ret;
0199 
0200     ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
0201     if (ret)
0202         return ret;
0203 
0204     len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
0205 
0206     return simple_read_from_buffer(userbuf, count, ppos, buf, len);
0207 }
0208 
0209 static const struct file_operations adis16480_firmware_revision_fops = {
0210     .open = simple_open,
0211     .read = adis16480_show_firmware_revision,
0212     .llseek = default_llseek,
0213     .owner = THIS_MODULE,
0214 };
0215 
0216 static ssize_t adis16480_show_firmware_date(struct file *file,
0217         char __user *userbuf, size_t count, loff_t *ppos)
0218 {
0219     struct adis16480 *adis16480 = file->private_data;
0220     u16 md, year;
0221     char buf[12];
0222     size_t len;
0223     int ret;
0224 
0225     ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
0226     if (ret)
0227         return ret;
0228 
0229     ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
0230     if (ret)
0231         return ret;
0232 
0233     len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
0234             md >> 8, md & 0xff, year);
0235 
0236     return simple_read_from_buffer(userbuf, count, ppos, buf, len);
0237 }
0238 
0239 static const struct file_operations adis16480_firmware_date_fops = {
0240     .open = simple_open,
0241     .read = adis16480_show_firmware_date,
0242     .llseek = default_llseek,
0243     .owner = THIS_MODULE,
0244 };
0245 
0246 static int adis16480_show_serial_number(void *arg, u64 *val)
0247 {
0248     struct adis16480 *adis16480 = arg;
0249     u16 serial;
0250     int ret;
0251 
0252     ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
0253         &serial);
0254     if (ret)
0255         return ret;
0256 
0257     *val = serial;
0258 
0259     return 0;
0260 }
0261 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
0262     adis16480_show_serial_number, NULL, "0x%.4llx\n");
0263 
0264 static int adis16480_show_product_id(void *arg, u64 *val)
0265 {
0266     struct adis16480 *adis16480 = arg;
0267     u16 prod_id;
0268     int ret;
0269 
0270     ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
0271         &prod_id);
0272     if (ret)
0273         return ret;
0274 
0275     *val = prod_id;
0276 
0277     return 0;
0278 }
0279 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
0280     adis16480_show_product_id, NULL, "%llu\n");
0281 
0282 static int adis16480_show_flash_count(void *arg, u64 *val)
0283 {
0284     struct adis16480 *adis16480 = arg;
0285     u32 flash_count;
0286     int ret;
0287 
0288     ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
0289         &flash_count);
0290     if (ret)
0291         return ret;
0292 
0293     *val = flash_count;
0294 
0295     return 0;
0296 }
0297 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
0298     adis16480_show_flash_count, NULL, "%lld\n");
0299 
0300 static int adis16480_debugfs_init(struct iio_dev *indio_dev)
0301 {
0302     struct adis16480 *adis16480 = iio_priv(indio_dev);
0303     struct dentry *d = iio_get_debugfs_dentry(indio_dev);
0304 
0305     debugfs_create_file_unsafe("firmware_revision", 0400,
0306         d, adis16480, &adis16480_firmware_revision_fops);
0307     debugfs_create_file_unsafe("firmware_date", 0400,
0308         d, adis16480, &adis16480_firmware_date_fops);
0309     debugfs_create_file_unsafe("serial_number", 0400,
0310         d, adis16480, &adis16480_serial_number_fops);
0311     debugfs_create_file_unsafe("product_id", 0400,
0312         d, adis16480, &adis16480_product_id_fops);
0313     debugfs_create_file_unsafe("flash_count", 0400,
0314         d, adis16480, &adis16480_flash_count_fops);
0315 
0316     return 0;
0317 }
0318 
0319 #else
0320 
0321 static int adis16480_debugfs_init(struct iio_dev *indio_dev)
0322 {
0323     return 0;
0324 }
0325 
0326 #endif
0327 
0328 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
0329 {
0330     struct adis16480 *st = iio_priv(indio_dev);
0331     unsigned int t, sample_rate = st->clk_freq;
0332     int ret;
0333 
0334     if (val < 0 || val2 < 0)
0335         return -EINVAL;
0336 
0337     t =  val * 1000 + val2 / 1000;
0338     if (t == 0)
0339         return -EINVAL;
0340 
0341     adis_dev_lock(&st->adis);
0342     /*
0343      * When using PPS mode, the input clock needs to be scaled so that we have an IMU
0344      * sample rate between (optimally) 4000 and 4250. After this, we can use the
0345      * decimation filter to lower the sampling rate in order to get what the user wants.
0346      * Optimally, the user sample rate is a multiple of both the IMU sample rate and
0347      * the input clock. Hence, calculating the sync_scale dynamically gives us better
0348      * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
0349      *  1. lcm of the input clock and the desired output rate.
0350      *  2. get the highest multiple of the previous result lower than the adis max rate.
0351      *  3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
0352      *     and DEC_RATE (to get the user output rate)
0353      */
0354     if (st->clk_mode == ADIS16480_CLK_PPS) {
0355         unsigned long scaled_rate = lcm(st->clk_freq, t);
0356         int sync_scale;
0357 
0358         /*
0359          * If lcm is bigger than the IMU maximum sampling rate there's no perfect
0360          * solution. In this case, we get the highest multiple of the input clock
0361          * lower than the IMU max sample rate.
0362          */
0363         if (scaled_rate > st->chip_info->int_clk)
0364             scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq;
0365         else
0366             scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate;
0367 
0368         /*
0369          * This is not an hard requirement but it's not advised to run the IMU
0370          * with a sample rate lower than 4000Hz due to possible undersampling
0371          * issues. However, there are users that might really want to take the risk.
0372          * Hence, we provide a module parameter for them. If set, we allow sample
0373          * rates lower than 4KHz. By default, we won't allow this and we just roundup
0374          * the rate to the next multiple of the input clock bigger than 4KHz. This
0375          * is done like this as in some cases (when DEC_RATE is 0) might give
0376          * us the closest value to the one desired by the user...
0377          */
0378         if (scaled_rate < 4000000 && !low_rate_allow)
0379             scaled_rate = roundup(4000000, st->clk_freq);
0380 
0381         sync_scale = scaled_rate / st->clk_freq;
0382         ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
0383         if (ret)
0384             goto error;
0385 
0386         sample_rate = scaled_rate;
0387     }
0388 
0389     t = DIV_ROUND_CLOSEST(sample_rate, t);
0390     if (t)
0391         t--;
0392 
0393     if (t > st->chip_info->max_dec_rate)
0394         t = st->chip_info->max_dec_rate;
0395 
0396     ret = __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t);
0397 error:
0398     adis_dev_unlock(&st->adis);
0399     return ret;
0400 }
0401 
0402 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
0403 {
0404     struct adis16480 *st = iio_priv(indio_dev);
0405     uint16_t t;
0406     int ret;
0407     unsigned int freq, sample_rate = st->clk_freq;
0408 
0409     adis_dev_lock(&st->adis);
0410 
0411     if (st->clk_mode == ADIS16480_CLK_PPS) {
0412         u16 sync_scale;
0413 
0414         ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale);
0415         if (ret)
0416             goto error;
0417 
0418         sample_rate = st->clk_freq * sync_scale;
0419     }
0420 
0421     ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t);
0422     if (ret)
0423         goto error;
0424 
0425     adis_dev_unlock(&st->adis);
0426 
0427     freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1));
0428 
0429     *val = freq / 1000;
0430     *val2 = (freq % 1000) * 1000;
0431 
0432     return IIO_VAL_INT_PLUS_MICRO;
0433 error:
0434     adis_dev_unlock(&st->adis);
0435     return ret;
0436 }
0437 
0438 enum {
0439     ADIS16480_SCAN_GYRO_X,
0440     ADIS16480_SCAN_GYRO_Y,
0441     ADIS16480_SCAN_GYRO_Z,
0442     ADIS16480_SCAN_ACCEL_X,
0443     ADIS16480_SCAN_ACCEL_Y,
0444     ADIS16480_SCAN_ACCEL_Z,
0445     ADIS16480_SCAN_MAGN_X,
0446     ADIS16480_SCAN_MAGN_Y,
0447     ADIS16480_SCAN_MAGN_Z,
0448     ADIS16480_SCAN_BARO,
0449     ADIS16480_SCAN_TEMP,
0450 };
0451 
0452 static const unsigned int adis16480_calibbias_regs[] = {
0453     [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
0454     [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
0455     [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
0456     [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
0457     [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
0458     [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
0459     [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
0460     [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
0461     [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
0462     [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
0463 };
0464 
0465 static const unsigned int adis16480_calibscale_regs[] = {
0466     [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
0467     [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
0468     [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
0469     [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
0470     [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
0471     [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
0472 };
0473 
0474 static int adis16480_set_calibbias(struct iio_dev *indio_dev,
0475     const struct iio_chan_spec *chan, int bias)
0476 {
0477     unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
0478     struct adis16480 *st = iio_priv(indio_dev);
0479 
0480     switch (chan->type) {
0481     case IIO_MAGN:
0482     case IIO_PRESSURE:
0483         if (bias < -0x8000 || bias >= 0x8000)
0484             return -EINVAL;
0485         return adis_write_reg_16(&st->adis, reg, bias);
0486     case IIO_ANGL_VEL:
0487     case IIO_ACCEL:
0488         return adis_write_reg_32(&st->adis, reg, bias);
0489     default:
0490         break;
0491     }
0492 
0493     return -EINVAL;
0494 }
0495 
0496 static int adis16480_get_calibbias(struct iio_dev *indio_dev,
0497     const struct iio_chan_spec *chan, int *bias)
0498 {
0499     unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
0500     struct adis16480 *st = iio_priv(indio_dev);
0501     uint16_t val16;
0502     uint32_t val32;
0503     int ret;
0504 
0505     switch (chan->type) {
0506     case IIO_MAGN:
0507     case IIO_PRESSURE:
0508         ret = adis_read_reg_16(&st->adis, reg, &val16);
0509         if (ret == 0)
0510             *bias = sign_extend32(val16, 15);
0511         break;
0512     case IIO_ANGL_VEL:
0513     case IIO_ACCEL:
0514         ret = adis_read_reg_32(&st->adis, reg, &val32);
0515         if (ret == 0)
0516             *bias = sign_extend32(val32, 31);
0517         break;
0518     default:
0519         ret = -EINVAL;
0520     }
0521 
0522     if (ret)
0523         return ret;
0524 
0525     return IIO_VAL_INT;
0526 }
0527 
0528 static int adis16480_set_calibscale(struct iio_dev *indio_dev,
0529     const struct iio_chan_spec *chan, int scale)
0530 {
0531     unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
0532     struct adis16480 *st = iio_priv(indio_dev);
0533 
0534     if (scale < -0x8000 || scale >= 0x8000)
0535         return -EINVAL;
0536 
0537     return adis_write_reg_16(&st->adis, reg, scale);
0538 }
0539 
0540 static int adis16480_get_calibscale(struct iio_dev *indio_dev,
0541     const struct iio_chan_spec *chan, int *scale)
0542 {
0543     unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
0544     struct adis16480 *st = iio_priv(indio_dev);
0545     uint16_t val16;
0546     int ret;
0547 
0548     ret = adis_read_reg_16(&st->adis, reg, &val16);
0549     if (ret)
0550         return ret;
0551 
0552     *scale = sign_extend32(val16, 15);
0553     return IIO_VAL_INT;
0554 }
0555 
0556 static const unsigned int adis16480_def_filter_freqs[] = {
0557     310,
0558     55,
0559     275,
0560     63,
0561 };
0562 
0563 static const unsigned int adis16495_def_filter_freqs[] = {
0564     300,
0565     100,
0566     300,
0567     100,
0568 };
0569 
0570 static const unsigned int ad16480_filter_data[][2] = {
0571     [ADIS16480_SCAN_GYRO_X]     = { ADIS16480_REG_FILTER_BNK0, 0 },
0572     [ADIS16480_SCAN_GYRO_Y]     = { ADIS16480_REG_FILTER_BNK0, 3 },
0573     [ADIS16480_SCAN_GYRO_Z]     = { ADIS16480_REG_FILTER_BNK0, 6 },
0574     [ADIS16480_SCAN_ACCEL_X]    = { ADIS16480_REG_FILTER_BNK0, 9 },
0575     [ADIS16480_SCAN_ACCEL_Y]    = { ADIS16480_REG_FILTER_BNK0, 12 },
0576     [ADIS16480_SCAN_ACCEL_Z]    = { ADIS16480_REG_FILTER_BNK1, 0 },
0577     [ADIS16480_SCAN_MAGN_X]     = { ADIS16480_REG_FILTER_BNK1, 3 },
0578     [ADIS16480_SCAN_MAGN_Y]     = { ADIS16480_REG_FILTER_BNK1, 6 },
0579     [ADIS16480_SCAN_MAGN_Z]     = { ADIS16480_REG_FILTER_BNK1, 9 },
0580 };
0581 
0582 static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
0583     const struct iio_chan_spec *chan, int *freq)
0584 {
0585     struct adis16480 *st = iio_priv(indio_dev);
0586     unsigned int enable_mask, offset, reg;
0587     uint16_t val;
0588     int ret;
0589 
0590     reg = ad16480_filter_data[chan->scan_index][0];
0591     offset = ad16480_filter_data[chan->scan_index][1];
0592     enable_mask = BIT(offset + 2);
0593 
0594     ret = adis_read_reg_16(&st->adis, reg, &val);
0595     if (ret)
0596         return ret;
0597 
0598     if (!(val & enable_mask))
0599         *freq = 0;
0600     else
0601         *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
0602 
0603     return IIO_VAL_INT;
0604 }
0605 
0606 static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
0607     const struct iio_chan_spec *chan, unsigned int freq)
0608 {
0609     struct adis16480 *st = iio_priv(indio_dev);
0610     unsigned int enable_mask, offset, reg;
0611     unsigned int diff, best_diff;
0612     unsigned int i, best_freq;
0613     uint16_t val;
0614     int ret;
0615 
0616     reg = ad16480_filter_data[chan->scan_index][0];
0617     offset = ad16480_filter_data[chan->scan_index][1];
0618     enable_mask = BIT(offset + 2);
0619 
0620     adis_dev_lock(&st->adis);
0621 
0622     ret = __adis_read_reg_16(&st->adis, reg, &val);
0623     if (ret)
0624         goto out_unlock;
0625 
0626     if (freq == 0) {
0627         val &= ~enable_mask;
0628     } else {
0629         best_freq = 0;
0630         best_diff = st->chip_info->filter_freqs[0];
0631         for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
0632             if (st->chip_info->filter_freqs[i] >= freq) {
0633                 diff = st->chip_info->filter_freqs[i] - freq;
0634                 if (diff < best_diff) {
0635                     best_diff = diff;
0636                     best_freq = i;
0637                 }
0638             }
0639         }
0640 
0641         val &= ~(0x3 << offset);
0642         val |= best_freq << offset;
0643         val |= enable_mask;
0644     }
0645 
0646     ret = __adis_write_reg_16(&st->adis, reg, val);
0647 out_unlock:
0648     adis_dev_unlock(&st->adis);
0649 
0650     return ret;
0651 }
0652 
0653 static int adis16480_read_raw(struct iio_dev *indio_dev,
0654     const struct iio_chan_spec *chan, int *val, int *val2, long info)
0655 {
0656     struct adis16480 *st = iio_priv(indio_dev);
0657     unsigned int temp;
0658 
0659     switch (info) {
0660     case IIO_CHAN_INFO_RAW:
0661         return adis_single_conversion(indio_dev, chan, 0, val);
0662     case IIO_CHAN_INFO_SCALE:
0663         switch (chan->type) {
0664         case IIO_ANGL_VEL:
0665             *val = st->chip_info->gyro_max_scale;
0666             *val2 = st->chip_info->gyro_max_val;
0667             return IIO_VAL_FRACTIONAL;
0668         case IIO_ACCEL:
0669             *val = st->chip_info->accel_max_scale;
0670             *val2 = st->chip_info->accel_max_val;
0671             return IIO_VAL_FRACTIONAL;
0672         case IIO_MAGN:
0673             *val = 0;
0674             *val2 = 100; /* 0.0001 gauss */
0675             return IIO_VAL_INT_PLUS_MICRO;
0676         case IIO_TEMP:
0677             /*
0678              * +85 degrees Celsius = temp_max_scale
0679              * +25 degrees Celsius = 0
0680              * LSB, 25 degrees Celsius  = 60 / temp_max_scale
0681              */
0682             *val = st->chip_info->temp_scale / 1000;
0683             *val2 = (st->chip_info->temp_scale % 1000) * 1000;
0684             return IIO_VAL_INT_PLUS_MICRO;
0685         case IIO_PRESSURE:
0686             /*
0687              * max scale is 1310 mbar
0688              * max raw value is 32767 shifted for 32bits
0689              */
0690             *val = 131; /* 1310mbar = 131 kPa */
0691             *val2 = 32767 << 16;
0692             return IIO_VAL_FRACTIONAL;
0693         default:
0694             return -EINVAL;
0695         }
0696     case IIO_CHAN_INFO_OFFSET:
0697         /* Only the temperature channel has a offset */
0698         temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */
0699         *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
0700         return IIO_VAL_INT;
0701     case IIO_CHAN_INFO_CALIBBIAS:
0702         return adis16480_get_calibbias(indio_dev, chan, val);
0703     case IIO_CHAN_INFO_CALIBSCALE:
0704         return adis16480_get_calibscale(indio_dev, chan, val);
0705     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0706         return adis16480_get_filter_freq(indio_dev, chan, val);
0707     case IIO_CHAN_INFO_SAMP_FREQ:
0708         return adis16480_get_freq(indio_dev, val, val2);
0709     default:
0710         return -EINVAL;
0711     }
0712 }
0713 
0714 static int adis16480_write_raw(struct iio_dev *indio_dev,
0715     const struct iio_chan_spec *chan, int val, int val2, long info)
0716 {
0717     switch (info) {
0718     case IIO_CHAN_INFO_CALIBBIAS:
0719         return adis16480_set_calibbias(indio_dev, chan, val);
0720     case IIO_CHAN_INFO_CALIBSCALE:
0721         return adis16480_set_calibscale(indio_dev, chan, val);
0722     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0723         return adis16480_set_filter_freq(indio_dev, chan, val);
0724     case IIO_CHAN_INFO_SAMP_FREQ:
0725         return adis16480_set_freq(indio_dev, val, val2);
0726 
0727     default:
0728         return -EINVAL;
0729     }
0730 }
0731 
0732 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
0733     { \
0734         .type = (_type), \
0735         .modified = 1, \
0736         .channel2 = (_mod), \
0737         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0738             BIT(IIO_CHAN_INFO_CALIBBIAS) | \
0739             _info_sep, \
0740         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
0741         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
0742         .address = (_address), \
0743         .scan_index = (_si), \
0744         .scan_type = { \
0745             .sign = 's', \
0746             .realbits = (_bits), \
0747             .storagebits = (_bits), \
0748             .endianness = IIO_BE, \
0749         }, \
0750     }
0751 
0752 #define ADIS16480_GYRO_CHANNEL(_mod) \
0753     ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
0754     ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
0755     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
0756     BIT(IIO_CHAN_INFO_CALIBSCALE), \
0757     32)
0758 
0759 #define ADIS16480_ACCEL_CHANNEL(_mod) \
0760     ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
0761     ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
0762     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
0763     BIT(IIO_CHAN_INFO_CALIBSCALE), \
0764     32)
0765 
0766 #define ADIS16480_MAGN_CHANNEL(_mod) \
0767     ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
0768     ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
0769     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
0770     16)
0771 
0772 #define ADIS16480_PRESSURE_CHANNEL() \
0773     { \
0774         .type = IIO_PRESSURE, \
0775         .indexed = 1, \
0776         .channel = 0, \
0777         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0778             BIT(IIO_CHAN_INFO_CALIBBIAS) | \
0779             BIT(IIO_CHAN_INFO_SCALE), \
0780         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
0781         .address = ADIS16480_REG_BAROM_OUT, \
0782         .scan_index = ADIS16480_SCAN_BARO, \
0783         .scan_type = { \
0784             .sign = 's', \
0785             .realbits = 32, \
0786             .storagebits = 32, \
0787             .endianness = IIO_BE, \
0788         }, \
0789     }
0790 
0791 #define ADIS16480_TEMP_CHANNEL() { \
0792         .type = IIO_TEMP, \
0793         .indexed = 1, \
0794         .channel = 0, \
0795         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0796             BIT(IIO_CHAN_INFO_SCALE) | \
0797             BIT(IIO_CHAN_INFO_OFFSET), \
0798         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
0799         .address = ADIS16480_REG_TEMP_OUT, \
0800         .scan_index = ADIS16480_SCAN_TEMP, \
0801         .scan_type = { \
0802             .sign = 's', \
0803             .realbits = 16, \
0804             .storagebits = 16, \
0805             .endianness = IIO_BE, \
0806         }, \
0807     }
0808 
0809 static const struct iio_chan_spec adis16480_channels[] = {
0810     ADIS16480_GYRO_CHANNEL(X),
0811     ADIS16480_GYRO_CHANNEL(Y),
0812     ADIS16480_GYRO_CHANNEL(Z),
0813     ADIS16480_ACCEL_CHANNEL(X),
0814     ADIS16480_ACCEL_CHANNEL(Y),
0815     ADIS16480_ACCEL_CHANNEL(Z),
0816     ADIS16480_MAGN_CHANNEL(X),
0817     ADIS16480_MAGN_CHANNEL(Y),
0818     ADIS16480_MAGN_CHANNEL(Z),
0819     ADIS16480_PRESSURE_CHANNEL(),
0820     ADIS16480_TEMP_CHANNEL(),
0821     IIO_CHAN_SOFT_TIMESTAMP(11)
0822 };
0823 
0824 static const struct iio_chan_spec adis16485_channels[] = {
0825     ADIS16480_GYRO_CHANNEL(X),
0826     ADIS16480_GYRO_CHANNEL(Y),
0827     ADIS16480_GYRO_CHANNEL(Z),
0828     ADIS16480_ACCEL_CHANNEL(X),
0829     ADIS16480_ACCEL_CHANNEL(Y),
0830     ADIS16480_ACCEL_CHANNEL(Z),
0831     ADIS16480_TEMP_CHANNEL(),
0832     IIO_CHAN_SOFT_TIMESTAMP(7)
0833 };
0834 
0835 enum adis16480_variant {
0836     ADIS16375,
0837     ADIS16480,
0838     ADIS16485,
0839     ADIS16488,
0840     ADIS16490,
0841     ADIS16495_1,
0842     ADIS16495_2,
0843     ADIS16495_3,
0844     ADIS16497_1,
0845     ADIS16497_2,
0846     ADIS16497_3,
0847 };
0848 
0849 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
0850 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
0851 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
0852 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3
0853 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4
0854 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
0855 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
0856 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
0857 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
0858 #define ADIS16480_DIAG_STAT_BARO_FAIL 11
0859 
0860 static const char * const adis16480_status_error_msgs[] = {
0861     [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
0862     [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
0863     [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
0864     [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
0865     [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
0866     [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
0867     [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
0868     [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
0869     [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
0870     [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
0871 };
0872 
0873 static int adis16480_enable_irq(struct adis *adis, bool enable);
0874 
0875 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len)         \
0876 {                                   \
0877     .diag_stat_reg = ADIS16480_REG_DIAG_STS,            \
0878     .glob_cmd_reg = ADIS16480_REG_GLOB_CMD,             \
0879     .prod_id_reg = ADIS16480_REG_PROD_ID,               \
0880     .prod_id = (_prod_id),                      \
0881     .has_paging = true,                     \
0882     .read_delay = 5,                        \
0883     .write_delay = 5,                       \
0884     .self_test_mask = BIT(1),                   \
0885     .self_test_reg = ADIS16480_REG_GLOB_CMD,            \
0886     .status_error_msgs = adis16480_status_error_msgs,       \
0887     .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) |  \
0888         BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) |           \
0889         BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) |           \
0890         BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) |           \
0891         BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) |           \
0892         BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) |           \
0893         BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) |           \
0894         BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) |           \
0895         BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) |           \
0896         BIT(ADIS16480_DIAG_STAT_BARO_FAIL),         \
0897     .enable_irq = adis16480_enable_irq,             \
0898     .timeouts = (_timeouts),                    \
0899     .burst_reg_cmd = ADIS16495_REG_BURST_CMD,           \
0900     .burst_len = (_burst_len),                  \
0901     .burst_max_speed_hz = ADIS16495_BURST_MAX_SPEED         \
0902 }
0903 
0904 static const struct adis_timeout adis16485_timeouts = {
0905     .reset_ms = 560,
0906     .sw_reset_ms = 120,
0907     .self_test_ms = 12,
0908 };
0909 
0910 static const struct adis_timeout adis16480_timeouts = {
0911     .reset_ms = 560,
0912     .sw_reset_ms = 560,
0913     .self_test_ms = 12,
0914 };
0915 
0916 static const struct adis_timeout adis16495_timeouts = {
0917     .reset_ms = 170,
0918     .sw_reset_ms = 130,
0919     .self_test_ms = 40,
0920 };
0921 
0922 static const struct adis_timeout adis16495_1_timeouts = {
0923     .reset_ms = 250,
0924     .sw_reset_ms = 210,
0925     .self_test_ms = 20,
0926 };
0927 
0928 static const struct adis16480_chip_info adis16480_chip_info[] = {
0929     [ADIS16375] = {
0930         .channels = adis16485_channels,
0931         .num_channels = ARRAY_SIZE(adis16485_channels),
0932         /*
0933          * Typically we do IIO_RAD_TO_DEGREE in the denominator, which
0934          * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since
0935          * it gives better approximation. However, in this case we
0936          * cannot do it since it would not fit in a 32bit variable.
0937          */
0938         .gyro_max_val = 22887 << 16,
0939         .gyro_max_scale = IIO_DEGREE_TO_RAD(300),
0940         .accel_max_val = IIO_M_S_2_TO_G(21973 << 16),
0941         .accel_max_scale = 18,
0942         .temp_scale = 5650, /* 5.65 milli degree Celsius */
0943         .int_clk = 2460000,
0944         .max_dec_rate = 2048,
0945         .has_sleep_cnt = true,
0946         .filter_freqs = adis16480_def_filter_freqs,
0947         .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0),
0948     },
0949     [ADIS16480] = {
0950         .channels = adis16480_channels,
0951         .num_channels = ARRAY_SIZE(adis16480_channels),
0952         .gyro_max_val = 22500 << 16,
0953         .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
0954         .accel_max_val = IIO_M_S_2_TO_G(12500 << 16),
0955         .accel_max_scale = 10,
0956         .temp_scale = 5650, /* 5.65 milli degree Celsius */
0957         .int_clk = 2460000,
0958         .max_dec_rate = 2048,
0959         .has_sleep_cnt = true,
0960         .filter_freqs = adis16480_def_filter_freqs,
0961         .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0),
0962     },
0963     [ADIS16485] = {
0964         .channels = adis16485_channels,
0965         .num_channels = ARRAY_SIZE(adis16485_channels),
0966         .gyro_max_val = 22500 << 16,
0967         .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
0968         .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
0969         .accel_max_scale = 5,
0970         .temp_scale = 5650, /* 5.65 milli degree Celsius */
0971         .int_clk = 2460000,
0972         .max_dec_rate = 2048,
0973         .has_sleep_cnt = true,
0974         .filter_freqs = adis16480_def_filter_freqs,
0975         .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0),
0976     },
0977     [ADIS16488] = {
0978         .channels = adis16480_channels,
0979         .num_channels = ARRAY_SIZE(adis16480_channels),
0980         .gyro_max_val = 22500 << 16,
0981         .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
0982         .accel_max_val = IIO_M_S_2_TO_G(22500 << 16),
0983         .accel_max_scale = 18,
0984         .temp_scale = 5650, /* 5.65 milli degree Celsius */
0985         .int_clk = 2460000,
0986         .max_dec_rate = 2048,
0987         .has_sleep_cnt = true,
0988         .filter_freqs = adis16480_def_filter_freqs,
0989         .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0),
0990     },
0991     [ADIS16490] = {
0992         .channels = adis16485_channels,
0993         .num_channels = ARRAY_SIZE(adis16485_channels),
0994         .gyro_max_val = 20000 << 16,
0995         .gyro_max_scale = IIO_DEGREE_TO_RAD(100),
0996         .accel_max_val = IIO_M_S_2_TO_G(16000 << 16),
0997         .accel_max_scale = 8,
0998         .temp_scale = 14285, /* 14.285 milli degree Celsius */
0999         .int_clk = 4250000,
1000         .max_dec_rate = 4250,
1001         .filter_freqs = adis16495_def_filter_freqs,
1002         .has_pps_clk_mode = true,
1003         .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0),
1004     },
1005     [ADIS16495_1] = {
1006         .channels = adis16485_channels,
1007         .num_channels = ARRAY_SIZE(adis16485_channels),
1008         .gyro_max_val = 20000 << 16,
1009         .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1010         .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1011         .accel_max_scale = 8,
1012         .temp_scale = 12500, /* 12.5 milli degree Celsius */
1013         .int_clk = 4250000,
1014         .max_dec_rate = 4250,
1015         .filter_freqs = adis16495_def_filter_freqs,
1016         .has_pps_clk_mode = true,
1017         /* 20 elements of 16bits */
1018         .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1019                         ADIS16495_BURST_MAX_DATA * 2),
1020     },
1021     [ADIS16495_2] = {
1022         .channels = adis16485_channels,
1023         .num_channels = ARRAY_SIZE(adis16485_channels),
1024         .gyro_max_val = 18000 << 16,
1025         .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1026         .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1027         .accel_max_scale = 8,
1028         .temp_scale = 12500, /* 12.5 milli degree Celsius */
1029         .int_clk = 4250000,
1030         .max_dec_rate = 4250,
1031         .filter_freqs = adis16495_def_filter_freqs,
1032         .has_pps_clk_mode = true,
1033         /* 20 elements of 16bits */
1034         .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1035                         ADIS16495_BURST_MAX_DATA * 2),
1036     },
1037     [ADIS16495_3] = {
1038         .channels = adis16485_channels,
1039         .num_channels = ARRAY_SIZE(adis16485_channels),
1040         .gyro_max_val = 20000 << 16,
1041         .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1042         .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1043         .accel_max_scale = 8,
1044         .temp_scale = 12500, /* 12.5 milli degree Celsius */
1045         .int_clk = 4250000,
1046         .max_dec_rate = 4250,
1047         .filter_freqs = adis16495_def_filter_freqs,
1048         .has_pps_clk_mode = true,
1049         /* 20 elements of 16bits */
1050         .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1051                         ADIS16495_BURST_MAX_DATA * 2),
1052     },
1053     [ADIS16497_1] = {
1054         .channels = adis16485_channels,
1055         .num_channels = ARRAY_SIZE(adis16485_channels),
1056         .gyro_max_val = 20000 << 16,
1057         .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1058         .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1059         .accel_max_scale = 40,
1060         .temp_scale = 12500, /* 12.5 milli degree Celsius */
1061         .int_clk = 4250000,
1062         .max_dec_rate = 4250,
1063         .filter_freqs = adis16495_def_filter_freqs,
1064         .has_pps_clk_mode = true,
1065         /* 20 elements of 16bits */
1066         .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1067                         ADIS16495_BURST_MAX_DATA * 2),
1068     },
1069     [ADIS16497_2] = {
1070         .channels = adis16485_channels,
1071         .num_channels = ARRAY_SIZE(adis16485_channels),
1072         .gyro_max_val = 18000 << 16,
1073         .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1074         .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1075         .accel_max_scale = 40,
1076         .temp_scale = 12500, /* 12.5 milli degree Celsius */
1077         .int_clk = 4250000,
1078         .max_dec_rate = 4250,
1079         .filter_freqs = adis16495_def_filter_freqs,
1080         .has_pps_clk_mode = true,
1081         /* 20 elements of 16bits */
1082         .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1083                         ADIS16495_BURST_MAX_DATA * 2),
1084     },
1085     [ADIS16497_3] = {
1086         .channels = adis16485_channels,
1087         .num_channels = ARRAY_SIZE(adis16485_channels),
1088         .gyro_max_val = 20000 << 16,
1089         .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1090         .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1091         .accel_max_scale = 40,
1092         .temp_scale = 12500, /* 12.5 milli degree Celsius */
1093         .int_clk = 4250000,
1094         .max_dec_rate = 4250,
1095         .filter_freqs = adis16495_def_filter_freqs,
1096         .has_pps_clk_mode = true,
1097         /* 20 elements of 16bits */
1098         .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1099                         ADIS16495_BURST_MAX_DATA * 2),
1100     },
1101 };
1102 
1103 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc)
1104 {
1105     u32 crc_calc;
1106     u16 crc_buf[15];
1107     int j;
1108 
1109     for (j = 0; j < n_elem; j++)
1110         crc_buf[j] = swab16(buf[j]);
1111 
1112     crc_calc = crc32(~0, crc_buf, n_elem * 2);
1113     crc_calc ^= ~0;
1114 
1115     return (crc == crc_calc);
1116 }
1117 
1118 static irqreturn_t adis16480_trigger_handler(int irq, void *p)
1119 {
1120     struct iio_poll_func *pf = p;
1121     struct iio_dev *indio_dev = pf->indio_dev;
1122     struct adis16480 *st = iio_priv(indio_dev);
1123     struct adis *adis = &st->adis;
1124     struct device *dev = &adis->spi->dev;
1125     int ret, bit, offset, i = 0;
1126     __be16 *buffer;
1127     u32 crc;
1128     bool valid;
1129 
1130     adis_dev_lock(adis);
1131     if (adis->current_page != 0) {
1132         adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID);
1133         adis->tx[1] = 0;
1134         ret = spi_write(adis->spi, adis->tx, 2);
1135         if (ret) {
1136             dev_err(dev, "Failed to change device page: %d\n", ret);
1137             adis_dev_unlock(adis);
1138             goto irq_done;
1139         }
1140 
1141         adis->current_page = 0;
1142     }
1143 
1144     ret = spi_sync(adis->spi, &adis->msg);
1145     if (ret) {
1146         dev_err(dev, "Failed to read data: %d\n", ret);
1147         adis_dev_unlock(adis);
1148         goto irq_done;
1149     }
1150 
1151     adis_dev_unlock(adis);
1152 
1153     /*
1154      * After making the burst request, the response can have one or two
1155      * 16-bit responses containing the BURST_ID depending on the sclk. If
1156      * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ,
1157      * we have only one. To manage that variation, we use the transition from the
1158      * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5. If
1159      * we not find this variation in the first 4 segments, then the data should
1160      * not be valid.
1161      */
1162     buffer = adis->buffer;
1163     for (offset = 0; offset < 4; offset++) {
1164         u16 curr = be16_to_cpu(buffer[offset]);
1165         u16 next = be16_to_cpu(buffer[offset + 1]);
1166 
1167         if (curr == ADIS16495_BURST_ID && next != ADIS16495_BURST_ID) {
1168             offset++;
1169             break;
1170         }
1171     }
1172 
1173     if (offset == 4) {
1174         dev_err(dev, "Invalid burst data\n");
1175         goto irq_done;
1176     }
1177 
1178     crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]);
1179     valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc);
1180     if (!valid) {
1181         dev_err(dev, "Invalid crc\n");
1182         goto irq_done;
1183     }
1184 
1185     for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) {
1186         /*
1187          * When burst mode is used, temperature is the first data
1188          * channel in the sequence, but the temperature scan index
1189          * is 10.
1190          */
1191         switch (bit) {
1192         case ADIS16480_SCAN_TEMP:
1193             st->data[i++] = buffer[offset + 1];
1194             break;
1195         case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z:
1196             /* The lower register data is sequenced first */
1197             st->data[i++] = buffer[2 * bit + offset + 3];
1198             st->data[i++] = buffer[2 * bit + offset + 2];
1199             break;
1200         }
1201     }
1202 
1203     iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1204 irq_done:
1205     iio_trigger_notify_done(indio_dev->trig);
1206 
1207     return IRQ_HANDLED;
1208 }
1209 
1210 static const struct iio_info adis16480_info = {
1211     .read_raw = &adis16480_read_raw,
1212     .write_raw = &adis16480_write_raw,
1213     .update_scan_mode = adis_update_scan_mode,
1214     .debugfs_reg_access = adis_debugfs_reg_access,
1215 };
1216 
1217 static int adis16480_stop_device(struct iio_dev *indio_dev)
1218 {
1219     struct adis16480 *st = iio_priv(indio_dev);
1220     struct device *dev = &st->adis.spi->dev;
1221     int ret;
1222 
1223     ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
1224     if (ret)
1225         dev_err(dev, "Could not power down device: %d\n", ret);
1226 
1227     return ret;
1228 }
1229 
1230 static int adis16480_enable_irq(struct adis *adis, bool enable)
1231 {
1232     uint16_t val;
1233     int ret;
1234 
1235     ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1236     if (ret)
1237         return ret;
1238 
1239     val &= ~ADIS16480_DRDY_EN_MSK;
1240     val |= ADIS16480_DRDY_EN(enable);
1241 
1242     return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
1243 }
1244 
1245 static int adis16480_config_irq_pin(struct adis16480 *st)
1246 {
1247     struct device *dev = &st->adis.spi->dev;
1248     struct fwnode_handle *fwnode = dev_fwnode(dev);
1249     struct irq_data *desc;
1250     enum adis16480_int_pin pin;
1251     unsigned int irq_type;
1252     uint16_t val;
1253     int i, irq = 0;
1254 
1255     desc = irq_get_irq_data(st->adis.spi->irq);
1256     if (!desc) {
1257         dev_err(dev, "Could not find IRQ %d\n", irq);
1258         return -EINVAL;
1259     }
1260 
1261     /* Disable data ready since the default after reset is on */
1262     val = ADIS16480_DRDY_EN(0);
1263 
1264     /*
1265      * Get the interrupt from the devicetre by reading the interrupt-names
1266      * property. If it is not specified, use DIO1 pin as default.
1267      * According to the datasheet, the factory default assigns DIO2 as data
1268      * ready signal. However, in the previous versions of the driver, DIO1
1269      * pin was used. So, we should leave it as is since some devices might
1270      * be expecting the interrupt on the wrong physical pin.
1271      */
1272     pin = ADIS16480_PIN_DIO1;
1273     for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1274         irq = fwnode_irq_get_byname(fwnode, adis16480_int_pin_names[i]);
1275         if (irq > 0) {
1276             pin = i;
1277             break;
1278         }
1279     }
1280 
1281     val |= ADIS16480_DRDY_SEL(pin);
1282 
1283     /*
1284      * Get the interrupt line behaviour. The data ready polarity can be
1285      * configured as positive or negative, corresponding to
1286      * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively.
1287      */
1288     irq_type = irqd_get_trigger_type(desc);
1289     if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */
1290         val |= ADIS16480_DRDY_POL(1);
1291     } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1292         val |= ADIS16480_DRDY_POL(0);
1293     } else {
1294         dev_err(dev, "Invalid interrupt type 0x%x specified\n", irq_type);
1295         return -EINVAL;
1296     }
1297     /* Write the data ready configuration to the FNCTIO_CTRL register */
1298     return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1299 }
1300 
1301 static int adis16480_fw_get_ext_clk_pin(struct adis16480 *st)
1302 {
1303     struct device *dev = &st->adis.spi->dev;
1304     const char *ext_clk_pin;
1305     enum adis16480_int_pin pin;
1306     int i;
1307 
1308     pin = ADIS16480_PIN_DIO2;
1309     if (device_property_read_string(dev, "adi,ext-clk-pin", &ext_clk_pin))
1310         goto clk_input_not_found;
1311 
1312     for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1313         if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
1314             return i;
1315     }
1316 
1317 clk_input_not_found:
1318     dev_info(dev, "clk input line not specified, using DIO2\n");
1319     return pin;
1320 }
1321 
1322 static int adis16480_ext_clk_config(struct adis16480 *st, bool enable)
1323 {
1324     struct device *dev = &st->adis.spi->dev;
1325     unsigned int mode, mask;
1326     enum adis16480_int_pin pin;
1327     uint16_t val;
1328     int ret;
1329 
1330     ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1331     if (ret)
1332         return ret;
1333 
1334     pin = adis16480_fw_get_ext_clk_pin(st);
1335     /*
1336      * Each DIOx pin supports only one function at a time. When a single pin
1337      * has two assignments, the enable bit for a lower priority function
1338      * automatically resets to zero (disabling the lower priority function).
1339      */
1340     if (pin == ADIS16480_DRDY_SEL(val))
1341         dev_warn(dev, "DIO%x pin supports only one function at a time\n", pin + 1);
1342 
1343     mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
1344     mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
1345     /* Only ADIS1649x devices support pps ext clock mode */
1346     if (st->chip_info->has_pps_clk_mode) {
1347         mode |= ADIS16480_SYNC_MODE(st->clk_mode);
1348         mask |= ADIS16480_SYNC_MODE_MSK;
1349     }
1350 
1351     val &= ~mask;
1352     val |= mode;
1353 
1354     ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1355     if (ret)
1356         return ret;
1357 
1358     return clk_prepare_enable(st->ext_clk);
1359 }
1360 
1361 static int adis16480_get_ext_clocks(struct adis16480 *st)
1362 {
1363     struct device *dev = &st->adis.spi->dev;
1364 
1365     st->ext_clk = devm_clk_get_optional(dev, "sync");
1366     if (IS_ERR(st->ext_clk))
1367         return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1368     if (st->ext_clk) {
1369         st->clk_mode = ADIS16480_CLK_SYNC;
1370         return 0;
1371     }
1372 
1373     if (st->chip_info->has_pps_clk_mode) {
1374         st->ext_clk = devm_clk_get_optional(dev, "pps");
1375         if (IS_ERR(st->ext_clk))
1376             return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1377         if (st->ext_clk) {
1378             st->clk_mode = ADIS16480_CLK_PPS;
1379             return 0;
1380         }
1381     }
1382 
1383     st->clk_mode = ADIS16480_CLK_INT;
1384     return 0;
1385 }
1386 
1387 static void adis16480_stop(void *data)
1388 {
1389     adis16480_stop_device(data);
1390 }
1391 
1392 static void adis16480_clk_disable(void *data)
1393 {
1394     clk_disable_unprepare(data);
1395 }
1396 
1397 static int adis16480_probe(struct spi_device *spi)
1398 {
1399     const struct spi_device_id *id = spi_get_device_id(spi);
1400     const struct adis_data *adis16480_data;
1401     irq_handler_t trigger_handler = NULL;
1402     struct device *dev = &spi->dev;
1403     struct iio_dev *indio_dev;
1404     struct adis16480 *st;
1405     int ret;
1406 
1407     indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1408     if (indio_dev == NULL)
1409         return -ENOMEM;
1410 
1411     st = iio_priv(indio_dev);
1412 
1413     st->chip_info = &adis16480_chip_info[id->driver_data];
1414     indio_dev->name = spi_get_device_id(spi)->name;
1415     indio_dev->channels = st->chip_info->channels;
1416     indio_dev->num_channels = st->chip_info->num_channels;
1417     indio_dev->info = &adis16480_info;
1418     indio_dev->modes = INDIO_DIRECT_MODE;
1419 
1420     adis16480_data = &st->chip_info->adis_data;
1421 
1422     ret = adis_init(&st->adis, indio_dev, spi, adis16480_data);
1423     if (ret)
1424         return ret;
1425 
1426     ret = __adis_initial_startup(&st->adis);
1427     if (ret)
1428         return ret;
1429 
1430     if (st->chip_info->has_sleep_cnt) {
1431         ret = devm_add_action_or_reset(dev, adis16480_stop, indio_dev);
1432         if (ret)
1433             return ret;
1434     }
1435 
1436     ret = adis16480_config_irq_pin(st);
1437     if (ret)
1438         return ret;
1439 
1440     ret = adis16480_get_ext_clocks(st);
1441     if (ret)
1442         return ret;
1443 
1444     if (st->ext_clk) {
1445         ret = adis16480_ext_clk_config(st, true);
1446         if (ret)
1447             return ret;
1448 
1449         ret = devm_add_action_or_reset(dev, adis16480_clk_disable, st->ext_clk);
1450         if (ret)
1451             return ret;
1452 
1453         st->clk_freq = clk_get_rate(st->ext_clk);
1454         st->clk_freq *= 1000; /* micro */
1455         if (st->clk_mode == ADIS16480_CLK_PPS) {
1456             u16 sync_scale;
1457 
1458             /*
1459              * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence,
1460              * default the IMU sample rate to the highest multiple of the input clock
1461              * lower than the IMU max sample rate. The internal sample rate is the
1462              * max...
1463              */
1464             sync_scale = st->chip_info->int_clk / st->clk_freq;
1465             ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
1466             if (ret)
1467                 return ret;
1468         }
1469     } else {
1470         st->clk_freq = st->chip_info->int_clk;
1471     }
1472 
1473     /* Only use our trigger handler if burst mode is supported */
1474     if (adis16480_data->burst_len)
1475         trigger_handler = adis16480_trigger_handler;
1476 
1477     ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1478                          trigger_handler);
1479     if (ret)
1480         return ret;
1481 
1482     ret = devm_iio_device_register(dev, indio_dev);
1483     if (ret)
1484         return ret;
1485 
1486     adis16480_debugfs_init(indio_dev);
1487 
1488     return 0;
1489 }
1490 
1491 static const struct spi_device_id adis16480_ids[] = {
1492     { "adis16375", ADIS16375 },
1493     { "adis16480", ADIS16480 },
1494     { "adis16485", ADIS16485 },
1495     { "adis16488", ADIS16488 },
1496     { "adis16490", ADIS16490 },
1497     { "adis16495-1", ADIS16495_1 },
1498     { "adis16495-2", ADIS16495_2 },
1499     { "adis16495-3", ADIS16495_3 },
1500     { "adis16497-1", ADIS16497_1 },
1501     { "adis16497-2", ADIS16497_2 },
1502     { "adis16497-3", ADIS16497_3 },
1503     { }
1504 };
1505 MODULE_DEVICE_TABLE(spi, adis16480_ids);
1506 
1507 static const struct of_device_id adis16480_of_match[] = {
1508     { .compatible = "adi,adis16375" },
1509     { .compatible = "adi,adis16480" },
1510     { .compatible = "adi,adis16485" },
1511     { .compatible = "adi,adis16488" },
1512     { .compatible = "adi,adis16490" },
1513     { .compatible = "adi,adis16495-1" },
1514     { .compatible = "adi,adis16495-2" },
1515     { .compatible = "adi,adis16495-3" },
1516     { .compatible = "adi,adis16497-1" },
1517     { .compatible = "adi,adis16497-2" },
1518     { .compatible = "adi,adis16497-3" },
1519     { },
1520 };
1521 MODULE_DEVICE_TABLE(of, adis16480_of_match);
1522 
1523 static struct spi_driver adis16480_driver = {
1524     .driver = {
1525         .name = "adis16480",
1526         .of_match_table = adis16480_of_match,
1527     },
1528     .id_table = adis16480_ids,
1529     .probe = adis16480_probe,
1530 };
1531 module_spi_driver(adis16480_driver);
1532 
1533 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1534 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
1535 MODULE_LICENSE("GPL v2");
1536 MODULE_IMPORT_NS(IIO_ADISLIB);
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