iio/health/max30102.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
0004  *
0005  * Copyright (C) 2017 Matt Ranostay <matt.ranostay@konsulko.com>
0006  *
0007  * Support for MAX30105 optical particle sensor
0008  * Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
0009  *
0010  * 7-bit I2C chip address: 0x57
0011  * TODO: proximity power saving feature
0012  */
0013
0014 #include <linux/module.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/delay.h>
0018 #include <linux/err.h>
0019 #include <linux/irq.h>
0020 #include <linux/i2c.h>
0021 #include <linux/mutex.h>
0022 #include <linux/mod_devicetable.h>
0023 #include <linux/regmap.h>
0024 #include <linux/iio/iio.h>
0025 #include <linux/iio/buffer.h>
0026 #include <linux/iio/kfifo_buf.h>
0027
0028 #define MAX30102_REGMAP_NAME    "max30102_regmap"
0029 #define MAX30102_DRV_NAME   "max30102"
0030 #define MAX30102_PART_NUMBER    0x15
0031
0032 enum max30102_chip_id {
0033     max30102,
0034     max30105,
0035 };
0036
0037 enum max3012_led_idx {
0038     MAX30102_LED_RED,
0039     MAX30102_LED_IR,
0040     MAX30105_LED_GREEN,
0041 };
0042
0043 #define MAX30102_REG_INT_STATUS         0x00
0044 #define MAX30102_REG_INT_STATUS_PWR_RDY     BIT(0)
0045 #define MAX30102_REG_INT_STATUS_PROX_INT    BIT(4)
0046 #define MAX30102_REG_INT_STATUS_ALC_OVF     BIT(5)
0047 #define MAX30102_REG_INT_STATUS_PPG_RDY     BIT(6)
0048 #define MAX30102_REG_INT_STATUS_FIFO_RDY    BIT(7)
0049
0050 #define MAX30102_REG_INT_ENABLE         0x02
0051 #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4)
0052 #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN  BIT(5)
0053 #define MAX30102_REG_INT_ENABLE_PPG_EN      BIT(6)
0054 #define MAX30102_REG_INT_ENABLE_FIFO_EN     BIT(7)
0055 #define MAX30102_REG_INT_ENABLE_MASK        0xf0
0056 #define MAX30102_REG_INT_ENABLE_MASK_SHIFT  4
0057
0058 #define MAX30102_REG_FIFO_WR_PTR        0x04
0059 #define MAX30102_REG_FIFO_OVR_CTR       0x05
0060 #define MAX30102_REG_FIFO_RD_PTR        0x06
0061 #define MAX30102_REG_FIFO_DATA          0x07
0062 #define MAX30102_REG_FIFO_DATA_BYTES        3
0063
0064 #define MAX30102_REG_FIFO_CONFIG        0x08
0065 #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES   BIT(1)
0066 #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT  5
0067 #define MAX30102_REG_FIFO_CONFIG_AFULL      BIT(0)
0068
0069 #define MAX30102_REG_MODE_CONFIG        0x09
0070 #define MAX30102_REG_MODE_CONFIG_MODE_NONE  0x00
0071 #define MAX30102_REG_MODE_CONFIG_MODE_HR    0x02 /* red LED */
0072 #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2   0x03 /* red + IR LED */
0073 #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
0074 #define MAX30102_REG_MODE_CONFIG_MODE_MASK  GENMASK(2, 0)
0075 #define MAX30102_REG_MODE_CONFIG_PWR        BIT(7)
0076
0077 #define MAX30102_REG_MODE_CONTROL_SLOT21    0x11 /* multi-LED control */
0078 #define MAX30102_REG_MODE_CONTROL_SLOT43    0x12
0079 #define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))
0080 #define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT    4
0081
0082 #define MAX30102_REG_SPO2_CONFIG        0x0a
0083 #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US   0x03
0084 #define MAX30102_REG_SPO2_CONFIG_SR_400HZ   0x03
0085 #define MAX30102_REG_SPO2_CONFIG_SR_MASK    0x07
0086 #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT  2
0087 #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0)
0088 #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5
0089
0090 #define MAX30102_REG_RED_LED_CONFIG     0x0c
0091 #define MAX30102_REG_IR_LED_CONFIG      0x0d
0092 #define MAX30105_REG_GREEN_LED_CONFIG       0x0e
0093
0094 #define MAX30102_REG_TEMP_CONFIG        0x21
0095 #define MAX30102_REG_TEMP_CONFIG_TEMP_EN    BIT(0)
0096
0097 #define MAX30102_REG_TEMP_INTEGER       0x1f
0098 #define MAX30102_REG_TEMP_FRACTION      0x20
0099
0100 #define MAX30102_REG_REV_ID         0xfe
0101 #define MAX30102_REG_PART_ID            0xff
0102
0103 struct max30102_data {
0104     struct i2c_client *client;
0105     struct iio_dev *indio_dev;
0106     struct mutex lock;
0107     struct regmap *regmap;
0108     enum max30102_chip_id chip_id;
0109
0110     u8 buffer[12];
0111     __be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
0112 };
0113
0114 static const struct regmap_config max30102_regmap_config = {
0115     .name = MAX30102_REGMAP_NAME,
0116
0117     .reg_bits = 8,
0118     .val_bits = 8,
0119 };
0120
0121 static const unsigned long max30102_scan_masks[] = {
0122     BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
0123     0
0124 };
0125
0126 static const unsigned long max30105_scan_masks[] = {
0127     BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
0128     BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
0129         BIT(MAX30105_LED_GREEN),
0130     0
0131 };
0132
0133 #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
0134         .type = IIO_INTENSITY, \
0135         .channel2 = _mod, \
0136         .modified = 1, \
0137         .scan_index = _si, \
0138         .scan_type = { \
0139             .sign = 'u', \
0140             .shift = 8, \
0141             .realbits = 18, \
0142             .storagebits = 32, \
0143             .endianness = IIO_BE, \
0144         }, \
0145     }
0146
0147 static const struct iio_chan_spec max30102_channels[] = {
0148     MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
0149     MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
0150     {
0151         .type = IIO_TEMP,
0152         .info_mask_separate =
0153             BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
0154         .scan_index = -1,
0155     },
0156 };
0157
0158 static const struct iio_chan_spec max30105_channels[] = {
0159     MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
0160     MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
0161     MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
0162     {
0163         .type = IIO_TEMP,
0164         .info_mask_separate =
0165             BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
0166         .scan_index = -1,
0167     },
0168 };
0169
0170 static int max30102_set_power(struct max30102_data *data, bool en)
0171 {
0172     return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
0173                   MAX30102_REG_MODE_CONFIG_PWR,
0174                   en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
0175 }
0176
0177 static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
0178 {
0179     u8 reg = mode;
0180
0181     if (!en)
0182         reg |= MAX30102_REG_MODE_CONFIG_PWR;
0183
0184     return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
0185                   MAX30102_REG_MODE_CONFIG_PWR |
0186                   MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
0187 }
0188
0189 #define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
0190     ((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
0191
0192 static int max30102_buffer_postenable(struct iio_dev *indio_dev)
0193 {
0194     struct max30102_data *data = iio_priv(indio_dev);
0195     int ret;
0196     u8 reg;
0197
0198     switch (*indio_dev->active_scan_mask) {
0199     case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
0200         reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
0201         break;
0202     case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
0203          BIT(MAX30105_LED_GREEN):
0204         ret = regmap_update_bits(data->regmap,
0205                      MAX30102_REG_MODE_CONTROL_SLOT21,
0206                      MAX30102_REG_MODE_CONTROL_SLOT_MASK,
0207                      MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
0208         if (ret)
0209             return ret;
0210
0211         ret = regmap_update_bits(data->regmap,
0212                      MAX30102_REG_MODE_CONTROL_SLOT43,
0213                      MAX30102_REG_MODE_CONTROL_SLOT_MASK,
0214                      MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
0215         if (ret)
0216             return ret;
0217
0218         reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
0219         break;
0220     default:
0221         return -EINVAL;
0222     }
0223
0224     return max30102_set_powermode(data, reg, true);
0225 }
0226
0227 static int max30102_buffer_predisable(struct iio_dev *indio_dev)
0228 {
0229     struct max30102_data *data = iio_priv(indio_dev);
0230
0231     return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
0232                       false);
0233 }
0234
0235 static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
0236     .postenable = max30102_buffer_postenable,
0237     .predisable = max30102_buffer_predisable,
0238 };
0239
0240 static inline int max30102_fifo_count(struct max30102_data *data)
0241 {
0242     unsigned int val;
0243     int ret;
0244
0245     ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
0246     if (ret)
0247         return ret;
0248
0249     /* FIFO has one sample slot left */
0250     if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
0251         return 1;
0252
0253     return 0;
0254 }
0255
0256 #define MAX30102_COPY_DATA(i) \
0257     memcpy(&data->processed_buffer[(i)], \
0258            &buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
0259            MAX30102_REG_FIFO_DATA_BYTES)
0260
0261 static int max30102_read_measurement(struct max30102_data *data,
0262                      unsigned int measurements)
0263 {
0264     int ret;
0265     u8 *buffer = (u8 *) &data->buffer;
0266
0267     ret = i2c_smbus_read_i2c_block_data(data->client,
0268                         MAX30102_REG_FIFO_DATA,
0269                         measurements *
0270                         MAX30102_REG_FIFO_DATA_BYTES,
0271                         buffer);
0272
0273     switch (measurements) {
0274     case 3:
0275         MAX30102_COPY_DATA(2);
0276         fallthrough;
0277     case 2:
0278         MAX30102_COPY_DATA(1);
0279         fallthrough;
0280     case 1:
0281         MAX30102_COPY_DATA(0);
0282         break;
0283     default:
0284         return -EINVAL;
0285     }
0286
0287     return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
0288            0 : -EINVAL;
0289 }
0290
0291 static irqreturn_t max30102_interrupt_handler(int irq, void *private)
0292 {
0293     struct iio_dev *indio_dev = private;
0294     struct max30102_data *data = iio_priv(indio_dev);
0295     unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
0296                           indio_dev->masklength);
0297     int ret, cnt = 0;
0298
0299     mutex_lock(&data->lock);
0300
0301     while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
0302         ret = max30102_read_measurement(data, measurements);
0303         if (ret)
0304             break;
0305
0306         iio_push_to_buffers(data->indio_dev, data->processed_buffer);
0307         cnt--;
0308     }
0309
0310     mutex_unlock(&data->lock);
0311
0312     return IRQ_HANDLED;
0313 }
0314
0315 static int max30102_get_current_idx(unsigned int val, int *reg)
0316 {
0317     /* each step is 0.200 mA */
0318     *reg = val / 200;
0319
0320     return *reg > 0xff ? -EINVAL : 0;
0321 }
0322
0323 static int max30102_led_init(struct max30102_data *data)
0324 {
0325     struct device *dev = &data->client->dev;
0326     unsigned int val;
0327     int reg, ret;
0328
0329     ret = device_property_read_u32(dev, "maxim,red-led-current-microamp", &val);
0330     if (ret) {
0331         dev_info(dev, "no red-led-current-microamp set\n");
0332
0333         /* Default to 7 mA RED LED */
0334         val = 7000;
0335     }
0336
0337     ret = max30102_get_current_idx(val, &reg);
0338     if (ret) {
0339         dev_err(dev, "invalid RED LED current setting %d\n", val);
0340         return ret;
0341     }
0342
0343     ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
0344     if (ret)
0345         return ret;
0346
0347     if (data->chip_id == max30105) {
0348         ret = device_property_read_u32(dev,
0349             "maxim,green-led-current-microamp", &val);
0350         if (ret) {
0351             dev_info(dev, "no green-led-current-microamp set\n");
0352
0353             /* Default to 7 mA green LED */
0354             val = 7000;
0355         }
0356
0357         ret = max30102_get_current_idx(val, &reg);
0358         if (ret) {
0359             dev_err(dev, "invalid green LED current setting %d\n",
0360                 val);
0361             return ret;
0362         }
0363
0364         ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
0365                    reg);
0366         if (ret)
0367             return ret;
0368     }
0369
0370     ret = device_property_read_u32(dev, "maxim,ir-led-current-microamp", &val);
0371     if (ret) {
0372         dev_info(dev, "no ir-led-current-microamp set\n");
0373
0374         /* Default to 7 mA IR LED */
0375         val = 7000;
0376     }
0377
0378     ret = max30102_get_current_idx(val, &reg);
0379     if (ret) {
0380         dev_err(dev, "invalid IR LED current setting %d\n", val);
0381         return ret;
0382     }
0383
0384     return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
0385 }
0386
0387 static int max30102_chip_init(struct max30102_data *data)
0388 {
0389     int ret;
0390
0391     /* setup LED current settings */
0392     ret = max30102_led_init(data);
0393     if (ret)
0394         return ret;
0395
0396     /* configure 18-bit HR + SpO2 readings at 400Hz */
0397     ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
0398                 (MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
0399                  << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
0400                 (MAX30102_REG_SPO2_CONFIG_SR_400HZ
0401                  << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
0402                  MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
0403     if (ret)
0404         return ret;
0405
0406     /* average 4 samples + generate FIFO interrupt */
0407     ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
0408                 (MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
0409                  << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
0410                  MAX30102_REG_FIFO_CONFIG_AFULL);
0411     if (ret)
0412         return ret;
0413
0414     /* enable FIFO interrupt */
0415     return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
0416                  MAX30102_REG_INT_ENABLE_MASK,
0417                  MAX30102_REG_INT_ENABLE_FIFO_EN);
0418 }
0419
0420 static int max30102_read_temp(struct max30102_data *data, int *val)
0421 {
0422     int ret;
0423     unsigned int reg;
0424
0425     ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
0426     if (ret < 0)
0427         return ret;
0428     *val = reg << 4;
0429
0430     ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
0431     if (ret < 0)
0432         return ret;
0433
0434     *val |= reg & 0xf;
0435     *val = sign_extend32(*val, 11);
0436
0437     return 0;
0438 }
0439
0440 static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
0441 {
0442     int ret;
0443
0444     if (en) {
0445         ret = max30102_set_power(data, true);
0446         if (ret)
0447             return ret;
0448     }
0449
0450     /* start acquisition */
0451     ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
0452                  MAX30102_REG_TEMP_CONFIG_TEMP_EN,
0453                  MAX30102_REG_TEMP_CONFIG_TEMP_EN);
0454     if (ret)
0455         goto out;
0456
0457     msleep(35);
0458     ret = max30102_read_temp(data, val);
0459
0460 out:
0461     if (en)
0462         max30102_set_power(data, false);
0463
0464     return ret;
0465 }
0466
0467 static int max30102_read_raw(struct iio_dev *indio_dev,
0468                  struct iio_chan_spec const *chan,
0469                  int *val, int *val2, long mask)
0470 {
0471     struct max30102_data *data = iio_priv(indio_dev);
0472     int ret = -EINVAL;
0473
0474     switch (mask) {
0475     case IIO_CHAN_INFO_RAW:
0476         /*
0477          * Temperature reading can only be acquired when not in
0478          * shutdown; leave shutdown briefly when buffer not running
0479          */
0480         mutex_lock(&indio_dev->mlock);
0481         if (!iio_buffer_enabled(indio_dev))
0482             ret = max30102_get_temp(data, val, true);
0483         else
0484             ret = max30102_get_temp(data, val, false);
0485         mutex_unlock(&indio_dev->mlock);
0486         if (ret)
0487             return ret;
0488
0489         ret = IIO_VAL_INT;
0490         break;
0491     case IIO_CHAN_INFO_SCALE:
0492         *val = 1000;  /* 62.5 */
0493         *val2 = 16;
0494         ret = IIO_VAL_FRACTIONAL;
0495         break;
0496     }
0497
0498     return ret;
0499 }
0500
0501 static const struct iio_info max30102_info = {
0502     .read_raw = max30102_read_raw,
0503 };
0504
0505 static int max30102_probe(struct i2c_client *client,
0506               const struct i2c_device_id *id)
0507 {
0508     struct max30102_data *data;
0509     struct iio_dev *indio_dev;
0510     int ret;
0511     unsigned int reg;
0512
0513     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0514     if (!indio_dev)
0515         return -ENOMEM;
0516
0517     indio_dev->name = MAX30102_DRV_NAME;
0518     indio_dev->info = &max30102_info;
0519     indio_dev->modes = INDIO_DIRECT_MODE;
0520
0521     data = iio_priv(indio_dev);
0522     data->indio_dev = indio_dev;
0523     data->client = client;
0524     data->chip_id = id->driver_data;
0525
0526     mutex_init(&data->lock);
0527     i2c_set_clientdata(client, indio_dev);
0528
0529     switch (data->chip_id) {
0530     case max30105:
0531         indio_dev->channels = max30105_channels;
0532         indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
0533         indio_dev->available_scan_masks = max30105_scan_masks;
0534         break;
0535     case max30102:
0536         indio_dev->channels = max30102_channels;
0537         indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
0538         indio_dev->available_scan_masks = max30102_scan_masks;
0539         break;
0540     default:
0541         return -ENODEV;
0542     }
0543
0544     ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
0545                       &max30102_buffer_setup_ops);
0546     if (ret)
0547         return ret;
0548
0549     data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
0550     if (IS_ERR(data->regmap)) {
0551         dev_err(&client->dev, "regmap initialization failed\n");
0552         return PTR_ERR(data->regmap);
0553     }
0554
0555     /* check part ID */
0556     ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
0557     if (ret)
0558         return ret;
0559     if (reg != MAX30102_PART_NUMBER)
0560         return -ENODEV;
0561
0562     /* show revision ID */
0563     ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
0564     if (ret)
0565         return ret;
0566     dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
0567
0568     /* clear mode setting, chip shutdown */
0569     ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
0570                      false);
0571     if (ret)
0572         return ret;
0573
0574     ret = max30102_chip_init(data);
0575     if (ret)
0576         return ret;
0577
0578     if (client->irq <= 0) {
0579         dev_err(&client->dev, "no valid irq defined\n");
0580         return -EINVAL;
0581     }
0582
0583     ret = devm_request_threaded_irq(&client->dev, client->irq,
0584                     NULL, max30102_interrupt_handler,
0585                     IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0586                     "max30102_irq", indio_dev);
0587     if (ret) {
0588         dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
0589         return ret;
0590     }
0591
0592     return iio_device_register(indio_dev);
0593 }
0594
0595 static int max30102_remove(struct i2c_client *client)
0596 {
0597     struct iio_dev *indio_dev = i2c_get_clientdata(client);
0598     struct max30102_data *data = iio_priv(indio_dev);
0599
0600     iio_device_unregister(indio_dev);
0601     max30102_set_power(data, false);
0602
0603     return 0;
0604 }
0605
0606 static const struct i2c_device_id max30102_id[] = {
0607     { "max30102", max30102 },
0608     { "max30105", max30105 },
0609     {}
0610 };
0611 MODULE_DEVICE_TABLE(i2c, max30102_id);
0612
0613 static const struct of_device_id max30102_dt_ids[] = {
0614     { .compatible = "maxim,max30102" },
0615     { .compatible = "maxim,max30105" },
0616     { }
0617 };
0618 MODULE_DEVICE_TABLE(of, max30102_dt_ids);
0619
0620 static struct i2c_driver max30102_driver = {
0621     .driver = {
0622         .name   = MAX30102_DRV_NAME,
0623         .of_match_table = max30102_dt_ids,
0624     },
0625     .probe      = max30102_probe,
0626     .remove     = max30102_remove,
0627     .id_table   = max30102_id,
0628 };
0629 module_i2c_driver(max30102_driver);
0630
0631 MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
0632 MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
0633 MODULE_LICENSE("GPL");