iio/health/max30100.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * max30100.c - Support for MAX30100 heart rate and pulse oximeter sensor
0004  *
0005  * Copyright (C) 2015, 2018
0006  * Author: Matt Ranostay <matt.ranostay@konsulko.com>
0007  *
0008  * TODO: enable pulse length controls via device tree properties
0009  */
0010
0011 #include <linux/module.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/delay.h>
0015 #include <linux/err.h>
0016 #include <linux/irq.h>
0017 #include <linux/i2c.h>
0018 #include <linux/mutex.h>
0019 #include <linux/property.h>
0020 #include <linux/regmap.h>
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/buffer.h>
0023 #include <linux/iio/kfifo_buf.h>
0024
0025 #define MAX30100_REGMAP_NAME    "max30100_regmap"
0026 #define MAX30100_DRV_NAME   "max30100"
0027
0028 #define MAX30100_REG_INT_STATUS         0x00
0029 #define MAX30100_REG_INT_STATUS_PWR_RDY     BIT(0)
0030 #define MAX30100_REG_INT_STATUS_SPO2_RDY    BIT(4)
0031 #define MAX30100_REG_INT_STATUS_HR_RDY      BIT(5)
0032 #define MAX30100_REG_INT_STATUS_FIFO_RDY    BIT(7)
0033
0034 #define MAX30100_REG_INT_ENABLE         0x01
0035 #define MAX30100_REG_INT_ENABLE_SPO2_EN     BIT(0)
0036 #define MAX30100_REG_INT_ENABLE_HR_EN       BIT(1)
0037 #define MAX30100_REG_INT_ENABLE_FIFO_EN     BIT(3)
0038 #define MAX30100_REG_INT_ENABLE_MASK        0xf0
0039 #define MAX30100_REG_INT_ENABLE_MASK_SHIFT  4
0040
0041 #define MAX30100_REG_FIFO_WR_PTR        0x02
0042 #define MAX30100_REG_FIFO_OVR_CTR       0x03
0043 #define MAX30100_REG_FIFO_RD_PTR        0x04
0044 #define MAX30100_REG_FIFO_DATA          0x05
0045 #define MAX30100_REG_FIFO_DATA_ENTRY_COUNT  16
0046 #define MAX30100_REG_FIFO_DATA_ENTRY_LEN    4
0047
0048 #define MAX30100_REG_MODE_CONFIG        0x06
0049 #define MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN   BIT(0)
0050 #define MAX30100_REG_MODE_CONFIG_MODE_HR_EN BIT(1)
0051 #define MAX30100_REG_MODE_CONFIG_MODE_MASK  0x03
0052 #define MAX30100_REG_MODE_CONFIG_TEMP_EN    BIT(3)
0053 #define MAX30100_REG_MODE_CONFIG_PWR        BIT(7)
0054
0055 #define MAX30100_REG_SPO2_CONFIG        0x07
0056 #define MAX30100_REG_SPO2_CONFIG_100HZ      BIT(2)
0057 #define MAX30100_REG_SPO2_CONFIG_HI_RES_EN  BIT(6)
0058 #define MAX30100_REG_SPO2_CONFIG_1600US     0x3
0059
0060 #define MAX30100_REG_LED_CONFIG         0x09
0061 #define MAX30100_REG_LED_CONFIG_LED_MASK    0x0f
0062 #define MAX30100_REG_LED_CONFIG_RED_LED_SHIFT   4
0063
0064 #define MAX30100_REG_LED_CONFIG_24MA        0x07
0065 #define MAX30100_REG_LED_CONFIG_50MA        0x0f
0066
0067 #define MAX30100_REG_TEMP_INTEGER       0x16
0068 #define MAX30100_REG_TEMP_FRACTION      0x17
0069
0070 struct max30100_data {
0071     struct i2c_client *client;
0072     struct iio_dev *indio_dev;
0073     struct mutex lock;
0074     struct regmap *regmap;
0075
0076     __be16 buffer[2]; /* 2 16-bit channels */
0077 };
0078
0079 static bool max30100_is_volatile_reg(struct device *dev, unsigned int reg)
0080 {
0081     switch (reg) {
0082     case MAX30100_REG_INT_STATUS:
0083     case MAX30100_REG_MODE_CONFIG:
0084     case MAX30100_REG_FIFO_WR_PTR:
0085     case MAX30100_REG_FIFO_OVR_CTR:
0086     case MAX30100_REG_FIFO_RD_PTR:
0087     case MAX30100_REG_FIFO_DATA:
0088     case MAX30100_REG_TEMP_INTEGER:
0089     case MAX30100_REG_TEMP_FRACTION:
0090         return true;
0091     default:
0092         return false;
0093     }
0094 }
0095
0096 static const struct regmap_config max30100_regmap_config = {
0097     .name = MAX30100_REGMAP_NAME,
0098
0099     .reg_bits = 8,
0100     .val_bits = 8,
0101
0102     .max_register = MAX30100_REG_TEMP_FRACTION,
0103     .cache_type = REGCACHE_FLAT,
0104
0105     .volatile_reg = max30100_is_volatile_reg,
0106 };
0107
0108 static const unsigned int max30100_led_current_mapping[] = {
0109     4400, 7600, 11000, 14200, 17400,
0110     20800, 24000, 27100, 30600, 33800,
0111     37000, 40200, 43600, 46800, 50000
0112 };
0113
0114 static const unsigned long max30100_scan_masks[] = {0x3, 0};
0115
0116 static const struct iio_chan_spec max30100_channels[] = {
0117     {
0118         .type = IIO_INTENSITY,
0119         .channel2 = IIO_MOD_LIGHT_IR,
0120         .modified = 1,
0121
0122         .scan_index = 0,
0123         .scan_type = {
0124             .sign = 'u',
0125             .realbits = 16,
0126             .storagebits = 16,
0127             .endianness = IIO_BE,
0128         },
0129     },
0130     {
0131         .type = IIO_INTENSITY,
0132         .channel2 = IIO_MOD_LIGHT_RED,
0133         .modified = 1,
0134
0135         .scan_index = 1,
0136         .scan_type = {
0137             .sign = 'u',
0138             .realbits = 16,
0139             .storagebits = 16,
0140             .endianness = IIO_BE,
0141         },
0142     },
0143     {
0144         .type = IIO_TEMP,
0145         .info_mask_separate =
0146             BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
0147         .scan_index = -1,
0148     },
0149 };
0150
0151 static int max30100_set_powermode(struct max30100_data *data, bool state)
0152 {
0153     return regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
0154                   MAX30100_REG_MODE_CONFIG_PWR,
0155                   state ? 0 : MAX30100_REG_MODE_CONFIG_PWR);
0156 }
0157
0158 static int max30100_clear_fifo(struct max30100_data *data)
0159 {
0160     int ret;
0161
0162     ret = regmap_write(data->regmap, MAX30100_REG_FIFO_WR_PTR, 0);
0163     if (ret)
0164         return ret;
0165
0166     ret = regmap_write(data->regmap, MAX30100_REG_FIFO_OVR_CTR, 0);
0167     if (ret)
0168         return ret;
0169
0170     return regmap_write(data->regmap, MAX30100_REG_FIFO_RD_PTR, 0);
0171 }
0172
0173 static int max30100_buffer_postenable(struct iio_dev *indio_dev)
0174 {
0175     struct max30100_data *data = iio_priv(indio_dev);
0176     int ret;
0177
0178     ret = max30100_set_powermode(data, true);
0179     if (ret)
0180         return ret;
0181
0182     return max30100_clear_fifo(data);
0183 }
0184
0185 static int max30100_buffer_predisable(struct iio_dev *indio_dev)
0186 {
0187     struct max30100_data *data = iio_priv(indio_dev);
0188
0189     return max30100_set_powermode(data, false);
0190 }
0191
0192 static const struct iio_buffer_setup_ops max30100_buffer_setup_ops = {
0193     .postenable = max30100_buffer_postenable,
0194     .predisable = max30100_buffer_predisable,
0195 };
0196
0197 static inline int max30100_fifo_count(struct max30100_data *data)
0198 {
0199     unsigned int val;
0200     int ret;
0201
0202     ret = regmap_read(data->regmap, MAX30100_REG_INT_STATUS, &val);
0203     if (ret)
0204         return ret;
0205
0206     /* FIFO is almost full */
0207     if (val & MAX30100_REG_INT_STATUS_FIFO_RDY)
0208         return MAX30100_REG_FIFO_DATA_ENTRY_COUNT - 1;
0209
0210     return 0;
0211 }
0212
0213 static int max30100_read_measurement(struct max30100_data *data)
0214 {
0215     int ret;
0216
0217     ret = i2c_smbus_read_i2c_block_data(data->client,
0218                         MAX30100_REG_FIFO_DATA,
0219                         MAX30100_REG_FIFO_DATA_ENTRY_LEN,
0220                         (u8 *) &data->buffer);
0221
0222     return (ret == MAX30100_REG_FIFO_DATA_ENTRY_LEN) ? 0 : ret;
0223 }
0224
0225 static irqreturn_t max30100_interrupt_handler(int irq, void *private)
0226 {
0227     struct iio_dev *indio_dev = private;
0228     struct max30100_data *data = iio_priv(indio_dev);
0229     int ret, cnt = 0;
0230
0231     mutex_lock(&data->lock);
0232
0233     while (cnt || (cnt = max30100_fifo_count(data)) > 0) {
0234         ret = max30100_read_measurement(data);
0235         if (ret)
0236             break;
0237
0238         iio_push_to_buffers(data->indio_dev, data->buffer);
0239         cnt--;
0240     }
0241
0242     mutex_unlock(&data->lock);
0243
0244     return IRQ_HANDLED;
0245 }
0246
0247 static int max30100_get_current_idx(unsigned int val, int *reg)
0248 {
0249     int idx;
0250
0251     /* LED turned off */
0252     if (val == 0) {
0253         *reg = 0;
0254         return 0;
0255     }
0256
0257     for (idx = 0; idx < ARRAY_SIZE(max30100_led_current_mapping); idx++) {
0258         if (max30100_led_current_mapping[idx] == val) {
0259             *reg = idx + 1;
0260             return 0;
0261         }
0262     }
0263
0264     return -EINVAL;
0265 }
0266
0267 static int max30100_led_init(struct max30100_data *data)
0268 {
0269     struct device *dev = &data->client->dev;
0270     unsigned int val[2];
0271     int reg, ret;
0272
0273     ret = device_property_read_u32_array(dev, "maxim,led-current-microamp",
0274                     (unsigned int *) &val, 2);
0275     if (ret) {
0276         /* Default to 24 mA RED LED, 50 mA IR LED */
0277         reg = (MAX30100_REG_LED_CONFIG_24MA <<
0278             MAX30100_REG_LED_CONFIG_RED_LED_SHIFT) |
0279             MAX30100_REG_LED_CONFIG_50MA;
0280         dev_warn(dev, "no led-current-microamp set");
0281
0282         return regmap_write(data->regmap, MAX30100_REG_LED_CONFIG, reg);
0283     }
0284
0285     /* RED LED current */
0286     ret = max30100_get_current_idx(val[0], &reg);
0287     if (ret) {
0288         dev_err(dev, "invalid RED current setting %d", val[0]);
0289         return ret;
0290     }
0291
0292     ret = regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
0293         MAX30100_REG_LED_CONFIG_LED_MASK <<
0294         MAX30100_REG_LED_CONFIG_RED_LED_SHIFT,
0295         reg << MAX30100_REG_LED_CONFIG_RED_LED_SHIFT);
0296     if (ret)
0297         return ret;
0298
0299     /* IR LED current */
0300     ret = max30100_get_current_idx(val[1], &reg);
0301     if (ret) {
0302         dev_err(dev, "invalid IR current setting %d", val[1]);
0303         return ret;
0304     }
0305
0306     return regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
0307         MAX30100_REG_LED_CONFIG_LED_MASK, reg);
0308 }
0309
0310 static int max30100_chip_init(struct max30100_data *data)
0311 {
0312     int ret;
0313
0314     /* setup LED current settings */
0315     ret = max30100_led_init(data);
0316     if (ret)
0317         return ret;
0318
0319     /* enable hi-res SPO2 readings at 100Hz */
0320     ret = regmap_write(data->regmap, MAX30100_REG_SPO2_CONFIG,
0321                  MAX30100_REG_SPO2_CONFIG_HI_RES_EN |
0322                  MAX30100_REG_SPO2_CONFIG_100HZ);
0323     if (ret)
0324         return ret;
0325
0326     /* enable SPO2 mode */
0327     ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
0328                  MAX30100_REG_MODE_CONFIG_MODE_MASK,
0329                  MAX30100_REG_MODE_CONFIG_MODE_HR_EN |
0330                  MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN);
0331     if (ret)
0332         return ret;
0333
0334     /* enable FIFO interrupt */
0335     return regmap_update_bits(data->regmap, MAX30100_REG_INT_ENABLE,
0336                  MAX30100_REG_INT_ENABLE_MASK,
0337                  MAX30100_REG_INT_ENABLE_FIFO_EN
0338                  << MAX30100_REG_INT_ENABLE_MASK_SHIFT);
0339 }
0340
0341 static int max30100_read_temp(struct max30100_data *data, int *val)
0342 {
0343     int ret;
0344     unsigned int reg;
0345
0346     ret = regmap_read(data->regmap, MAX30100_REG_TEMP_INTEGER, &reg);
0347     if (ret < 0)
0348         return ret;
0349     *val = reg << 4;
0350
0351     ret = regmap_read(data->regmap, MAX30100_REG_TEMP_FRACTION, &reg);
0352     if (ret < 0)
0353         return ret;
0354
0355     *val |= reg & 0xf;
0356     *val = sign_extend32(*val, 11);
0357
0358     return 0;
0359 }
0360
0361 static int max30100_get_temp(struct max30100_data *data, int *val)
0362 {
0363     int ret;
0364
0365     /* start acquisition */
0366     ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
0367                  MAX30100_REG_MODE_CONFIG_TEMP_EN,
0368                  MAX30100_REG_MODE_CONFIG_TEMP_EN);
0369     if (ret)
0370         return ret;
0371
0372     msleep(35);
0373
0374     return max30100_read_temp(data, val);
0375 }
0376
0377 static int max30100_read_raw(struct iio_dev *indio_dev,
0378                  struct iio_chan_spec const *chan,
0379                  int *val, int *val2, long mask)
0380 {
0381     struct max30100_data *data = iio_priv(indio_dev);
0382     int ret = -EINVAL;
0383
0384     switch (mask) {
0385     case IIO_CHAN_INFO_RAW:
0386         /*
0387          * Temperature reading can only be acquired while engine
0388          * is running
0389          */
0390         mutex_lock(&indio_dev->mlock);
0391
0392         if (!iio_buffer_enabled(indio_dev))
0393             ret = -EAGAIN;
0394         else {
0395             ret = max30100_get_temp(data, val);
0396             if (!ret)
0397                 ret = IIO_VAL_INT;
0398
0399         }
0400
0401         mutex_unlock(&indio_dev->mlock);
0402         break;
0403     case IIO_CHAN_INFO_SCALE:
0404         *val = 1;  /* 0.0625 */
0405         *val2 = 16;
0406         ret = IIO_VAL_FRACTIONAL;
0407         break;
0408     }
0409
0410     return ret;
0411 }
0412
0413 static const struct iio_info max30100_info = {
0414     .read_raw = max30100_read_raw,
0415 };
0416
0417 static int max30100_probe(struct i2c_client *client,
0418               const struct i2c_device_id *id)
0419 {
0420     struct max30100_data *data;
0421     struct iio_dev *indio_dev;
0422     int ret;
0423
0424     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0425     if (!indio_dev)
0426         return -ENOMEM;
0427
0428     indio_dev->name = MAX30100_DRV_NAME;
0429     indio_dev->channels = max30100_channels;
0430     indio_dev->info = &max30100_info;
0431     indio_dev->num_channels = ARRAY_SIZE(max30100_channels);
0432     indio_dev->available_scan_masks = max30100_scan_masks;
0433     indio_dev->modes = INDIO_DIRECT_MODE;
0434
0435     ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
0436                       &max30100_buffer_setup_ops);
0437     if (ret)
0438         return ret;
0439
0440     data = iio_priv(indio_dev);
0441     data->indio_dev = indio_dev;
0442     data->client = client;
0443
0444     mutex_init(&data->lock);
0445     i2c_set_clientdata(client, indio_dev);
0446
0447     data->regmap = devm_regmap_init_i2c(client, &max30100_regmap_config);
0448     if (IS_ERR(data->regmap)) {
0449         dev_err(&client->dev, "regmap initialization failed.\n");
0450         return PTR_ERR(data->regmap);
0451     }
0452     max30100_set_powermode(data, false);
0453
0454     ret = max30100_chip_init(data);
0455     if (ret)
0456         return ret;
0457
0458     if (client->irq <= 0) {
0459         dev_err(&client->dev, "no valid irq defined\n");
0460         return -EINVAL;
0461     }
0462     ret = devm_request_threaded_irq(&client->dev, client->irq,
0463                     NULL, max30100_interrupt_handler,
0464                     IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0465                     "max30100_irq", indio_dev);
0466     if (ret) {
0467         dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
0468         return ret;
0469     }
0470
0471     return iio_device_register(indio_dev);
0472 }
0473
0474 static int max30100_remove(struct i2c_client *client)
0475 {
0476     struct iio_dev *indio_dev = i2c_get_clientdata(client);
0477     struct max30100_data *data = iio_priv(indio_dev);
0478
0479     iio_device_unregister(indio_dev);
0480     max30100_set_powermode(data, false);
0481
0482     return 0;
0483 }
0484
0485 static const struct i2c_device_id max30100_id[] = {
0486     { "max30100", 0 },
0487     {}
0488 };
0489 MODULE_DEVICE_TABLE(i2c, max30100_id);
0490
0491 static const struct of_device_id max30100_dt_ids[] = {
0492     { .compatible = "maxim,max30100" },
0493     { }
0494 };
0495 MODULE_DEVICE_TABLE(of, max30100_dt_ids);
0496
0497 static struct i2c_driver max30100_driver = {
0498     .driver = {
0499         .name   = MAX30100_DRV_NAME,
0500         .of_match_table = max30100_dt_ids,
0501     },
0502     .probe      = max30100_probe,
0503     .remove     = max30100_remove,
0504     .id_table   = max30100_id,
0505 };
0506 module_i2c_driver(max30100_driver);
0507
0508 MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
0509 MODULE_DESCRIPTION("MAX30100 heart rate and pulse oximeter sensor");
0510 MODULE_LICENSE("GPL");