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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MPU3050 gyroscope driver
0004  *
0005  * Copyright (C) 2016 Linaro Ltd.
0006  * Author: Linus Walleij <linus.walleij@linaro.org>
0007  *
0008  * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
0009  * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
0010  * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
0011  * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
0012  *
0013  * TODO: add support for setting up the low pass 3dB frequency.
0014  */
0015 
0016 #include <linux/bitfield.h>
0017 #include <linux/bitops.h>
0018 #include <linux/delay.h>
0019 #include <linux/err.h>
0020 #include <linux/iio/buffer.h>
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/sysfs.h>
0023 #include <linux/iio/trigger.h>
0024 #include <linux/iio/trigger_consumer.h>
0025 #include <linux/iio/triggered_buffer.h>
0026 #include <linux/interrupt.h>
0027 #include <linux/module.h>
0028 #include <linux/pm_runtime.h>
0029 #include <linux/property.h>
0030 #include <linux/random.h>
0031 #include <linux/slab.h>
0032 
0033 #include "mpu3050.h"
0034 
0035 #define MPU3050_CHIP_ID     0x68
0036 #define MPU3050_CHIP_ID_MASK    0x7E
0037 
0038 /*
0039  * Register map: anything suffixed *_H is a big-endian high byte and always
0040  * followed by the corresponding low byte (*_L) even though these are not
0041  * explicitly included in the register definitions.
0042  */
0043 #define MPU3050_CHIP_ID_REG 0x00
0044 #define MPU3050_PRODUCT_ID_REG  0x01
0045 #define MPU3050_XG_OFFS_TC  0x05
0046 #define MPU3050_YG_OFFS_TC  0x08
0047 #define MPU3050_ZG_OFFS_TC  0x0B
0048 #define MPU3050_X_OFFS_USR_H    0x0C
0049 #define MPU3050_Y_OFFS_USR_H    0x0E
0050 #define MPU3050_Z_OFFS_USR_H    0x10
0051 #define MPU3050_FIFO_EN     0x12
0052 #define MPU3050_AUX_VDDIO   0x13
0053 #define MPU3050_SLV_ADDR    0x14
0054 #define MPU3050_SMPLRT_DIV  0x15
0055 #define MPU3050_DLPF_FS_SYNC    0x16
0056 #define MPU3050_INT_CFG     0x17
0057 #define MPU3050_AUX_ADDR    0x18
0058 #define MPU3050_INT_STATUS  0x1A
0059 #define MPU3050_TEMP_H      0x1B
0060 #define MPU3050_XOUT_H      0x1D
0061 #define MPU3050_YOUT_H      0x1F
0062 #define MPU3050_ZOUT_H      0x21
0063 #define MPU3050_DMP_CFG1    0x35
0064 #define MPU3050_DMP_CFG2    0x36
0065 #define MPU3050_BANK_SEL    0x37
0066 #define MPU3050_MEM_START_ADDR  0x38
0067 #define MPU3050_MEM_R_W     0x39
0068 #define MPU3050_FIFO_COUNT_H    0x3A
0069 #define MPU3050_FIFO_R      0x3C
0070 #define MPU3050_USR_CTRL    0x3D
0071 #define MPU3050_PWR_MGM     0x3E
0072 
0073 /* MPU memory bank read options */
0074 #define MPU3050_MEM_PRFTCH  BIT(5)
0075 #define MPU3050_MEM_USER_BANK   BIT(4)
0076 /* Bits 8-11 select memory bank */
0077 #define MPU3050_MEM_RAM_BANK_0  0
0078 #define MPU3050_MEM_RAM_BANK_1  1
0079 #define MPU3050_MEM_RAM_BANK_2  2
0080 #define MPU3050_MEM_RAM_BANK_3  3
0081 #define MPU3050_MEM_OTP_BANK_0  4
0082 
0083 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
0084 
0085 /* Register bits */
0086 
0087 /* FIFO Enable */
0088 #define MPU3050_FIFO_EN_FOOTER      BIT(0)
0089 #define MPU3050_FIFO_EN_AUX_ZOUT    BIT(1)
0090 #define MPU3050_FIFO_EN_AUX_YOUT    BIT(2)
0091 #define MPU3050_FIFO_EN_AUX_XOUT    BIT(3)
0092 #define MPU3050_FIFO_EN_GYRO_ZOUT   BIT(4)
0093 #define MPU3050_FIFO_EN_GYRO_YOUT   BIT(5)
0094 #define MPU3050_FIFO_EN_GYRO_XOUT   BIT(6)
0095 #define MPU3050_FIFO_EN_TEMP_OUT    BIT(7)
0096 
0097 /*
0098  * Digital Low Pass filter (DLPF)
0099  * Full Scale (FS)
0100  * and Synchronization
0101  */
0102 #define MPU3050_EXT_SYNC_NONE       0x00
0103 #define MPU3050_EXT_SYNC_TEMP       0x20
0104 #define MPU3050_EXT_SYNC_GYROX      0x40
0105 #define MPU3050_EXT_SYNC_GYROY      0x60
0106 #define MPU3050_EXT_SYNC_GYROZ      0x80
0107 #define MPU3050_EXT_SYNC_ACCELX 0xA0
0108 #define MPU3050_EXT_SYNC_ACCELY 0xC0
0109 #define MPU3050_EXT_SYNC_ACCELZ 0xE0
0110 #define MPU3050_EXT_SYNC_MASK       0xE0
0111 #define MPU3050_EXT_SYNC_SHIFT      5
0112 
0113 #define MPU3050_FS_250DPS       0x00
0114 #define MPU3050_FS_500DPS       0x08
0115 #define MPU3050_FS_1000DPS      0x10
0116 #define MPU3050_FS_2000DPS      0x18
0117 #define MPU3050_FS_MASK         0x18
0118 #define MPU3050_FS_SHIFT        3
0119 
0120 #define MPU3050_DLPF_CFG_256HZ_NOLPF2   0x00
0121 #define MPU3050_DLPF_CFG_188HZ      0x01
0122 #define MPU3050_DLPF_CFG_98HZ       0x02
0123 #define MPU3050_DLPF_CFG_42HZ       0x03
0124 #define MPU3050_DLPF_CFG_20HZ       0x04
0125 #define MPU3050_DLPF_CFG_10HZ       0x05
0126 #define MPU3050_DLPF_CFG_5HZ        0x06
0127 #define MPU3050_DLPF_CFG_2100HZ_NOLPF   0x07
0128 #define MPU3050_DLPF_CFG_MASK       0x07
0129 #define MPU3050_DLPF_CFG_SHIFT      0
0130 
0131 /* Interrupt config */
0132 #define MPU3050_INT_RAW_RDY_EN      BIT(0)
0133 #define MPU3050_INT_DMP_DONE_EN     BIT(1)
0134 #define MPU3050_INT_MPU_RDY_EN      BIT(2)
0135 #define MPU3050_INT_ANYRD_2CLEAR    BIT(4)
0136 #define MPU3050_INT_LATCH_EN        BIT(5)
0137 #define MPU3050_INT_OPEN        BIT(6)
0138 #define MPU3050_INT_ACTL        BIT(7)
0139 /* Interrupt status */
0140 #define MPU3050_INT_STATUS_RAW_RDY  BIT(0)
0141 #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
0142 #define MPU3050_INT_STATUS_MPU_RDY  BIT(2)
0143 #define MPU3050_INT_STATUS_FIFO_OVFLW   BIT(7)
0144 /* USR_CTRL */
0145 #define MPU3050_USR_CTRL_FIFO_EN    BIT(6)
0146 #define MPU3050_USR_CTRL_AUX_IF_EN  BIT(5)
0147 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
0148 #define MPU3050_USR_CTRL_FIFO_RST   BIT(1)
0149 #define MPU3050_USR_CTRL_GYRO_RST   BIT(0)
0150 /* PWR_MGM */
0151 #define MPU3050_PWR_MGM_PLL_X       0x01
0152 #define MPU3050_PWR_MGM_PLL_Y       0x02
0153 #define MPU3050_PWR_MGM_PLL_Z       0x03
0154 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
0155 #define MPU3050_PWR_MGM_STBY_ZG     BIT(3)
0156 #define MPU3050_PWR_MGM_STBY_YG     BIT(4)
0157 #define MPU3050_PWR_MGM_STBY_XG     BIT(5)
0158 #define MPU3050_PWR_MGM_SLEEP       BIT(6)
0159 #define MPU3050_PWR_MGM_RESET       BIT(7)
0160 #define MPU3050_PWR_MGM_MASK        0xff
0161 
0162 /*
0163  * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
0164  * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
0165  * in two's complement.
0166  */
0167 static unsigned int mpu3050_fs_precision[] = {
0168     IIO_DEGREE_TO_RAD(250),
0169     IIO_DEGREE_TO_RAD(500),
0170     IIO_DEGREE_TO_RAD(1000),
0171     IIO_DEGREE_TO_RAD(2000)
0172 };
0173 
0174 /*
0175  * Regulator names
0176  */
0177 static const char mpu3050_reg_vdd[] = "vdd";
0178 static const char mpu3050_reg_vlogic[] = "vlogic";
0179 
0180 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
0181 {
0182     unsigned int freq;
0183 
0184     if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
0185         freq = 8000;
0186     else
0187         freq = 1000;
0188     freq /= (mpu3050->divisor + 1);
0189 
0190     return freq;
0191 }
0192 
0193 static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
0194 {
0195     __be16 raw_val[3];
0196     int ret;
0197     int i;
0198 
0199     /* Reset */
0200     ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
0201                  MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
0202     if (ret)
0203         return ret;
0204 
0205     /* Turn on the Z-axis PLL */
0206     ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
0207                  MPU3050_PWR_MGM_CLKSEL_MASK,
0208                  MPU3050_PWR_MGM_PLL_Z);
0209     if (ret)
0210         return ret;
0211 
0212     /* Write calibration offset registers */
0213     for (i = 0; i < 3; i++)
0214         raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
0215 
0216     ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
0217                 sizeof(raw_val));
0218     if (ret)
0219         return ret;
0220 
0221     /* Set low pass filter (sample rate), sync and full scale */
0222     ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
0223                MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
0224                mpu3050->fullscale << MPU3050_FS_SHIFT |
0225                mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
0226     if (ret)
0227         return ret;
0228 
0229     /* Set up sampling frequency */
0230     ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
0231     if (ret)
0232         return ret;
0233 
0234     /*
0235      * Max 50 ms start-up time after setting DLPF_FS_SYNC
0236      * according to the data sheet, then wait for the next sample
0237      * at this frequency T = 1000/f ms.
0238      */
0239     msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
0240 
0241     return 0;
0242 }
0243 
0244 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
0245 {
0246     int ret;
0247     u8 divisor;
0248     enum mpu3050_lpf lpf;
0249 
0250     lpf = mpu3050->lpf;
0251     divisor = mpu3050->divisor;
0252 
0253     mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
0254     mpu3050->divisor = 0; /* Divide by 1 */
0255     ret = mpu3050_start_sampling(mpu3050);
0256 
0257     mpu3050->lpf = lpf;
0258     mpu3050->divisor = divisor;
0259 
0260     return ret;
0261 }
0262 
0263 static int mpu3050_read_raw(struct iio_dev *indio_dev,
0264                 struct iio_chan_spec const *chan,
0265                 int *val, int *val2,
0266                 long mask)
0267 {
0268     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0269     int ret;
0270     __be16 raw_val;
0271 
0272     switch (mask) {
0273     case IIO_CHAN_INFO_OFFSET:
0274         switch (chan->type) {
0275         case IIO_TEMP:
0276             /*
0277              * The temperature scaling is (x+23000)/280 Celsius
0278              * for the "best fit straight line" temperature range
0279              * of -30C..85C.  The 23000 includes room temperature
0280              * offset of +35C, 280 is the precision scale and x is
0281              * the 16-bit signed integer reported by hardware.
0282              *
0283              * Temperature value itself represents temperature of
0284              * the sensor die.
0285              */
0286             *val = 23000;
0287             return IIO_VAL_INT;
0288         default:
0289             return -EINVAL;
0290         }
0291     case IIO_CHAN_INFO_CALIBBIAS:
0292         switch (chan->type) {
0293         case IIO_ANGL_VEL:
0294             *val = mpu3050->calibration[chan->scan_index-1];
0295             return IIO_VAL_INT;
0296         default:
0297             return -EINVAL;
0298         }
0299     case IIO_CHAN_INFO_SAMP_FREQ:
0300         *val = mpu3050_get_freq(mpu3050);
0301         return IIO_VAL_INT;
0302     case IIO_CHAN_INFO_SCALE:
0303         switch (chan->type) {
0304         case IIO_TEMP:
0305             /* Millidegrees, see about temperature scaling above */
0306             *val = 1000;
0307             *val2 = 280;
0308             return IIO_VAL_FRACTIONAL;
0309         case IIO_ANGL_VEL:
0310             /*
0311              * Convert to the corresponding full scale in
0312              * radians. All 16 bits are used with sign to
0313              * span the available scale: to account for the one
0314              * missing value if we multiply by 1/S16_MAX, instead
0315              * multiply with 2/U16_MAX.
0316              */
0317             *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
0318             *val2 = U16_MAX;
0319             return IIO_VAL_FRACTIONAL;
0320         default:
0321             return -EINVAL;
0322         }
0323     case IIO_CHAN_INFO_RAW:
0324         /* Resume device */
0325         pm_runtime_get_sync(mpu3050->dev);
0326         mutex_lock(&mpu3050->lock);
0327 
0328         ret = mpu3050_set_8khz_samplerate(mpu3050);
0329         if (ret)
0330             goto out_read_raw_unlock;
0331 
0332         switch (chan->type) {
0333         case IIO_TEMP:
0334             ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
0335                            &raw_val, sizeof(raw_val));
0336             if (ret) {
0337                 dev_err(mpu3050->dev,
0338                     "error reading temperature\n");
0339                 goto out_read_raw_unlock;
0340             }
0341 
0342             *val = (s16)be16_to_cpu(raw_val);
0343             ret = IIO_VAL_INT;
0344 
0345             goto out_read_raw_unlock;
0346         case IIO_ANGL_VEL:
0347             ret = regmap_bulk_read(mpu3050->map,
0348                        MPU3050_AXIS_REGS(chan->scan_index-1),
0349                        &raw_val,
0350                        sizeof(raw_val));
0351             if (ret) {
0352                 dev_err(mpu3050->dev,
0353                     "error reading axis data\n");
0354                 goto out_read_raw_unlock;
0355             }
0356 
0357             *val = be16_to_cpu(raw_val);
0358             ret = IIO_VAL_INT;
0359 
0360             goto out_read_raw_unlock;
0361         default:
0362             ret = -EINVAL;
0363             goto out_read_raw_unlock;
0364         }
0365     default:
0366         break;
0367     }
0368 
0369     return -EINVAL;
0370 
0371 out_read_raw_unlock:
0372     mutex_unlock(&mpu3050->lock);
0373     pm_runtime_mark_last_busy(mpu3050->dev);
0374     pm_runtime_put_autosuspend(mpu3050->dev);
0375 
0376     return ret;
0377 }
0378 
0379 static int mpu3050_write_raw(struct iio_dev *indio_dev,
0380                  const struct iio_chan_spec *chan,
0381                  int val, int val2, long mask)
0382 {
0383     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0384     /*
0385      * Couldn't figure out a way to precalculate these at compile time.
0386      */
0387     unsigned int fs250 =
0388         DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
0389                   U16_MAX);
0390     unsigned int fs500 =
0391         DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
0392                   U16_MAX);
0393     unsigned int fs1000 =
0394         DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
0395                   U16_MAX);
0396     unsigned int fs2000 =
0397         DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
0398                   U16_MAX);
0399 
0400     switch (mask) {
0401     case IIO_CHAN_INFO_CALIBBIAS:
0402         if (chan->type != IIO_ANGL_VEL)
0403             return -EINVAL;
0404         mpu3050->calibration[chan->scan_index-1] = val;
0405         return 0;
0406     case IIO_CHAN_INFO_SAMP_FREQ:
0407         /*
0408          * The max samplerate is 8000 Hz, the minimum
0409          * 1000 / 256 ~= 4 Hz
0410          */
0411         if (val < 4 || val > 8000)
0412             return -EINVAL;
0413 
0414         /*
0415          * Above 1000 Hz we must turn off the digital low pass filter
0416          * so we get a base frequency of 8kHz to the divider
0417          */
0418         if (val > 1000) {
0419             mpu3050->lpf = LPF_256_HZ_NOLPF;
0420             mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
0421             return 0;
0422         }
0423 
0424         mpu3050->lpf = LPF_188_HZ;
0425         mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
0426         return 0;
0427     case IIO_CHAN_INFO_SCALE:
0428         if (chan->type != IIO_ANGL_VEL)
0429             return -EINVAL;
0430         /*
0431          * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
0432          * which means we need to round to the closest radians
0433          * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
0434          * rad/s. The scale is then for the 16 bits used to cover
0435          * it 2/(2^16) of that.
0436          */
0437 
0438         /* Just too large, set the max range */
0439         if (val != 0) {
0440             mpu3050->fullscale = FS_2000_DPS;
0441             return 0;
0442         }
0443 
0444         /*
0445          * Now we're dealing with fractions below zero in millirad/s
0446          * do some integer interpolation and match with the closest
0447          * fullscale in the table.
0448          */
0449         if (val2 <= fs250 ||
0450             val2 < ((fs500 + fs250) / 2))
0451             mpu3050->fullscale = FS_250_DPS;
0452         else if (val2 <= fs500 ||
0453              val2 < ((fs1000 + fs500) / 2))
0454             mpu3050->fullscale = FS_500_DPS;
0455         else if (val2 <= fs1000 ||
0456              val2 < ((fs2000 + fs1000) / 2))
0457             mpu3050->fullscale = FS_1000_DPS;
0458         else
0459             /* Catch-all */
0460             mpu3050->fullscale = FS_2000_DPS;
0461         return 0;
0462     default:
0463         break;
0464     }
0465 
0466     return -EINVAL;
0467 }
0468 
0469 static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
0470 {
0471     const struct iio_poll_func *pf = p;
0472     struct iio_dev *indio_dev = pf->indio_dev;
0473     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0474     int ret;
0475     struct {
0476         __be16 chans[4];
0477         s64 timestamp __aligned(8);
0478     } scan;
0479     s64 timestamp;
0480     unsigned int datums_from_fifo = 0;
0481 
0482     /*
0483      * If we're using the hardware trigger, get the precise timestamp from
0484      * the top half of the threaded IRQ handler. Otherwise get the
0485      * timestamp here so it will be close in time to the actual values
0486      * read from the registers.
0487      */
0488     if (iio_trigger_using_own(indio_dev))
0489         timestamp = mpu3050->hw_timestamp;
0490     else
0491         timestamp = iio_get_time_ns(indio_dev);
0492 
0493     mutex_lock(&mpu3050->lock);
0494 
0495     /* Using the hardware IRQ trigger? Check the buffer then. */
0496     if (mpu3050->hw_irq_trigger) {
0497         __be16 raw_fifocnt;
0498         u16 fifocnt;
0499         /* X, Y, Z + temperature */
0500         unsigned int bytes_per_datum = 8;
0501         bool fifo_overflow = false;
0502 
0503         ret = regmap_bulk_read(mpu3050->map,
0504                        MPU3050_FIFO_COUNT_H,
0505                        &raw_fifocnt,
0506                        sizeof(raw_fifocnt));
0507         if (ret)
0508             goto out_trigger_unlock;
0509         fifocnt = be16_to_cpu(raw_fifocnt);
0510 
0511         if (fifocnt == 512) {
0512             dev_info(mpu3050->dev,
0513                  "FIFO overflow! Emptying and resetting FIFO\n");
0514             fifo_overflow = true;
0515             /* Reset and enable the FIFO */
0516             ret = regmap_update_bits(mpu3050->map,
0517                          MPU3050_USR_CTRL,
0518                          MPU3050_USR_CTRL_FIFO_EN |
0519                          MPU3050_USR_CTRL_FIFO_RST,
0520                          MPU3050_USR_CTRL_FIFO_EN |
0521                          MPU3050_USR_CTRL_FIFO_RST);
0522             if (ret) {
0523                 dev_info(mpu3050->dev, "error resetting FIFO\n");
0524                 goto out_trigger_unlock;
0525             }
0526             mpu3050->pending_fifo_footer = false;
0527         }
0528 
0529         if (fifocnt)
0530             dev_dbg(mpu3050->dev,
0531                 "%d bytes in the FIFO\n",
0532                 fifocnt);
0533 
0534         while (!fifo_overflow && fifocnt > bytes_per_datum) {
0535             unsigned int toread;
0536             unsigned int offset;
0537             __be16 fifo_values[5];
0538 
0539             /*
0540              * If there is a FIFO footer in the pipe, first clear
0541              * that out. This follows the complex algorithm in the
0542              * datasheet that states that you may never leave the
0543              * FIFO empty after the first reading: you have to
0544              * always leave two footer bytes in it. The footer is
0545              * in practice just two zero bytes.
0546              */
0547             if (mpu3050->pending_fifo_footer) {
0548                 toread = bytes_per_datum + 2;
0549                 offset = 0;
0550             } else {
0551                 toread = bytes_per_datum;
0552                 offset = 1;
0553                 /* Put in some dummy value */
0554                 fifo_values[0] = cpu_to_be16(0xAAAA);
0555             }
0556 
0557             ret = regmap_bulk_read(mpu3050->map,
0558                            MPU3050_FIFO_R,
0559                            &fifo_values[offset],
0560                            toread);
0561             if (ret)
0562                 goto out_trigger_unlock;
0563 
0564             dev_dbg(mpu3050->dev,
0565                 "%04x %04x %04x %04x %04x\n",
0566                 fifo_values[0],
0567                 fifo_values[1],
0568                 fifo_values[2],
0569                 fifo_values[3],
0570                 fifo_values[4]);
0571 
0572             /* Index past the footer (fifo_values[0]) and push */
0573             iio_push_to_buffers_with_ts_unaligned(indio_dev,
0574                                   &fifo_values[1],
0575                                   sizeof(__be16) * 4,
0576                                   timestamp);
0577 
0578             fifocnt -= toread;
0579             datums_from_fifo++;
0580             mpu3050->pending_fifo_footer = true;
0581 
0582             /*
0583              * If we're emptying the FIFO, just make sure to
0584              * check if something new appeared.
0585              */
0586             if (fifocnt < bytes_per_datum) {
0587                 ret = regmap_bulk_read(mpu3050->map,
0588                                MPU3050_FIFO_COUNT_H,
0589                                &raw_fifocnt,
0590                                sizeof(raw_fifocnt));
0591                 if (ret)
0592                     goto out_trigger_unlock;
0593                 fifocnt = be16_to_cpu(raw_fifocnt);
0594             }
0595 
0596             if (fifocnt < bytes_per_datum)
0597                 dev_dbg(mpu3050->dev,
0598                     "%d bytes left in the FIFO\n",
0599                     fifocnt);
0600 
0601             /*
0602              * At this point, the timestamp that triggered the
0603              * hardware interrupt is no longer valid for what
0604              * we are reading (the interrupt likely fired for
0605              * the value on the top of the FIFO), so set the
0606              * timestamp to zero and let userspace deal with it.
0607              */
0608             timestamp = 0;
0609         }
0610     }
0611 
0612     /*
0613      * If we picked some datums from the FIFO that's enough, else
0614      * fall through and just read from the current value registers.
0615      * This happens in two cases:
0616      *
0617      * - We are using some other trigger (external, like an HRTimer)
0618      *   than the sensor's own sample generator. In this case the
0619      *   sensor is just set to the max sampling frequency and we give
0620      *   the trigger a copy of the latest value every time we get here.
0621      *
0622      * - The hardware trigger is active but unused and we actually use
0623      *   another trigger which calls here with a frequency higher
0624      *   than what the device provides data. We will then just read
0625      *   duplicate values directly from the hardware registers.
0626      */
0627     if (datums_from_fifo) {
0628         dev_dbg(mpu3050->dev,
0629             "read %d datums from the FIFO\n",
0630             datums_from_fifo);
0631         goto out_trigger_unlock;
0632     }
0633 
0634     ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans,
0635                    sizeof(scan.chans));
0636     if (ret) {
0637         dev_err(mpu3050->dev,
0638             "error reading axis data\n");
0639         goto out_trigger_unlock;
0640     }
0641 
0642     iio_push_to_buffers_with_timestamp(indio_dev, &scan, timestamp);
0643 
0644 out_trigger_unlock:
0645     mutex_unlock(&mpu3050->lock);
0646     iio_trigger_notify_done(indio_dev->trig);
0647 
0648     return IRQ_HANDLED;
0649 }
0650 
0651 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
0652 {
0653     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0654 
0655     pm_runtime_get_sync(mpu3050->dev);
0656 
0657     /* Unless we have OUR trigger active, run at full speed */
0658     if (!mpu3050->hw_irq_trigger)
0659         return mpu3050_set_8khz_samplerate(mpu3050);
0660 
0661     return 0;
0662 }
0663 
0664 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
0665 {
0666     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0667 
0668     pm_runtime_mark_last_busy(mpu3050->dev);
0669     pm_runtime_put_autosuspend(mpu3050->dev);
0670 
0671     return 0;
0672 }
0673 
0674 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
0675     .preenable = mpu3050_buffer_preenable,
0676     .postdisable = mpu3050_buffer_postdisable,
0677 };
0678 
0679 static const struct iio_mount_matrix *
0680 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
0681              const struct iio_chan_spec *chan)
0682 {
0683     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0684 
0685     return &mpu3050->orientation;
0686 }
0687 
0688 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
0689     IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
0690     { },
0691 };
0692 
0693 #define MPU3050_AXIS_CHANNEL(axis, index)               \
0694     {                               \
0695         .type = IIO_ANGL_VEL,                   \
0696         .modified = 1,                      \
0697         .channel2 = IIO_MOD_##axis,             \
0698         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0699             BIT(IIO_CHAN_INFO_CALIBBIAS),           \
0700         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0701         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
0702         .ext_info = mpu3050_ext_info,               \
0703         .scan_index = index,                    \
0704         .scan_type = {                      \
0705             .sign = 's',                    \
0706             .realbits = 16,                 \
0707             .storagebits = 16,              \
0708             .endianness = IIO_BE,               \
0709         },                          \
0710     }
0711 
0712 static const struct iio_chan_spec mpu3050_channels[] = {
0713     {
0714         .type = IIO_TEMP,
0715         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0716                       BIT(IIO_CHAN_INFO_SCALE) |
0717                       BIT(IIO_CHAN_INFO_OFFSET),
0718         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0719         .scan_index = 0,
0720         .scan_type = {
0721             .sign = 's',
0722             .realbits = 16,
0723             .storagebits = 16,
0724             .endianness = IIO_BE,
0725         },
0726     },
0727     MPU3050_AXIS_CHANNEL(X, 1),
0728     MPU3050_AXIS_CHANNEL(Y, 2),
0729     MPU3050_AXIS_CHANNEL(Z, 3),
0730     IIO_CHAN_SOFT_TIMESTAMP(4),
0731 };
0732 
0733 /* Four channels apart from timestamp, scan mask = 0x0f */
0734 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
0735 
0736 /*
0737  * These are just the hardcoded factors resulting from the more elaborate
0738  * calculations done with fractions in the scale raw get/set functions.
0739  */
0740 static IIO_CONST_ATTR(anglevel_scale_available,
0741               "0.000122070 "
0742               "0.000274658 "
0743               "0.000518798 "
0744               "0.001068115");
0745 
0746 static struct attribute *mpu3050_attributes[] = {
0747     &iio_const_attr_anglevel_scale_available.dev_attr.attr,
0748     NULL,
0749 };
0750 
0751 static const struct attribute_group mpu3050_attribute_group = {
0752     .attrs = mpu3050_attributes,
0753 };
0754 
0755 static const struct iio_info mpu3050_info = {
0756     .read_raw = mpu3050_read_raw,
0757     .write_raw = mpu3050_write_raw,
0758     .attrs = &mpu3050_attribute_group,
0759 };
0760 
0761 /**
0762  * mpu3050_read_mem() - read MPU-3050 internal memory
0763  * @mpu3050: device to read from
0764  * @bank: target bank
0765  * @addr: target address
0766  * @len: number of bytes
0767  * @buf: the buffer to store the read bytes in
0768  */
0769 static int mpu3050_read_mem(struct mpu3050 *mpu3050,
0770                 u8 bank,
0771                 u8 addr,
0772                 u8 len,
0773                 u8 *buf)
0774 {
0775     int ret;
0776 
0777     ret = regmap_write(mpu3050->map,
0778                MPU3050_BANK_SEL,
0779                bank);
0780     if (ret)
0781         return ret;
0782 
0783     ret = regmap_write(mpu3050->map,
0784                MPU3050_MEM_START_ADDR,
0785                addr);
0786     if (ret)
0787         return ret;
0788 
0789     return regmap_bulk_read(mpu3050->map,
0790                 MPU3050_MEM_R_W,
0791                 buf,
0792                 len);
0793 }
0794 
0795 static int mpu3050_hw_init(struct mpu3050 *mpu3050)
0796 {
0797     int ret;
0798     __le64 otp_le;
0799     u64 otp;
0800 
0801     /* Reset */
0802     ret = regmap_update_bits(mpu3050->map,
0803                  MPU3050_PWR_MGM,
0804                  MPU3050_PWR_MGM_RESET,
0805                  MPU3050_PWR_MGM_RESET);
0806     if (ret)
0807         return ret;
0808 
0809     /* Turn on the PLL */
0810     ret = regmap_update_bits(mpu3050->map,
0811                  MPU3050_PWR_MGM,
0812                  MPU3050_PWR_MGM_CLKSEL_MASK,
0813                  MPU3050_PWR_MGM_PLL_Z);
0814     if (ret)
0815         return ret;
0816 
0817     /* Disable IRQs */
0818     ret = regmap_write(mpu3050->map,
0819                MPU3050_INT_CFG,
0820                0);
0821     if (ret)
0822         return ret;
0823 
0824     /* Read out the 8 bytes of OTP (one-time-programmable) memory */
0825     ret = mpu3050_read_mem(mpu3050,
0826                    (MPU3050_MEM_PRFTCH |
0827                 MPU3050_MEM_USER_BANK |
0828                 MPU3050_MEM_OTP_BANK_0),
0829                    0,
0830                    sizeof(otp_le),
0831                    (u8 *)&otp_le);
0832     if (ret)
0833         return ret;
0834 
0835     /* This is device-unique data so it goes into the entropy pool */
0836     add_device_randomness(&otp_le, sizeof(otp_le));
0837 
0838     otp = le64_to_cpu(otp_le);
0839 
0840     dev_info(mpu3050->dev,
0841          "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, "
0842          "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n",
0843          /* Die ID, bits 0-12 */
0844          FIELD_GET(GENMASK_ULL(12, 0), otp),
0845          /* Wafer ID, bits 13-17 */
0846          FIELD_GET(GENMASK_ULL(17, 13), otp),
0847          /* A lot ID, bits 18-33 */
0848          FIELD_GET(GENMASK_ULL(33, 18), otp),
0849          /* W lot ID, bits 34-45 */
0850          FIELD_GET(GENMASK_ULL(45, 34), otp),
0851          /* WP ID, bits 47-49 */
0852          FIELD_GET(GENMASK_ULL(49, 47), otp),
0853          /* rev ID, bits 50-55 */
0854          FIELD_GET(GENMASK_ULL(55, 50), otp));
0855 
0856     return 0;
0857 }
0858 
0859 static int mpu3050_power_up(struct mpu3050 *mpu3050)
0860 {
0861     int ret;
0862 
0863     ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
0864     if (ret) {
0865         dev_err(mpu3050->dev, "cannot enable regulators\n");
0866         return ret;
0867     }
0868     /*
0869      * 20-100 ms start-up time for register read/write according to
0870      * the datasheet, be on the safe side and wait 200 ms.
0871      */
0872     msleep(200);
0873 
0874     /* Take device out of sleep mode */
0875     ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
0876                  MPU3050_PWR_MGM_SLEEP, 0);
0877     if (ret) {
0878         regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
0879         dev_err(mpu3050->dev, "error setting power mode\n");
0880         return ret;
0881     }
0882     usleep_range(10000, 20000);
0883 
0884     return 0;
0885 }
0886 
0887 static int mpu3050_power_down(struct mpu3050 *mpu3050)
0888 {
0889     int ret;
0890 
0891     /*
0892      * Put MPU-3050 into sleep mode before cutting regulators.
0893      * This is important, because we may not be the sole user
0894      * of the regulator so the power may stay on after this, and
0895      * then we would be wasting power unless we go to sleep mode
0896      * first.
0897      */
0898     ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
0899                  MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
0900     if (ret)
0901         dev_err(mpu3050->dev, "error putting to sleep\n");
0902 
0903     ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
0904     if (ret)
0905         dev_err(mpu3050->dev, "error disabling regulators\n");
0906 
0907     return 0;
0908 }
0909 
0910 static irqreturn_t mpu3050_irq_handler(int irq, void *p)
0911 {
0912     struct iio_trigger *trig = p;
0913     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0914     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0915 
0916     if (!mpu3050->hw_irq_trigger)
0917         return IRQ_NONE;
0918 
0919     /* Get the time stamp as close in time as possible */
0920     mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
0921 
0922     return IRQ_WAKE_THREAD;
0923 }
0924 
0925 static irqreturn_t mpu3050_irq_thread(int irq, void *p)
0926 {
0927     struct iio_trigger *trig = p;
0928     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0929     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0930     unsigned int val;
0931     int ret;
0932 
0933     /* ACK IRQ and check if it was from us */
0934     ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
0935     if (ret) {
0936         dev_err(mpu3050->dev, "error reading IRQ status\n");
0937         return IRQ_HANDLED;
0938     }
0939     if (!(val & MPU3050_INT_STATUS_RAW_RDY))
0940         return IRQ_NONE;
0941 
0942     iio_trigger_poll_chained(p);
0943 
0944     return IRQ_HANDLED;
0945 }
0946 
0947 /**
0948  * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
0949  * @trig: trigger instance
0950  * @enable: true if trigger should be enabled, false to disable
0951  */
0952 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
0953                       bool enable)
0954 {
0955     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0956     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
0957     unsigned int val;
0958     int ret;
0959 
0960     /* Disabling trigger: disable interrupt and return */
0961     if (!enable) {
0962         /* Disable all interrupts */
0963         ret = regmap_write(mpu3050->map,
0964                    MPU3050_INT_CFG,
0965                    0);
0966         if (ret)
0967             dev_err(mpu3050->dev, "error disabling IRQ\n");
0968 
0969         /* Clear IRQ flag */
0970         ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
0971         if (ret)
0972             dev_err(mpu3050->dev, "error clearing IRQ status\n");
0973 
0974         /* Disable all things in the FIFO and reset it */
0975         ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
0976         if (ret)
0977             dev_err(mpu3050->dev, "error disabling FIFO\n");
0978 
0979         ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
0980                    MPU3050_USR_CTRL_FIFO_RST);
0981         if (ret)
0982             dev_err(mpu3050->dev, "error resetting FIFO\n");
0983 
0984         pm_runtime_mark_last_busy(mpu3050->dev);
0985         pm_runtime_put_autosuspend(mpu3050->dev);
0986         mpu3050->hw_irq_trigger = false;
0987 
0988         return 0;
0989     } else {
0990         /* Else we're enabling the trigger from this point */
0991         pm_runtime_get_sync(mpu3050->dev);
0992         mpu3050->hw_irq_trigger = true;
0993 
0994         /* Disable all things in the FIFO */
0995         ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
0996         if (ret)
0997             return ret;
0998 
0999         /* Reset and enable the FIFO */
1000         ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
1001                      MPU3050_USR_CTRL_FIFO_EN |
1002                      MPU3050_USR_CTRL_FIFO_RST,
1003                      MPU3050_USR_CTRL_FIFO_EN |
1004                      MPU3050_USR_CTRL_FIFO_RST);
1005         if (ret)
1006             return ret;
1007 
1008         mpu3050->pending_fifo_footer = false;
1009 
1010         /* Turn on the FIFO for temp+X+Y+Z */
1011         ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
1012                    MPU3050_FIFO_EN_TEMP_OUT |
1013                    MPU3050_FIFO_EN_GYRO_XOUT |
1014                    MPU3050_FIFO_EN_GYRO_YOUT |
1015                    MPU3050_FIFO_EN_GYRO_ZOUT |
1016                    MPU3050_FIFO_EN_FOOTER);
1017         if (ret)
1018             return ret;
1019 
1020         /* Configure the sample engine */
1021         ret = mpu3050_start_sampling(mpu3050);
1022         if (ret)
1023             return ret;
1024 
1025         /* Clear IRQ flag */
1026         ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1027         if (ret)
1028             dev_err(mpu3050->dev, "error clearing IRQ status\n");
1029 
1030         /* Give us interrupts whenever there is new data ready */
1031         val = MPU3050_INT_RAW_RDY_EN;
1032 
1033         if (mpu3050->irq_actl)
1034             val |= MPU3050_INT_ACTL;
1035         if (mpu3050->irq_latch)
1036             val |= MPU3050_INT_LATCH_EN;
1037         if (mpu3050->irq_opendrain)
1038             val |= MPU3050_INT_OPEN;
1039 
1040         ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1041         if (ret)
1042             return ret;
1043     }
1044 
1045     return 0;
1046 }
1047 
1048 static const struct iio_trigger_ops mpu3050_trigger_ops = {
1049     .set_trigger_state = mpu3050_drdy_trigger_set_state,
1050 };
1051 
1052 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1053 {
1054     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1055     struct device *dev = mpu3050->dev;
1056     unsigned long irq_trig;
1057     int ret;
1058 
1059     mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1060                            "%s-dev%d",
1061                            indio_dev->name,
1062                            iio_device_id(indio_dev));
1063     if (!mpu3050->trig)
1064         return -ENOMEM;
1065 
1066     /* Check if IRQ is open drain */
1067     mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain");
1068 
1069     irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1070     /*
1071      * Configure the interrupt generator hardware to supply whatever
1072      * the interrupt is configured for, edges low/high level low/high,
1073      * we can provide it all.
1074      */
1075     switch (irq_trig) {
1076     case IRQF_TRIGGER_RISING:
1077         dev_info(&indio_dev->dev,
1078              "pulse interrupts on the rising edge\n");
1079         break;
1080     case IRQF_TRIGGER_FALLING:
1081         mpu3050->irq_actl = true;
1082         dev_info(&indio_dev->dev,
1083              "pulse interrupts on the falling edge\n");
1084         break;
1085     case IRQF_TRIGGER_HIGH:
1086         mpu3050->irq_latch = true;
1087         dev_info(&indio_dev->dev,
1088              "interrupts active high level\n");
1089         /*
1090          * With level IRQs, we mask the IRQ until it is processed,
1091          * but with edge IRQs (pulses) we can queue several interrupts
1092          * in the top half.
1093          */
1094         irq_trig |= IRQF_ONESHOT;
1095         break;
1096     case IRQF_TRIGGER_LOW:
1097         mpu3050->irq_latch = true;
1098         mpu3050->irq_actl = true;
1099         irq_trig |= IRQF_ONESHOT;
1100         dev_info(&indio_dev->dev,
1101              "interrupts active low level\n");
1102         break;
1103     default:
1104         /* This is the most preferred mode, if possible */
1105         dev_err(&indio_dev->dev,
1106             "unsupported IRQ trigger specified (%lx), enforce "
1107             "rising edge\n", irq_trig);
1108         irq_trig = IRQF_TRIGGER_RISING;
1109         break;
1110     }
1111 
1112     /* An open drain line can be shared with several devices */
1113     if (mpu3050->irq_opendrain)
1114         irq_trig |= IRQF_SHARED;
1115 
1116     ret = request_threaded_irq(irq,
1117                    mpu3050_irq_handler,
1118                    mpu3050_irq_thread,
1119                    irq_trig,
1120                    mpu3050->trig->name,
1121                    mpu3050->trig);
1122     if (ret) {
1123         dev_err(dev, "can't get IRQ %d, error %d\n", irq, ret);
1124         return ret;
1125     }
1126 
1127     mpu3050->irq = irq;
1128     mpu3050->trig->dev.parent = dev;
1129     mpu3050->trig->ops = &mpu3050_trigger_ops;
1130     iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1131 
1132     ret = iio_trigger_register(mpu3050->trig);
1133     if (ret)
1134         return ret;
1135 
1136     indio_dev->trig = iio_trigger_get(mpu3050->trig);
1137 
1138     return 0;
1139 }
1140 
1141 int mpu3050_common_probe(struct device *dev,
1142              struct regmap *map,
1143              int irq,
1144              const char *name)
1145 {
1146     struct iio_dev *indio_dev;
1147     struct mpu3050 *mpu3050;
1148     unsigned int val;
1149     int ret;
1150 
1151     indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1152     if (!indio_dev)
1153         return -ENOMEM;
1154     mpu3050 = iio_priv(indio_dev);
1155 
1156     mpu3050->dev = dev;
1157     mpu3050->map = map;
1158     mutex_init(&mpu3050->lock);
1159     /* Default fullscale: 2000 degrees per second */
1160     mpu3050->fullscale = FS_2000_DPS;
1161     /* 1 kHz, divide by 100, default frequency = 10 Hz */
1162     mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1163     mpu3050->divisor = 99;
1164 
1165     /* Read the mounting matrix, if present */
1166     ret = iio_read_mount_matrix(dev, &mpu3050->orientation);
1167     if (ret)
1168         return ret;
1169 
1170     /* Fetch and turn on regulators */
1171     mpu3050->regs[0].supply = mpu3050_reg_vdd;
1172     mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1173     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1174                       mpu3050->regs);
1175     if (ret) {
1176         dev_err(dev, "Cannot get regulators\n");
1177         return ret;
1178     }
1179 
1180     ret = mpu3050_power_up(mpu3050);
1181     if (ret)
1182         return ret;
1183 
1184     ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1185     if (ret) {
1186         dev_err(dev, "could not read device ID\n");
1187         ret = -ENODEV;
1188 
1189         goto err_power_down;
1190     }
1191 
1192     if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
1193         dev_err(dev, "unsupported chip id %02x\n",
1194                 (u8)(val & MPU3050_CHIP_ID_MASK));
1195         ret = -ENODEV;
1196         goto err_power_down;
1197     }
1198 
1199     ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1200     if (ret) {
1201         dev_err(dev, "could not read device ID\n");
1202         ret = -ENODEV;
1203 
1204         goto err_power_down;
1205     }
1206     dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1207          ((val >> 4) & 0xf), (val & 0xf));
1208 
1209     ret = mpu3050_hw_init(mpu3050);
1210     if (ret)
1211         goto err_power_down;
1212 
1213     indio_dev->channels = mpu3050_channels;
1214     indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1215     indio_dev->info = &mpu3050_info;
1216     indio_dev->available_scan_masks = mpu3050_scan_masks;
1217     indio_dev->modes = INDIO_DIRECT_MODE;
1218     indio_dev->name = name;
1219 
1220     ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1221                      mpu3050_trigger_handler,
1222                      &mpu3050_buffer_setup_ops);
1223     if (ret) {
1224         dev_err(dev, "triggered buffer setup failed\n");
1225         goto err_power_down;
1226     }
1227 
1228     ret = iio_device_register(indio_dev);
1229     if (ret) {
1230         dev_err(dev, "device register failed\n");
1231         goto err_cleanup_buffer;
1232     }
1233 
1234     dev_set_drvdata(dev, indio_dev);
1235 
1236     /* Check if we have an assigned IRQ to use as trigger */
1237     if (irq) {
1238         ret = mpu3050_trigger_probe(indio_dev, irq);
1239         if (ret)
1240             dev_err(dev, "failed to register trigger\n");
1241     }
1242 
1243     /* Enable runtime PM */
1244     pm_runtime_get_noresume(dev);
1245     pm_runtime_set_active(dev);
1246     pm_runtime_enable(dev);
1247     /*
1248      * Set autosuspend to two orders of magnitude larger than the
1249      * start-up time. 100ms start-up time means 10000ms autosuspend,
1250      * i.e. 10 seconds.
1251      */
1252     pm_runtime_set_autosuspend_delay(dev, 10000);
1253     pm_runtime_use_autosuspend(dev);
1254     pm_runtime_put(dev);
1255 
1256     return 0;
1257 
1258 err_cleanup_buffer:
1259     iio_triggered_buffer_cleanup(indio_dev);
1260 err_power_down:
1261     mpu3050_power_down(mpu3050);
1262 
1263     return ret;
1264 }
1265 
1266 void mpu3050_common_remove(struct device *dev)
1267 {
1268     struct iio_dev *indio_dev = dev_get_drvdata(dev);
1269     struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1270 
1271     pm_runtime_get_sync(dev);
1272     pm_runtime_put_noidle(dev);
1273     pm_runtime_disable(dev);
1274     iio_triggered_buffer_cleanup(indio_dev);
1275     if (mpu3050->irq)
1276         free_irq(mpu3050->irq, mpu3050);
1277     iio_device_unregister(indio_dev);
1278     mpu3050_power_down(mpu3050);
1279 }
1280 
1281 static int mpu3050_runtime_suspend(struct device *dev)
1282 {
1283     return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1284 }
1285 
1286 static int mpu3050_runtime_resume(struct device *dev)
1287 {
1288     return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1289 }
1290 
1291 DEFINE_RUNTIME_DEV_PM_OPS(mpu3050_dev_pm_ops, mpu3050_runtime_suspend,
1292               mpu3050_runtime_resume, NULL);
1293 MODULE_AUTHOR("Linus Walleij");
1294 MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1295 MODULE_LICENSE("GPL");
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