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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for NXP FXAS21002C Gyroscope - Core
0004  *
0005  * Copyright (C) 2019 Linaro Ltd.
0006  */
0007 
0008 #include <linux/interrupt.h>
0009 #include <linux/module.h>
0010 #include <linux/pm.h>
0011 #include <linux/pm_runtime.h>
0012 #include <linux/property.h>
0013 #include <linux/regmap.h>
0014 #include <linux/regulator/consumer.h>
0015 
0016 #include <linux/iio/events.h>
0017 #include <linux/iio/iio.h>
0018 #include <linux/iio/buffer.h>
0019 #include <linux/iio/sysfs.h>
0020 #include <linux/iio/trigger.h>
0021 #include <linux/iio/trigger_consumer.h>
0022 #include <linux/iio/triggered_buffer.h>
0023 
0024 #include "fxas21002c.h"
0025 
0026 #define FXAS21002C_CHIP_ID_1    0xD6
0027 #define FXAS21002C_CHIP_ID_2    0xD7
0028 
0029 enum fxas21002c_mode_state {
0030     FXAS21002C_MODE_STANDBY,
0031     FXAS21002C_MODE_READY,
0032     FXAS21002C_MODE_ACTIVE,
0033 };
0034 
0035 #define FXAS21002C_STANDBY_ACTIVE_TIME_MS   62
0036 #define FXAS21002C_READY_ACTIVE_TIME_MS     7
0037 
0038 #define FXAS21002C_ODR_LIST_MAX     10
0039 
0040 #define FXAS21002C_SCALE_FRACTIONAL 32
0041 #define FXAS21002C_RANGE_LIMIT_DOUBLE   2000
0042 
0043 #define FXAS21002C_AXIS_TO_REG(axis) (FXAS21002C_REG_OUT_X_MSB + ((axis) * 2))
0044 
0045 static const struct reg_field fxas21002c_reg_fields[] = {
0046     [F_DR_STATUS]       = REG_FIELD(FXAS21002C_REG_STATUS, 0, 7),
0047     [F_OUT_X_MSB]       = REG_FIELD(FXAS21002C_REG_OUT_X_MSB, 0, 7),
0048     [F_OUT_X_LSB]       = REG_FIELD(FXAS21002C_REG_OUT_X_LSB, 0, 7),
0049     [F_OUT_Y_MSB]       = REG_FIELD(FXAS21002C_REG_OUT_Y_MSB, 0, 7),
0050     [F_OUT_Y_LSB]       = REG_FIELD(FXAS21002C_REG_OUT_Y_LSB, 0, 7),
0051     [F_OUT_Z_MSB]       = REG_FIELD(FXAS21002C_REG_OUT_Z_MSB, 0, 7),
0052     [F_OUT_Z_LSB]       = REG_FIELD(FXAS21002C_REG_OUT_Z_LSB, 0, 7),
0053     [F_ZYX_OW]      = REG_FIELD(FXAS21002C_REG_DR_STATUS, 7, 7),
0054     [F_Z_OW]        = REG_FIELD(FXAS21002C_REG_DR_STATUS, 6, 6),
0055     [F_Y_OW]        = REG_FIELD(FXAS21002C_REG_DR_STATUS, 5, 5),
0056     [F_X_OW]        = REG_FIELD(FXAS21002C_REG_DR_STATUS, 4, 4),
0057     [F_ZYX_DR]      = REG_FIELD(FXAS21002C_REG_DR_STATUS, 3, 3),
0058     [F_Z_DR]        = REG_FIELD(FXAS21002C_REG_DR_STATUS, 2, 2),
0059     [F_Y_DR]        = REG_FIELD(FXAS21002C_REG_DR_STATUS, 1, 1),
0060     [F_X_DR]        = REG_FIELD(FXAS21002C_REG_DR_STATUS, 0, 0),
0061     [F_OVF]         = REG_FIELD(FXAS21002C_REG_F_STATUS, 7, 7),
0062     [F_WMKF]        = REG_FIELD(FXAS21002C_REG_F_STATUS, 6, 6),
0063     [F_CNT]         = REG_FIELD(FXAS21002C_REG_F_STATUS, 0, 5),
0064     [F_MODE]        = REG_FIELD(FXAS21002C_REG_F_SETUP, 6, 7),
0065     [F_WMRK]        = REG_FIELD(FXAS21002C_REG_F_SETUP, 0, 5),
0066     [F_EVENT]       = REG_FIELD(FXAS21002C_REG_F_EVENT, 5, 5),
0067     [FE_TIME]       = REG_FIELD(FXAS21002C_REG_F_EVENT, 0, 4),
0068     [F_BOOTEND]     = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 3, 3),
0069     [F_SRC_FIFO]        = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 2, 2),
0070     [F_SRC_RT]      = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 1, 1),
0071     [F_SRC_DRDY]        = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 0, 0),
0072     [F_WHO_AM_I]        = REG_FIELD(FXAS21002C_REG_WHO_AM_I, 0, 7),
0073     [F_BW]          = REG_FIELD(FXAS21002C_REG_CTRL0, 6, 7),
0074     [F_SPIW]        = REG_FIELD(FXAS21002C_REG_CTRL0, 5, 5),
0075     [F_SEL]         = REG_FIELD(FXAS21002C_REG_CTRL0, 3, 4),
0076     [F_HPF_EN]      = REG_FIELD(FXAS21002C_REG_CTRL0, 2, 2),
0077     [F_FS]          = REG_FIELD(FXAS21002C_REG_CTRL0, 0, 1),
0078     [F_ELE]         = REG_FIELD(FXAS21002C_REG_RT_CFG, 3, 3),
0079     [F_ZTEFE]       = REG_FIELD(FXAS21002C_REG_RT_CFG, 2, 2),
0080     [F_YTEFE]       = REG_FIELD(FXAS21002C_REG_RT_CFG, 1, 1),
0081     [F_XTEFE]       = REG_FIELD(FXAS21002C_REG_RT_CFG, 0, 0),
0082     [F_EA]          = REG_FIELD(FXAS21002C_REG_RT_SRC, 6, 6),
0083     [F_ZRT]         = REG_FIELD(FXAS21002C_REG_RT_SRC, 5, 5),
0084     [F_ZRT_POL]     = REG_FIELD(FXAS21002C_REG_RT_SRC, 4, 4),
0085     [F_YRT]         = REG_FIELD(FXAS21002C_REG_RT_SRC, 3, 3),
0086     [F_YRT_POL]     = REG_FIELD(FXAS21002C_REG_RT_SRC, 2, 2),
0087     [F_XRT]         = REG_FIELD(FXAS21002C_REG_RT_SRC, 1, 1),
0088     [F_XRT_POL]     = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 0),
0089     [F_DBCNTM]      = REG_FIELD(FXAS21002C_REG_RT_THS, 7, 7),
0090     [F_THS]         = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 6),
0091     [F_RT_COUNT]        = REG_FIELD(FXAS21002C_REG_RT_COUNT, 0, 7),
0092     [F_TEMP]        = REG_FIELD(FXAS21002C_REG_TEMP, 0, 7),
0093     [F_RST]         = REG_FIELD(FXAS21002C_REG_CTRL1, 6, 6),
0094     [F_ST]          = REG_FIELD(FXAS21002C_REG_CTRL1, 5, 5),
0095     [F_DR]          = REG_FIELD(FXAS21002C_REG_CTRL1, 2, 4),
0096     [F_ACTIVE]      = REG_FIELD(FXAS21002C_REG_CTRL1, 1, 1),
0097     [F_READY]       = REG_FIELD(FXAS21002C_REG_CTRL1, 0, 0),
0098     [F_INT_CFG_FIFO]    = REG_FIELD(FXAS21002C_REG_CTRL2, 7, 7),
0099     [F_INT_EN_FIFO]     = REG_FIELD(FXAS21002C_REG_CTRL2, 6, 6),
0100     [F_INT_CFG_RT]      = REG_FIELD(FXAS21002C_REG_CTRL2, 5, 5),
0101     [F_INT_EN_RT]       = REG_FIELD(FXAS21002C_REG_CTRL2, 4, 4),
0102     [F_INT_CFG_DRDY]    = REG_FIELD(FXAS21002C_REG_CTRL2, 3, 3),
0103     [F_INT_EN_DRDY]     = REG_FIELD(FXAS21002C_REG_CTRL2, 2, 2),
0104     [F_IPOL]        = REG_FIELD(FXAS21002C_REG_CTRL2, 1, 1),
0105     [F_PP_OD]       = REG_FIELD(FXAS21002C_REG_CTRL2, 0, 0),
0106     [F_WRAPTOONE]       = REG_FIELD(FXAS21002C_REG_CTRL3, 3, 3),
0107     [F_EXTCTRLEN]       = REG_FIELD(FXAS21002C_REG_CTRL3, 2, 2),
0108     [F_FS_DOUBLE]       = REG_FIELD(FXAS21002C_REG_CTRL3, 0, 0),
0109 };
0110 
0111 static const int fxas21002c_odr_values[] = {
0112     800, 400, 200, 100, 50, 25, 12, 12
0113 };
0114 
0115 /*
0116  * These values are taken from the low-pass filter cutoff frequency calculated
0117  * ODR * 0.lpf_values. So, for ODR = 800Hz with a lpf value = 0.32
0118  * => LPF cutoff frequency = 800 * 0.32 = 256 Hz
0119  */
0120 static const int fxas21002c_lpf_values[] = {
0121     32, 16, 8
0122 };
0123 
0124 /*
0125  * These values are taken from the high-pass filter cutoff frequency calculated
0126  * ODR * 0.0hpf_values. So, for ODR = 800Hz with a hpf value = 0.018750
0127  * => HPF cutoff frequency = 800 * 0.018750 = 15 Hz
0128  */
0129 static const int fxas21002c_hpf_values[] = {
0130     18750, 9625, 4875, 2475
0131 };
0132 
0133 static const int fxas21002c_range_values[] = {
0134     4000, 2000, 1000, 500, 250
0135 };
0136 
0137 struct fxas21002c_data {
0138     u8 chip_id;
0139     enum fxas21002c_mode_state mode;
0140     enum fxas21002c_mode_state prev_mode;
0141 
0142     struct mutex lock;      /* serialize data access */
0143     struct regmap *regmap;
0144     struct regmap_field *regmap_fields[F_MAX_FIELDS];
0145     struct iio_trigger *dready_trig;
0146     s64 timestamp;
0147     int irq;
0148 
0149     struct regulator *vdd;
0150     struct regulator *vddio;
0151 
0152     /*
0153      * DMA (thus cache coherency maintenance) may require the
0154      * transfer buffers live in their own cache lines.
0155      */
0156     s16 buffer[8] __aligned(IIO_DMA_MINALIGN);
0157 };
0158 
0159 enum fxas21002c_channel_index {
0160     CHANNEL_SCAN_INDEX_X,
0161     CHANNEL_SCAN_INDEX_Y,
0162     CHANNEL_SCAN_INDEX_Z,
0163     CHANNEL_SCAN_MAX,
0164 };
0165 
0166 static int fxas21002c_odr_hz_from_value(struct fxas21002c_data *data, u8 value)
0167 {
0168     int odr_value_max = ARRAY_SIZE(fxas21002c_odr_values) - 1;
0169 
0170     value = min_t(u8, value, odr_value_max);
0171 
0172     return fxas21002c_odr_values[value];
0173 }
0174 
0175 static int fxas21002c_odr_value_from_hz(struct fxas21002c_data *data,
0176                     unsigned int hz)
0177 {
0178     int odr_table_size = ARRAY_SIZE(fxas21002c_odr_values);
0179     int i;
0180 
0181     for (i = 0; i < odr_table_size; i++)
0182         if (fxas21002c_odr_values[i] == hz)
0183             return i;
0184 
0185     return -EINVAL;
0186 }
0187 
0188 static int fxas21002c_lpf_bw_from_value(struct fxas21002c_data *data, u8 value)
0189 {
0190     int lpf_value_max = ARRAY_SIZE(fxas21002c_lpf_values) - 1;
0191 
0192     value = min_t(u8, value, lpf_value_max);
0193 
0194     return fxas21002c_lpf_values[value];
0195 }
0196 
0197 static int fxas21002c_lpf_value_from_bw(struct fxas21002c_data *data,
0198                     unsigned int hz)
0199 {
0200     int lpf_table_size = ARRAY_SIZE(fxas21002c_lpf_values);
0201     int i;
0202 
0203     for (i = 0; i < lpf_table_size; i++)
0204         if (fxas21002c_lpf_values[i] == hz)
0205             return i;
0206 
0207     return -EINVAL;
0208 }
0209 
0210 static int fxas21002c_hpf_sel_from_value(struct fxas21002c_data *data, u8 value)
0211 {
0212     int hpf_value_max = ARRAY_SIZE(fxas21002c_hpf_values) - 1;
0213 
0214     value = min_t(u8, value, hpf_value_max);
0215 
0216     return fxas21002c_hpf_values[value];
0217 }
0218 
0219 static int fxas21002c_hpf_value_from_sel(struct fxas21002c_data *data,
0220                      unsigned int hz)
0221 {
0222     int hpf_table_size = ARRAY_SIZE(fxas21002c_hpf_values);
0223     int i;
0224 
0225     for (i = 0; i < hpf_table_size; i++)
0226         if (fxas21002c_hpf_values[i] == hz)
0227             return i;
0228 
0229     return -EINVAL;
0230 }
0231 
0232 static int fxas21002c_range_fs_from_value(struct fxas21002c_data *data,
0233                       u8 value)
0234 {
0235     int range_value_max = ARRAY_SIZE(fxas21002c_range_values) - 1;
0236     unsigned int fs_double;
0237     int ret;
0238 
0239     /* We need to check if FS_DOUBLE is enabled to offset the value */
0240     ret = regmap_field_read(data->regmap_fields[F_FS_DOUBLE], &fs_double);
0241     if (ret < 0)
0242         return ret;
0243 
0244     if (!fs_double)
0245         value += 1;
0246 
0247     value = min_t(u8, value, range_value_max);
0248 
0249     return fxas21002c_range_values[value];
0250 }
0251 
0252 static int fxas21002c_range_value_from_fs(struct fxas21002c_data *data,
0253                       unsigned int range)
0254 {
0255     int range_table_size = ARRAY_SIZE(fxas21002c_range_values);
0256     bool found = false;
0257     int fs_double = 0;
0258     int ret;
0259     int i;
0260 
0261     for (i = 0; i < range_table_size; i++)
0262         if (fxas21002c_range_values[i] == range) {
0263             found = true;
0264             break;
0265         }
0266 
0267     if (!found)
0268         return -EINVAL;
0269 
0270     if (range > FXAS21002C_RANGE_LIMIT_DOUBLE)
0271         fs_double = 1;
0272 
0273     ret = regmap_field_write(data->regmap_fields[F_FS_DOUBLE], fs_double);
0274     if (ret < 0)
0275         return ret;
0276 
0277     return i;
0278 }
0279 
0280 static int fxas21002c_mode_get(struct fxas21002c_data *data)
0281 {
0282     unsigned int active;
0283     unsigned int ready;
0284     int ret;
0285 
0286     ret = regmap_field_read(data->regmap_fields[F_ACTIVE], &active);
0287     if (ret < 0)
0288         return ret;
0289     if (active)
0290         return FXAS21002C_MODE_ACTIVE;
0291 
0292     ret = regmap_field_read(data->regmap_fields[F_READY], &ready);
0293     if (ret < 0)
0294         return ret;
0295     if (ready)
0296         return FXAS21002C_MODE_READY;
0297 
0298     return FXAS21002C_MODE_STANDBY;
0299 }
0300 
0301 static int fxas21002c_mode_set(struct fxas21002c_data *data,
0302                    enum fxas21002c_mode_state mode)
0303 {
0304     int ret;
0305 
0306     if (mode == data->mode)
0307         return 0;
0308 
0309     if (mode == FXAS21002C_MODE_READY)
0310         ret = regmap_field_write(data->regmap_fields[F_READY], 1);
0311     else
0312         ret = regmap_field_write(data->regmap_fields[F_READY], 0);
0313     if (ret < 0)
0314         return ret;
0315 
0316     if (mode == FXAS21002C_MODE_ACTIVE)
0317         ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 1);
0318     else
0319         ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 0);
0320     if (ret < 0)
0321         return ret;
0322 
0323     /* if going to active wait the setup times */
0324     if (mode == FXAS21002C_MODE_ACTIVE &&
0325         data->mode == FXAS21002C_MODE_STANDBY)
0326         msleep_interruptible(FXAS21002C_STANDBY_ACTIVE_TIME_MS);
0327 
0328     if (data->mode == FXAS21002C_MODE_READY)
0329         msleep_interruptible(FXAS21002C_READY_ACTIVE_TIME_MS);
0330 
0331     data->prev_mode = data->mode;
0332     data->mode = mode;
0333 
0334     return ret;
0335 }
0336 
0337 static int fxas21002c_write(struct fxas21002c_data *data,
0338                 enum fxas21002c_fields field, int bits)
0339 {
0340     int actual_mode;
0341     int ret;
0342 
0343     mutex_lock(&data->lock);
0344 
0345     actual_mode = fxas21002c_mode_get(data);
0346     if (actual_mode < 0) {
0347         ret = actual_mode;
0348         goto out_unlock;
0349     }
0350 
0351     ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
0352     if (ret < 0)
0353         goto out_unlock;
0354 
0355     ret = regmap_field_write(data->regmap_fields[field], bits);
0356     if (ret < 0)
0357         goto out_unlock;
0358 
0359     ret = fxas21002c_mode_set(data, data->prev_mode);
0360 
0361 out_unlock:
0362     mutex_unlock(&data->lock);
0363 
0364     return ret;
0365 }
0366 
0367 static int  fxas21002c_pm_get(struct fxas21002c_data *data)
0368 {
0369     return pm_runtime_resume_and_get(regmap_get_device(data->regmap));
0370 }
0371 
0372 static int  fxas21002c_pm_put(struct fxas21002c_data *data)
0373 {
0374     struct device *dev = regmap_get_device(data->regmap);
0375 
0376     pm_runtime_mark_last_busy(dev);
0377 
0378     return pm_runtime_put_autosuspend(dev);
0379 }
0380 
0381 static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val)
0382 {
0383     struct device *dev = regmap_get_device(data->regmap);
0384     unsigned int temp;
0385     int ret;
0386 
0387     mutex_lock(&data->lock);
0388     ret = fxas21002c_pm_get(data);
0389     if (ret < 0)
0390         goto data_unlock;
0391 
0392     ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp);
0393     if (ret < 0) {
0394         dev_err(dev, "failed to read temp: %d\n", ret);
0395         fxas21002c_pm_put(data);
0396         goto data_unlock;
0397     }
0398 
0399     *val = sign_extend32(temp, 7);
0400 
0401     ret = fxas21002c_pm_put(data);
0402     if (ret < 0)
0403         goto data_unlock;
0404 
0405     ret = IIO_VAL_INT;
0406 
0407 data_unlock:
0408     mutex_unlock(&data->lock);
0409 
0410     return ret;
0411 }
0412 
0413 static int fxas21002c_axis_get(struct fxas21002c_data *data,
0414                    int index, int *val)
0415 {
0416     struct device *dev = regmap_get_device(data->regmap);
0417     __be16 axis_be;
0418     int ret;
0419 
0420     mutex_lock(&data->lock);
0421     ret = fxas21002c_pm_get(data);
0422     if (ret < 0)
0423         goto data_unlock;
0424 
0425     ret = regmap_bulk_read(data->regmap, FXAS21002C_AXIS_TO_REG(index),
0426                    &axis_be, sizeof(axis_be));
0427     if (ret < 0) {
0428         dev_err(dev, "failed to read axis: %d: %d\n", index, ret);
0429         fxas21002c_pm_put(data);
0430         goto data_unlock;
0431     }
0432 
0433     *val = sign_extend32(be16_to_cpu(axis_be), 15);
0434 
0435     ret = fxas21002c_pm_put(data);
0436     if (ret < 0)
0437         goto data_unlock;
0438 
0439     ret = IIO_VAL_INT;
0440 
0441 data_unlock:
0442     mutex_unlock(&data->lock);
0443 
0444     return ret;
0445 }
0446 
0447 static int fxas21002c_odr_get(struct fxas21002c_data *data, int *odr)
0448 {
0449     unsigned int odr_bits;
0450     int ret;
0451 
0452     mutex_lock(&data->lock);
0453     ret = regmap_field_read(data->regmap_fields[F_DR], &odr_bits);
0454     if (ret < 0)
0455         goto data_unlock;
0456 
0457     *odr = fxas21002c_odr_hz_from_value(data, odr_bits);
0458 
0459     ret = IIO_VAL_INT;
0460 
0461 data_unlock:
0462     mutex_unlock(&data->lock);
0463 
0464     return ret;
0465 }
0466 
0467 static int fxas21002c_odr_set(struct fxas21002c_data *data, int odr)
0468 {
0469     int odr_bits;
0470 
0471     odr_bits = fxas21002c_odr_value_from_hz(data, odr);
0472     if (odr_bits < 0)
0473         return odr_bits;
0474 
0475     return fxas21002c_write(data, F_DR, odr_bits);
0476 }
0477 
0478 static int fxas21002c_lpf_get(struct fxas21002c_data *data, int *val2)
0479 {
0480     unsigned int bw_bits;
0481     int ret;
0482 
0483     mutex_lock(&data->lock);
0484     ret = regmap_field_read(data->regmap_fields[F_BW], &bw_bits);
0485     if (ret < 0)
0486         goto data_unlock;
0487 
0488     *val2 = fxas21002c_lpf_bw_from_value(data, bw_bits) * 10000;
0489 
0490     ret = IIO_VAL_INT_PLUS_MICRO;
0491 
0492 data_unlock:
0493     mutex_unlock(&data->lock);
0494 
0495     return ret;
0496 }
0497 
0498 static int fxas21002c_lpf_set(struct fxas21002c_data *data, int bw)
0499 {
0500     int bw_bits;
0501     int odr;
0502     int ret;
0503 
0504     bw_bits = fxas21002c_lpf_value_from_bw(data, bw);
0505     if (bw_bits < 0)
0506         return bw_bits;
0507 
0508     /*
0509      * From table 33 of the device spec, for ODR = 25Hz and 12.5 value 0.08
0510      * is not allowed and for ODR = 12.5 value 0.16 is also not allowed
0511      */
0512     ret = fxas21002c_odr_get(data, &odr);
0513     if (ret < 0)
0514         return -EINVAL;
0515 
0516     if ((odr == 25 && bw_bits > 0x01) || (odr == 12 && bw_bits > 0))
0517         return -EINVAL;
0518 
0519     return fxas21002c_write(data, F_BW, bw_bits);
0520 }
0521 
0522 static int fxas21002c_hpf_get(struct fxas21002c_data *data, int *val2)
0523 {
0524     unsigned int sel_bits;
0525     int ret;
0526 
0527     mutex_lock(&data->lock);
0528     ret = regmap_field_read(data->regmap_fields[F_SEL], &sel_bits);
0529     if (ret < 0)
0530         goto data_unlock;
0531 
0532     *val2 = fxas21002c_hpf_sel_from_value(data, sel_bits);
0533 
0534     ret = IIO_VAL_INT_PLUS_MICRO;
0535 
0536 data_unlock:
0537     mutex_unlock(&data->lock);
0538 
0539     return ret;
0540 }
0541 
0542 static int fxas21002c_hpf_set(struct fxas21002c_data *data, int sel)
0543 {
0544     int sel_bits;
0545 
0546     sel_bits = fxas21002c_hpf_value_from_sel(data, sel);
0547     if (sel_bits < 0)
0548         return sel_bits;
0549 
0550     return fxas21002c_write(data, F_SEL, sel_bits);
0551 }
0552 
0553 static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val)
0554 {
0555     int fs_bits;
0556     int scale;
0557     int ret;
0558 
0559     mutex_lock(&data->lock);
0560     ret = regmap_field_read(data->regmap_fields[F_FS], &fs_bits);
0561     if (ret < 0)
0562         goto data_unlock;
0563 
0564     scale = fxas21002c_range_fs_from_value(data, fs_bits);
0565     if (scale < 0) {
0566         ret = scale;
0567         goto data_unlock;
0568     }
0569 
0570     *val = scale;
0571 
0572 data_unlock:
0573     mutex_unlock(&data->lock);
0574 
0575     return ret;
0576 }
0577 
0578 static int fxas21002c_scale_set(struct fxas21002c_data *data, int range)
0579 {
0580     int fs_bits;
0581 
0582     fs_bits = fxas21002c_range_value_from_fs(data, range);
0583     if (fs_bits < 0)
0584         return fs_bits;
0585 
0586     return fxas21002c_write(data, F_FS, fs_bits);
0587 }
0588 
0589 static int fxas21002c_read_raw(struct iio_dev *indio_dev,
0590                    struct iio_chan_spec const *chan, int *val,
0591                    int *val2, long mask)
0592 {
0593     struct fxas21002c_data *data = iio_priv(indio_dev);
0594     int ret;
0595 
0596     switch (mask) {
0597     case IIO_CHAN_INFO_RAW:
0598         switch (chan->type) {
0599         case IIO_TEMP:
0600             return fxas21002c_temp_get(data, val);
0601         case IIO_ANGL_VEL:
0602             return fxas21002c_axis_get(data, chan->scan_index, val);
0603         default:
0604             return -EINVAL;
0605         }
0606     case IIO_CHAN_INFO_SCALE:
0607         switch (chan->type) {
0608         case IIO_ANGL_VEL:
0609             *val2 = FXAS21002C_SCALE_FRACTIONAL;
0610             ret = fxas21002c_scale_get(data, val);
0611             if (ret < 0)
0612                 return ret;
0613 
0614             return IIO_VAL_FRACTIONAL;
0615         default:
0616             return -EINVAL;
0617         }
0618     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0619         *val = 0;
0620         return fxas21002c_lpf_get(data, val2);
0621     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0622         *val = 0;
0623         return fxas21002c_hpf_get(data, val2);
0624     case IIO_CHAN_INFO_SAMP_FREQ:
0625         *val2 = 0;
0626         return fxas21002c_odr_get(data, val);
0627     default:
0628         return -EINVAL;
0629     }
0630 }
0631 
0632 static int fxas21002c_write_raw(struct iio_dev *indio_dev,
0633                 struct iio_chan_spec const *chan, int val,
0634                 int val2, long mask)
0635 {
0636     struct fxas21002c_data *data = iio_priv(indio_dev);
0637     int range;
0638 
0639     switch (mask) {
0640     case IIO_CHAN_INFO_SAMP_FREQ:
0641         if (val2)
0642             return -EINVAL;
0643 
0644         return fxas21002c_odr_set(data, val);
0645     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0646         if (val)
0647             return -EINVAL;
0648 
0649         val2 = val2 / 10000;
0650         return fxas21002c_lpf_set(data, val2);
0651     case IIO_CHAN_INFO_SCALE:
0652         switch (chan->type) {
0653         case IIO_ANGL_VEL:
0654             range = (((val * 1000 + val2 / 1000) *
0655                   FXAS21002C_SCALE_FRACTIONAL) / 1000);
0656             return fxas21002c_scale_set(data, range);
0657         default:
0658             return -EINVAL;
0659         }
0660     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0661         return fxas21002c_hpf_set(data, val2);
0662     default:
0663         return -EINVAL;
0664     }
0665 }
0666 
0667 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800");
0668 
0669 static IIO_CONST_ATTR(in_anglvel_filter_low_pass_3db_frequency_available,
0670               "0.32 0.16 0.08");
0671 
0672 static IIO_CONST_ATTR(in_anglvel_filter_high_pass_3db_frequency_available,
0673               "0.018750 0.009625 0.004875 0.002475");
0674 
0675 static IIO_CONST_ATTR(in_anglvel_scale_available,
0676               "125.0 62.5 31.25 15.625 7.8125");
0677 
0678 static struct attribute *fxas21002c_attributes[] = {
0679     &iio_const_attr_sampling_frequency_available.dev_attr.attr,
0680     &iio_const_attr_in_anglvel_filter_low_pass_3db_frequency_available.dev_attr.attr,
0681     &iio_const_attr_in_anglvel_filter_high_pass_3db_frequency_available.dev_attr.attr,
0682     &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
0683     NULL,
0684 };
0685 
0686 static const struct attribute_group fxas21002c_attrs_group = {
0687     .attrs = fxas21002c_attributes,
0688 };
0689 
0690 #define FXAS21002C_CHANNEL(_axis) {                 \
0691     .type = IIO_ANGL_VEL,                       \
0692     .modified = 1,                          \
0693     .channel2 = IIO_MOD_##_axis,                    \
0694     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
0695     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |      \
0696         BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |  \
0697         BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
0698         BIT(IIO_CHAN_INFO_SAMP_FREQ),               \
0699     .scan_index = CHANNEL_SCAN_INDEX_##_axis,           \
0700     .scan_type = {                          \
0701         .sign = 's',                        \
0702         .realbits = 16,                     \
0703         .storagebits = 16,                  \
0704         .endianness = IIO_BE,                   \
0705     },                              \
0706 }
0707 
0708 static const struct iio_chan_spec fxas21002c_channels[] = {
0709     {
0710         .type = IIO_TEMP,
0711         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0712         .scan_index = -1,
0713     },
0714     FXAS21002C_CHANNEL(X),
0715     FXAS21002C_CHANNEL(Y),
0716     FXAS21002C_CHANNEL(Z),
0717 };
0718 
0719 static const struct iio_info fxas21002c_info = {
0720     .attrs          = &fxas21002c_attrs_group,
0721     .read_raw       = &fxas21002c_read_raw,
0722     .write_raw      = &fxas21002c_write_raw,
0723 };
0724 
0725 static irqreturn_t fxas21002c_trigger_handler(int irq, void *p)
0726 {
0727     struct iio_poll_func *pf = p;
0728     struct iio_dev *indio_dev = pf->indio_dev;
0729     struct fxas21002c_data *data = iio_priv(indio_dev);
0730     int ret;
0731 
0732     mutex_lock(&data->lock);
0733     ret = regmap_bulk_read(data->regmap, FXAS21002C_REG_OUT_X_MSB,
0734                    data->buffer, CHANNEL_SCAN_MAX * sizeof(s16));
0735     if (ret < 0)
0736         goto out_unlock;
0737 
0738     iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
0739                        data->timestamp);
0740 
0741 out_unlock:
0742     mutex_unlock(&data->lock);
0743 
0744     iio_trigger_notify_done(indio_dev->trig);
0745 
0746     return IRQ_HANDLED;
0747 }
0748 
0749 static int fxas21002c_chip_init(struct fxas21002c_data *data)
0750 {
0751     struct device *dev = regmap_get_device(data->regmap);
0752     unsigned int chip_id;
0753     int ret;
0754 
0755     ret = regmap_field_read(data->regmap_fields[F_WHO_AM_I], &chip_id);
0756     if (ret < 0)
0757         return ret;
0758 
0759     if (chip_id != FXAS21002C_CHIP_ID_1 &&
0760         chip_id != FXAS21002C_CHIP_ID_2) {
0761         dev_err(dev, "chip id 0x%02x is not supported\n", chip_id);
0762         return -EINVAL;
0763     }
0764 
0765     data->chip_id = chip_id;
0766 
0767     ret = fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
0768     if (ret < 0)
0769         return ret;
0770 
0771     /* Set ODR to 200HZ as default */
0772     ret = fxas21002c_odr_set(data, 200);
0773     if (ret < 0)
0774         dev_err(dev, "failed to set ODR: %d\n", ret);
0775 
0776     return ret;
0777 }
0778 
0779 static int fxas21002c_data_rdy_trigger_set_state(struct iio_trigger *trig,
0780                          bool state)
0781 {
0782     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0783     struct fxas21002c_data *data = iio_priv(indio_dev);
0784 
0785     return regmap_field_write(data->regmap_fields[F_INT_EN_DRDY], state);
0786 }
0787 
0788 static const struct iio_trigger_ops fxas21002c_trigger_ops = {
0789     .set_trigger_state = &fxas21002c_data_rdy_trigger_set_state,
0790 };
0791 
0792 static irqreturn_t fxas21002c_data_rdy_handler(int irq, void *private)
0793 {
0794     struct iio_dev *indio_dev = private;
0795     struct fxas21002c_data *data = iio_priv(indio_dev);
0796 
0797     data->timestamp = iio_get_time_ns(indio_dev);
0798 
0799     return IRQ_WAKE_THREAD;
0800 }
0801 
0802 static irqreturn_t fxas21002c_data_rdy_thread(int irq, void *private)
0803 {
0804     struct iio_dev *indio_dev = private;
0805     struct fxas21002c_data *data = iio_priv(indio_dev);
0806     unsigned int data_ready;
0807     int ret;
0808 
0809     ret = regmap_field_read(data->regmap_fields[F_SRC_DRDY], &data_ready);
0810     if (ret < 0)
0811         return IRQ_NONE;
0812 
0813     if (!data_ready)
0814         return IRQ_NONE;
0815 
0816     iio_trigger_poll_chained(data->dready_trig);
0817 
0818     return IRQ_HANDLED;
0819 }
0820 
0821 static int fxas21002c_trigger_probe(struct fxas21002c_data *data)
0822 {
0823     struct device *dev = regmap_get_device(data->regmap);
0824     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0825     unsigned long irq_trig;
0826     bool irq_open_drain;
0827     int irq1;
0828     int ret;
0829 
0830     if (!data->irq)
0831         return 0;
0832 
0833     irq1 = fwnode_irq_get_byname(dev_fwnode(dev), "INT1");
0834     if (irq1 == data->irq) {
0835         dev_info(dev, "using interrupt line INT1\n");
0836         ret = regmap_field_write(data->regmap_fields[F_INT_CFG_DRDY],
0837                      1);
0838         if (ret < 0)
0839             return ret;
0840     }
0841 
0842     dev_info(dev, "using interrupt line INT2\n");
0843 
0844     irq_open_drain = device_property_read_bool(dev, "drive-open-drain");
0845 
0846     data->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
0847                            indio_dev->name,
0848                            iio_device_id(indio_dev));
0849     if (!data->dready_trig)
0850         return -ENOMEM;
0851 
0852     irq_trig = irqd_get_trigger_type(irq_get_irq_data(data->irq));
0853 
0854     if (irq_trig == IRQF_TRIGGER_RISING) {
0855         ret = regmap_field_write(data->regmap_fields[F_IPOL], 1);
0856         if (ret < 0)
0857             return ret;
0858     }
0859 
0860     if (irq_open_drain)
0861         irq_trig |= IRQF_SHARED;
0862 
0863     ret = devm_request_threaded_irq(dev, data->irq,
0864                     fxas21002c_data_rdy_handler,
0865                     fxas21002c_data_rdy_thread,
0866                     irq_trig, "fxas21002c_data_ready",
0867                     indio_dev);
0868     if (ret < 0)
0869         return ret;
0870 
0871     data->dready_trig->ops = &fxas21002c_trigger_ops;
0872     iio_trigger_set_drvdata(data->dready_trig, indio_dev);
0873 
0874     return devm_iio_trigger_register(dev, data->dready_trig);
0875 }
0876 
0877 static int fxas21002c_power_enable(struct fxas21002c_data *data)
0878 {
0879     int ret;
0880 
0881     ret = regulator_enable(data->vdd);
0882     if (ret < 0)
0883         return ret;
0884 
0885     ret = regulator_enable(data->vddio);
0886     if (ret < 0) {
0887         regulator_disable(data->vdd);
0888         return ret;
0889     }
0890 
0891     return 0;
0892 }
0893 
0894 static void fxas21002c_power_disable(struct fxas21002c_data *data)
0895 {
0896     regulator_disable(data->vdd);
0897     regulator_disable(data->vddio);
0898 }
0899 
0900 static void fxas21002c_power_disable_action(void *_data)
0901 {
0902     struct fxas21002c_data *data = _data;
0903 
0904     fxas21002c_power_disable(data);
0905 }
0906 
0907 static int fxas21002c_regulators_get(struct fxas21002c_data *data)
0908 {
0909     struct device *dev = regmap_get_device(data->regmap);
0910 
0911     data->vdd = devm_regulator_get(dev->parent, "vdd");
0912     if (IS_ERR(data->vdd))
0913         return PTR_ERR(data->vdd);
0914 
0915     data->vddio = devm_regulator_get(dev->parent, "vddio");
0916 
0917     return PTR_ERR_OR_ZERO(data->vddio);
0918 }
0919 
0920 int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq,
0921               const char *name)
0922 {
0923     struct fxas21002c_data *data;
0924     struct iio_dev *indio_dev;
0925     struct regmap_field *f;
0926     int i;
0927     int ret;
0928 
0929     indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
0930     if (!indio_dev)
0931         return -ENOMEM;
0932 
0933     data = iio_priv(indio_dev);
0934     dev_set_drvdata(dev, indio_dev);
0935     data->irq = irq;
0936     data->regmap = regmap;
0937 
0938     for (i = 0; i < F_MAX_FIELDS; i++) {
0939         f = devm_regmap_field_alloc(dev, data->regmap,
0940                         fxas21002c_reg_fields[i]);
0941         if (IS_ERR(f))
0942             return PTR_ERR(f);
0943 
0944         data->regmap_fields[i] = f;
0945     }
0946 
0947     mutex_init(&data->lock);
0948 
0949     ret = fxas21002c_regulators_get(data);
0950     if (ret < 0)
0951         return ret;
0952 
0953     ret = fxas21002c_power_enable(data);
0954     if (ret < 0)
0955         return ret;
0956 
0957     ret = devm_add_action_or_reset(dev, fxas21002c_power_disable_action,
0958                        data);
0959     if (ret < 0)
0960         return ret;
0961 
0962     ret = fxas21002c_chip_init(data);
0963     if (ret < 0)
0964         return ret;
0965 
0966     indio_dev->channels = fxas21002c_channels;
0967     indio_dev->num_channels = ARRAY_SIZE(fxas21002c_channels);
0968     indio_dev->name = name;
0969     indio_dev->modes = INDIO_DIRECT_MODE;
0970     indio_dev->info = &fxas21002c_info;
0971 
0972     ret = fxas21002c_trigger_probe(data);
0973     if (ret < 0)
0974         return ret;
0975 
0976     ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
0977                           fxas21002c_trigger_handler, NULL);
0978     if (ret < 0)
0979         return ret;
0980 
0981     ret = pm_runtime_set_active(dev);
0982     if (ret)
0983         return ret;
0984 
0985     pm_runtime_enable(dev);
0986     pm_runtime_set_autosuspend_delay(dev, 2000);
0987     pm_runtime_use_autosuspend(dev);
0988 
0989     ret = iio_device_register(indio_dev);
0990     if (ret < 0)
0991         goto pm_disable;
0992 
0993     return 0;
0994 
0995 pm_disable:
0996     pm_runtime_disable(dev);
0997     pm_runtime_set_suspended(dev);
0998 
0999     return ret;
1000 }
1001 EXPORT_SYMBOL_GPL(fxas21002c_core_probe);
1002 
1003 void fxas21002c_core_remove(struct device *dev)
1004 {
1005     struct iio_dev *indio_dev = dev_get_drvdata(dev);
1006 
1007     iio_device_unregister(indio_dev);
1008 
1009     pm_runtime_disable(dev);
1010     pm_runtime_set_suspended(dev);
1011 }
1012 EXPORT_SYMBOL_GPL(fxas21002c_core_remove);
1013 
1014 static int __maybe_unused fxas21002c_suspend(struct device *dev)
1015 {
1016     struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1017 
1018     fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
1019     fxas21002c_power_disable(data);
1020 
1021     return 0;
1022 }
1023 
1024 static int __maybe_unused fxas21002c_resume(struct device *dev)
1025 {
1026     struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1027     int ret;
1028 
1029     ret = fxas21002c_power_enable(data);
1030     if (ret < 0)
1031         return ret;
1032 
1033     return fxas21002c_mode_set(data, data->prev_mode);
1034 }
1035 
1036 static int __maybe_unused fxas21002c_runtime_suspend(struct device *dev)
1037 {
1038     struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1039 
1040     return fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
1041 }
1042 
1043 static int __maybe_unused fxas21002c_runtime_resume(struct device *dev)
1044 {
1045     struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1046 
1047     return fxas21002c_mode_set(data, FXAS21002C_MODE_ACTIVE);
1048 }
1049 
1050 const struct dev_pm_ops fxas21002c_pm_ops = {
1051     SET_SYSTEM_SLEEP_PM_OPS(fxas21002c_suspend, fxas21002c_resume)
1052     SET_RUNTIME_PM_OPS(fxas21002c_runtime_suspend,
1053                fxas21002c_runtime_resume, NULL)
1054 };
1055 EXPORT_SYMBOL_GPL(fxas21002c_pm_ops);
1056 
1057 MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
1058 MODULE_LICENSE("GPL v2");
1059 MODULE_DESCRIPTION("FXAS21002C Gyro driver");
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