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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * ADXRS290 SPI Gyroscope Driver
0004  *
0005  * Copyright (C) 2020 Nishant Malpani <nish.malpani25@gmail.com>
0006  * Copyright (C) 2020 Analog Devices, Inc.
0007  */
0008 
0009 #include <linux/bitfield.h>
0010 #include <linux/bitops.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/spi/spi.h>
0016 
0017 #include <linux/iio/buffer.h>
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 #include <linux/iio/trigger.h>
0021 #include <linux/iio/triggered_buffer.h>
0022 #include <linux/iio/trigger_consumer.h>
0023 
0024 #define ADXRS290_ADI_ID     0xAD
0025 #define ADXRS290_MEMS_ID    0x1D
0026 #define ADXRS290_DEV_ID     0x92
0027 
0028 #define ADXRS290_REG_ADI_ID 0x00
0029 #define ADXRS290_REG_MEMS_ID    0x01
0030 #define ADXRS290_REG_DEV_ID 0x02
0031 #define ADXRS290_REG_REV_ID 0x03
0032 #define ADXRS290_REG_SN0    0x04 /* Serial Number Registers, 4 bytes */
0033 #define ADXRS290_REG_DATAX0 0x08 /* Roll Rate o/p Data Regs, 2 bytes */
0034 #define ADXRS290_REG_DATAY0 0x0A /* Pitch Rate o/p Data Regs, 2 bytes */
0035 #define ADXRS290_REG_TEMP0  0x0C
0036 #define ADXRS290_REG_POWER_CTL  0x10
0037 #define ADXRS290_REG_FILTER 0x11
0038 #define ADXRS290_REG_DATA_RDY   0x12
0039 
0040 #define ADXRS290_READ       BIT(7)
0041 #define ADXRS290_TSM        BIT(0)
0042 #define ADXRS290_MEASUREMENT    BIT(1)
0043 #define ADXRS290_DATA_RDY_OUT   BIT(0)
0044 #define ADXRS290_SYNC_MASK  GENMASK(1, 0)
0045 #define ADXRS290_SYNC(x)    FIELD_PREP(ADXRS290_SYNC_MASK, x)
0046 #define ADXRS290_LPF_MASK   GENMASK(2, 0)
0047 #define ADXRS290_LPF(x)     FIELD_PREP(ADXRS290_LPF_MASK, x)
0048 #define ADXRS290_HPF_MASK   GENMASK(7, 4)
0049 #define ADXRS290_HPF(x)     FIELD_PREP(ADXRS290_HPF_MASK, x)
0050 
0051 #define ADXRS290_READ_REG(reg)  (ADXRS290_READ | (reg))
0052 
0053 #define ADXRS290_MAX_TRANSITION_TIME_MS 100
0054 
0055 enum adxrs290_mode {
0056     ADXRS290_MODE_STANDBY,
0057     ADXRS290_MODE_MEASUREMENT,
0058 };
0059 
0060 enum adxrs290_scan_index {
0061     ADXRS290_IDX_X,
0062     ADXRS290_IDX_Y,
0063     ADXRS290_IDX_TEMP,
0064     ADXRS290_IDX_TS,
0065 };
0066 
0067 struct adxrs290_state {
0068     struct spi_device   *spi;
0069     /* Serialize reads and their subsequent processing */
0070     struct mutex        lock;
0071     enum adxrs290_mode  mode;
0072     unsigned int        lpf_3db_freq_idx;
0073     unsigned int        hpf_3db_freq_idx;
0074     struct iio_trigger      *dready_trig;
0075     /* Ensure correct alignment of timestamp when present */
0076     struct {
0077         s16 channels[3];
0078         s64 ts __aligned(8);
0079     } buffer;
0080 };
0081 
0082 /*
0083  * Available cut-off frequencies of the low pass filter in Hz.
0084  * The integer part and fractional part are represented separately.
0085  */
0086 static const int adxrs290_lpf_3db_freq_hz_table[][2] = {
0087     [0] = {480, 0},
0088     [1] = {320, 0},
0089     [2] = {160, 0},
0090     [3] = {80, 0},
0091     [4] = {56, 600000},
0092     [5] = {40, 0},
0093     [6] = {28, 300000},
0094     [7] = {20, 0},
0095 };
0096 
0097 /*
0098  * Available cut-off frequencies of the high pass filter in Hz.
0099  * The integer part and fractional part are represented separately.
0100  */
0101 static const int adxrs290_hpf_3db_freq_hz_table[][2] = {
0102     [0] = {0, 0},
0103     [1] = {0, 11000},
0104     [2] = {0, 22000},
0105     [3] = {0, 44000},
0106     [4] = {0, 87000},
0107     [5] = {0, 175000},
0108     [6] = {0, 350000},
0109     [7] = {0, 700000},
0110     [8] = {1, 400000},
0111     [9] = {2, 800000},
0112     [10] = {11, 300000},
0113 };
0114 
0115 static int adxrs290_get_rate_data(struct iio_dev *indio_dev, const u8 cmd, int *val)
0116 {
0117     struct adxrs290_state *st = iio_priv(indio_dev);
0118     int ret = 0;
0119     int temp;
0120 
0121     mutex_lock(&st->lock);
0122     temp = spi_w8r16(st->spi, cmd);
0123     if (temp < 0) {
0124         ret = temp;
0125         goto err_unlock;
0126     }
0127 
0128     *val = sign_extend32(temp, 15);
0129 
0130 err_unlock:
0131     mutex_unlock(&st->lock);
0132     return ret;
0133 }
0134 
0135 static int adxrs290_get_temp_data(struct iio_dev *indio_dev, int *val)
0136 {
0137     const u8 cmd = ADXRS290_READ_REG(ADXRS290_REG_TEMP0);
0138     struct adxrs290_state *st = iio_priv(indio_dev);
0139     int ret = 0;
0140     int temp;
0141 
0142     mutex_lock(&st->lock);
0143     temp = spi_w8r16(st->spi, cmd);
0144     if (temp < 0) {
0145         ret = temp;
0146         goto err_unlock;
0147     }
0148 
0149     /* extract lower 12 bits temperature reading */
0150     *val = sign_extend32(temp, 11);
0151 
0152 err_unlock:
0153     mutex_unlock(&st->lock);
0154     return ret;
0155 }
0156 
0157 static int adxrs290_get_3db_freq(struct iio_dev *indio_dev, u8 *val, u8 *val2)
0158 {
0159     const u8 cmd = ADXRS290_READ_REG(ADXRS290_REG_FILTER);
0160     struct adxrs290_state *st = iio_priv(indio_dev);
0161     int ret = 0;
0162     short temp;
0163 
0164     mutex_lock(&st->lock);
0165     temp = spi_w8r8(st->spi, cmd);
0166     if (temp < 0) {
0167         ret = temp;
0168         goto err_unlock;
0169     }
0170 
0171     *val = FIELD_GET(ADXRS290_LPF_MASK, temp);
0172     *val2 = FIELD_GET(ADXRS290_HPF_MASK, temp);
0173 
0174 err_unlock:
0175     mutex_unlock(&st->lock);
0176     return ret;
0177 }
0178 
0179 static int adxrs290_spi_write_reg(struct spi_device *spi, const u8 reg,
0180                   const u8 val)
0181 {
0182     u8 buf[2];
0183 
0184     buf[0] = reg;
0185     buf[1] = val;
0186 
0187     return spi_write_then_read(spi, buf, ARRAY_SIZE(buf), NULL, 0);
0188 }
0189 
0190 static int adxrs290_find_match(const int (*freq_tbl)[2], const int n,
0191                    const int val, const int val2)
0192 {
0193     int i;
0194 
0195     for (i = 0; i < n; i++) {
0196         if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)
0197             return i;
0198     }
0199 
0200     return -EINVAL;
0201 }
0202 
0203 static int adxrs290_set_filter_freq(struct iio_dev *indio_dev,
0204                     const unsigned int lpf_idx,
0205                     const unsigned int hpf_idx)
0206 {
0207     struct adxrs290_state *st = iio_priv(indio_dev);
0208     u8 val;
0209 
0210     val = ADXRS290_HPF(hpf_idx) | ADXRS290_LPF(lpf_idx);
0211 
0212     return adxrs290_spi_write_reg(st->spi, ADXRS290_REG_FILTER, val);
0213 }
0214 
0215 static int adxrs290_set_mode(struct iio_dev *indio_dev, enum adxrs290_mode mode)
0216 {
0217     struct adxrs290_state *st = iio_priv(indio_dev);
0218     int val, ret;
0219 
0220     if (st->mode == mode)
0221         return 0;
0222 
0223     mutex_lock(&st->lock);
0224 
0225     ret = spi_w8r8(st->spi, ADXRS290_READ_REG(ADXRS290_REG_POWER_CTL));
0226     if (ret < 0)
0227         goto out_unlock;
0228 
0229     val = ret;
0230 
0231     switch (mode) {
0232     case ADXRS290_MODE_STANDBY:
0233         val &= ~ADXRS290_MEASUREMENT;
0234         break;
0235     case ADXRS290_MODE_MEASUREMENT:
0236         val |= ADXRS290_MEASUREMENT;
0237         break;
0238     default:
0239         ret = -EINVAL;
0240         goto out_unlock;
0241     }
0242 
0243     ret = adxrs290_spi_write_reg(st->spi, ADXRS290_REG_POWER_CTL, val);
0244     if (ret < 0) {
0245         dev_err(&st->spi->dev, "unable to set mode: %d\n", ret);
0246         goto out_unlock;
0247     }
0248 
0249     /* update cached mode */
0250     st->mode = mode;
0251 
0252 out_unlock:
0253     mutex_unlock(&st->lock);
0254     return ret;
0255 }
0256 
0257 static void adxrs290_chip_off_action(void *data)
0258 {
0259     struct iio_dev *indio_dev = data;
0260 
0261     adxrs290_set_mode(indio_dev, ADXRS290_MODE_STANDBY);
0262 }
0263 
0264 static int adxrs290_initial_setup(struct iio_dev *indio_dev)
0265 {
0266     struct adxrs290_state *st = iio_priv(indio_dev);
0267     struct spi_device *spi = st->spi;
0268     int ret;
0269 
0270     ret = adxrs290_spi_write_reg(spi, ADXRS290_REG_POWER_CTL,
0271                      ADXRS290_MEASUREMENT | ADXRS290_TSM);
0272     if (ret < 0)
0273         return ret;
0274 
0275     st->mode = ADXRS290_MODE_MEASUREMENT;
0276 
0277     return devm_add_action_or_reset(&spi->dev, adxrs290_chip_off_action,
0278                     indio_dev);
0279 }
0280 
0281 static int adxrs290_read_raw(struct iio_dev *indio_dev,
0282                  struct iio_chan_spec const *chan,
0283                  int *val,
0284                  int *val2,
0285                  long mask)
0286 {
0287     struct adxrs290_state *st = iio_priv(indio_dev);
0288     unsigned int t;
0289     int ret;
0290 
0291     switch (mask) {
0292     case IIO_CHAN_INFO_RAW:
0293         ret = iio_device_claim_direct_mode(indio_dev);
0294         if (ret)
0295             return ret;
0296 
0297         switch (chan->type) {
0298         case IIO_ANGL_VEL:
0299             ret = adxrs290_get_rate_data(indio_dev,
0300                              ADXRS290_READ_REG(chan->address),
0301                              val);
0302             if (ret < 0)
0303                 break;
0304 
0305             ret = IIO_VAL_INT;
0306             break;
0307         case IIO_TEMP:
0308             ret = adxrs290_get_temp_data(indio_dev, val);
0309             if (ret < 0)
0310                 break;
0311 
0312             ret = IIO_VAL_INT;
0313             break;
0314         default:
0315             ret = -EINVAL;
0316             break;
0317         }
0318 
0319         iio_device_release_direct_mode(indio_dev);
0320         return ret;
0321     case IIO_CHAN_INFO_SCALE:
0322         switch (chan->type) {
0323         case IIO_ANGL_VEL:
0324             /* 1 LSB = 0.005 degrees/sec */
0325             *val = 0;
0326             *val2 = 87266;
0327             return IIO_VAL_INT_PLUS_NANO;
0328         case IIO_TEMP:
0329             /* 1 LSB = 0.1 degrees Celsius */
0330             *val = 100;
0331             return IIO_VAL_INT;
0332         default:
0333             return -EINVAL;
0334         }
0335     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0336         switch (chan->type) {
0337         case IIO_ANGL_VEL:
0338             t = st->lpf_3db_freq_idx;
0339             *val = adxrs290_lpf_3db_freq_hz_table[t][0];
0340             *val2 = adxrs290_lpf_3db_freq_hz_table[t][1];
0341             return IIO_VAL_INT_PLUS_MICRO;
0342         default:
0343             return -EINVAL;
0344         }
0345     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0346         switch (chan->type) {
0347         case IIO_ANGL_VEL:
0348             t = st->hpf_3db_freq_idx;
0349             *val = adxrs290_hpf_3db_freq_hz_table[t][0];
0350             *val2 = adxrs290_hpf_3db_freq_hz_table[t][1];
0351             return IIO_VAL_INT_PLUS_MICRO;
0352         default:
0353             return -EINVAL;
0354         }
0355     }
0356 
0357     return -EINVAL;
0358 }
0359 
0360 static int adxrs290_write_raw(struct iio_dev *indio_dev,
0361                   struct iio_chan_spec const *chan,
0362                   int val,
0363                   int val2,
0364                   long mask)
0365 {
0366     struct adxrs290_state *st = iio_priv(indio_dev);
0367     int ret, lpf_idx, hpf_idx;
0368 
0369     ret = iio_device_claim_direct_mode(indio_dev);
0370     if (ret)
0371         return ret;
0372 
0373     switch (mask) {
0374     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0375         lpf_idx = adxrs290_find_match(adxrs290_lpf_3db_freq_hz_table,
0376                           ARRAY_SIZE(adxrs290_lpf_3db_freq_hz_table),
0377                           val, val2);
0378         if (lpf_idx < 0) {
0379             ret = -EINVAL;
0380             break;
0381         }
0382 
0383         /* caching the updated state of the low-pass filter */
0384         st->lpf_3db_freq_idx = lpf_idx;
0385         /* retrieving the current state of the high-pass filter */
0386         hpf_idx = st->hpf_3db_freq_idx;
0387         ret = adxrs290_set_filter_freq(indio_dev, lpf_idx, hpf_idx);
0388         break;
0389 
0390     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0391         hpf_idx = adxrs290_find_match(adxrs290_hpf_3db_freq_hz_table,
0392                           ARRAY_SIZE(adxrs290_hpf_3db_freq_hz_table),
0393                           val, val2);
0394         if (hpf_idx < 0) {
0395             ret = -EINVAL;
0396             break;
0397         }
0398 
0399         /* caching the updated state of the high-pass filter */
0400         st->hpf_3db_freq_idx = hpf_idx;
0401         /* retrieving the current state of the low-pass filter */
0402         lpf_idx = st->lpf_3db_freq_idx;
0403         ret = adxrs290_set_filter_freq(indio_dev, lpf_idx, hpf_idx);
0404         break;
0405 
0406     default:
0407         ret = -EINVAL;
0408         break;
0409     }
0410 
0411     iio_device_release_direct_mode(indio_dev);
0412     return ret;
0413 }
0414 
0415 static int adxrs290_read_avail(struct iio_dev *indio_dev,
0416                    struct iio_chan_spec const *chan,
0417                    const int **vals, int *type, int *length,
0418                    long mask)
0419 {
0420     switch (mask) {
0421     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0422         *vals = (const int *)adxrs290_lpf_3db_freq_hz_table;
0423         *type = IIO_VAL_INT_PLUS_MICRO;
0424         /* Values are stored in a 2D matrix */
0425         *length = ARRAY_SIZE(adxrs290_lpf_3db_freq_hz_table) * 2;
0426 
0427         return IIO_AVAIL_LIST;
0428     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0429         *vals = (const int *)adxrs290_hpf_3db_freq_hz_table;
0430         *type = IIO_VAL_INT_PLUS_MICRO;
0431         /* Values are stored in a 2D matrix */
0432         *length = ARRAY_SIZE(adxrs290_hpf_3db_freq_hz_table) * 2;
0433 
0434         return IIO_AVAIL_LIST;
0435     default:
0436         return -EINVAL;
0437     }
0438 }
0439 
0440 static int adxrs290_reg_access_rw(struct spi_device *spi, unsigned int reg,
0441                   unsigned int *readval)
0442 {
0443     int ret;
0444 
0445     ret = spi_w8r8(spi, ADXRS290_READ_REG(reg));
0446     if (ret < 0)
0447         return ret;
0448 
0449     *readval = ret;
0450 
0451     return 0;
0452 }
0453 
0454 static int adxrs290_reg_access(struct iio_dev *indio_dev, unsigned int reg,
0455                    unsigned int writeval, unsigned int *readval)
0456 {
0457     struct adxrs290_state *st = iio_priv(indio_dev);
0458 
0459     if (readval)
0460         return adxrs290_reg_access_rw(st->spi, reg, readval);
0461     else
0462         return adxrs290_spi_write_reg(st->spi, reg, writeval);
0463 }
0464 
0465 static int adxrs290_data_rdy_trigger_set_state(struct iio_trigger *trig,
0466                            bool state)
0467 {
0468     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0469     struct adxrs290_state *st = iio_priv(indio_dev);
0470     int ret;
0471     u8 val;
0472 
0473     val = state ? ADXRS290_SYNC(ADXRS290_DATA_RDY_OUT) : 0;
0474 
0475     ret = adxrs290_spi_write_reg(st->spi, ADXRS290_REG_DATA_RDY, val);
0476     if (ret < 0)
0477         dev_err(&st->spi->dev, "failed to start data rdy interrupt\n");
0478 
0479     return ret;
0480 }
0481 
0482 static void adxrs290_reset_trig(struct iio_trigger *trig)
0483 {
0484     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0485     int val;
0486 
0487     /*
0488      * Data ready interrupt is reset after a read of the data registers.
0489      * Here, we only read the 16b DATAY registers as that marks the end of
0490      * a read of the data registers and initiates a reset for the interrupt
0491      * line.
0492      */
0493     adxrs290_get_rate_data(indio_dev,
0494                    ADXRS290_READ_REG(ADXRS290_REG_DATAY0), &val);
0495 }
0496 
0497 static const struct iio_trigger_ops adxrs290_trigger_ops = {
0498     .set_trigger_state = &adxrs290_data_rdy_trigger_set_state,
0499     .validate_device = &iio_trigger_validate_own_device,
0500     .reenable = &adxrs290_reset_trig,
0501 };
0502 
0503 static irqreturn_t adxrs290_trigger_handler(int irq, void *p)
0504 {
0505     struct iio_poll_func *pf = p;
0506     struct iio_dev *indio_dev = pf->indio_dev;
0507     struct adxrs290_state *st = iio_priv(indio_dev);
0508     u8 tx = ADXRS290_READ_REG(ADXRS290_REG_DATAX0);
0509     int ret;
0510 
0511     mutex_lock(&st->lock);
0512 
0513     /* exercise a bulk data capture starting from reg DATAX0... */
0514     ret = spi_write_then_read(st->spi, &tx, sizeof(tx), st->buffer.channels,
0515                   sizeof(st->buffer.channels));
0516     if (ret < 0)
0517         goto out_unlock_notify;
0518 
0519     iio_push_to_buffers_with_timestamp(indio_dev, &st->buffer,
0520                        pf->timestamp);
0521 
0522 out_unlock_notify:
0523     mutex_unlock(&st->lock);
0524     iio_trigger_notify_done(indio_dev->trig);
0525 
0526     return IRQ_HANDLED;
0527 }
0528 
0529 #define ADXRS290_ANGL_VEL_CHANNEL(reg, axis) {              \
0530     .type = IIO_ANGL_VEL,                       \
0531     .address = reg,                         \
0532     .modified = 1,                          \
0533     .channel2 = IIO_MOD_##axis,                 \
0534     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
0535     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |      \
0536     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |      \
0537     BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY),      \
0538     .info_mask_shared_by_type_available =               \
0539     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |      \
0540     BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY),      \
0541     .scan_index = ADXRS290_IDX_##axis,              \
0542     .scan_type = {                                                  \
0543         .sign = 's',                                            \
0544         .realbits = 16,                                         \
0545         .storagebits = 16,                                      \
0546         .endianness = IIO_LE,                   \
0547     },                                                              \
0548 }
0549 
0550 static const struct iio_chan_spec adxrs290_channels[] = {
0551     ADXRS290_ANGL_VEL_CHANNEL(ADXRS290_REG_DATAX0, X),
0552     ADXRS290_ANGL_VEL_CHANNEL(ADXRS290_REG_DATAY0, Y),
0553     {
0554         .type = IIO_TEMP,
0555         .address = ADXRS290_REG_TEMP0,
0556         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0557         BIT(IIO_CHAN_INFO_SCALE),
0558         .scan_index = ADXRS290_IDX_TEMP,
0559         .scan_type = {
0560             .sign = 's',
0561             .realbits = 12,
0562             .storagebits = 16,
0563             .endianness = IIO_LE,
0564         },
0565     },
0566     IIO_CHAN_SOFT_TIMESTAMP(ADXRS290_IDX_TS),
0567 };
0568 
0569 static const unsigned long adxrs290_avail_scan_masks[] = {
0570     BIT(ADXRS290_IDX_X) | BIT(ADXRS290_IDX_Y) | BIT(ADXRS290_IDX_TEMP),
0571     0
0572 };
0573 
0574 static const struct iio_info adxrs290_info = {
0575     .read_raw = &adxrs290_read_raw,
0576     .write_raw = &adxrs290_write_raw,
0577     .read_avail = &adxrs290_read_avail,
0578     .debugfs_reg_access = &adxrs290_reg_access,
0579 };
0580 
0581 static int adxrs290_probe_trigger(struct iio_dev *indio_dev)
0582 {
0583     struct adxrs290_state *st = iio_priv(indio_dev);
0584     int ret;
0585 
0586     if (!st->spi->irq) {
0587         dev_info(&st->spi->dev, "no irq, using polling\n");
0588         return 0;
0589     }
0590 
0591     st->dready_trig = devm_iio_trigger_alloc(&st->spi->dev, "%s-dev%d",
0592                          indio_dev->name,
0593                          iio_device_id(indio_dev));
0594     if (!st->dready_trig)
0595         return -ENOMEM;
0596 
0597     st->dready_trig->ops = &adxrs290_trigger_ops;
0598     iio_trigger_set_drvdata(st->dready_trig, indio_dev);
0599 
0600     ret = devm_request_irq(&st->spi->dev, st->spi->irq,
0601                    &iio_trigger_generic_data_rdy_poll,
0602                    IRQF_ONESHOT, "adxrs290_irq", st->dready_trig);
0603     if (ret < 0)
0604         return dev_err_probe(&st->spi->dev, ret,
0605                      "request irq %d failed\n", st->spi->irq);
0606 
0607     ret = devm_iio_trigger_register(&st->spi->dev, st->dready_trig);
0608     if (ret) {
0609         dev_err(&st->spi->dev, "iio trigger register failed\n");
0610         return ret;
0611     }
0612 
0613     indio_dev->trig = iio_trigger_get(st->dready_trig);
0614 
0615     return 0;
0616 }
0617 
0618 static int adxrs290_probe(struct spi_device *spi)
0619 {
0620     struct iio_dev *indio_dev;
0621     struct adxrs290_state *st;
0622     u8 val, val2;
0623     int ret;
0624 
0625     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0626     if (!indio_dev)
0627         return -ENOMEM;
0628 
0629     st = iio_priv(indio_dev);
0630     st->spi = spi;
0631 
0632     indio_dev->name = "adxrs290";
0633     indio_dev->modes = INDIO_DIRECT_MODE;
0634     indio_dev->channels = adxrs290_channels;
0635     indio_dev->num_channels = ARRAY_SIZE(adxrs290_channels);
0636     indio_dev->info = &adxrs290_info;
0637     indio_dev->available_scan_masks = adxrs290_avail_scan_masks;
0638 
0639     mutex_init(&st->lock);
0640 
0641     val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_ADI_ID));
0642     if (val != ADXRS290_ADI_ID) {
0643         dev_err(&spi->dev, "Wrong ADI ID 0x%02x\n", val);
0644         return -ENODEV;
0645     }
0646 
0647     val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_MEMS_ID));
0648     if (val != ADXRS290_MEMS_ID) {
0649         dev_err(&spi->dev, "Wrong MEMS ID 0x%02x\n", val);
0650         return -ENODEV;
0651     }
0652 
0653     val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_DEV_ID));
0654     if (val != ADXRS290_DEV_ID) {
0655         dev_err(&spi->dev, "Wrong DEV ID 0x%02x\n", val);
0656         return -ENODEV;
0657     }
0658 
0659     /* default mode the gyroscope starts in */
0660     st->mode = ADXRS290_MODE_STANDBY;
0661 
0662     /* switch to measurement mode and switch on the temperature sensor */
0663     ret = adxrs290_initial_setup(indio_dev);
0664     if (ret < 0)
0665         return ret;
0666 
0667     /* max transition time to measurement mode */
0668     msleep(ADXRS290_MAX_TRANSITION_TIME_MS);
0669 
0670     ret = adxrs290_get_3db_freq(indio_dev, &val, &val2);
0671     if (ret < 0)
0672         return ret;
0673 
0674     st->lpf_3db_freq_idx = val;
0675     st->hpf_3db_freq_idx = val2;
0676 
0677     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
0678                           &iio_pollfunc_store_time,
0679                           &adxrs290_trigger_handler, NULL);
0680     if (ret < 0)
0681         return dev_err_probe(&spi->dev, ret,
0682                      "iio triggered buffer setup failed\n");
0683 
0684     ret = adxrs290_probe_trigger(indio_dev);
0685     if (ret < 0)
0686         return ret;
0687 
0688     return devm_iio_device_register(&spi->dev, indio_dev);
0689 }
0690 
0691 static const struct of_device_id adxrs290_of_match[] = {
0692     { .compatible = "adi,adxrs290" },
0693     { }
0694 };
0695 MODULE_DEVICE_TABLE(of, adxrs290_of_match);
0696 
0697 static struct spi_driver adxrs290_driver = {
0698     .driver = {
0699         .name = "adxrs290",
0700         .of_match_table = adxrs290_of_match,
0701     },
0702     .probe = adxrs290_probe,
0703 };
0704 module_spi_driver(adxrs290_driver);
0705 
0706 MODULE_AUTHOR("Nishant Malpani <nish.malpani25@gmail.com>");
0707 MODULE_DESCRIPTION("Analog Devices ADXRS290 Gyroscope SPI driver");
0708 MODULE_LICENSE("GPL");
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