iio/frequency/adrf6780.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADRF6780 driver
0004  *
0005  * Copyright 2021 Analog Devices Inc.
0006  */
0007
0008 #include <linux/bitfield.h>
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/iio/iio.h>
0016 #include <linux/module.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/spi/spi.h>
0019
0020 #include <asm/unaligned.h>
0021
0022 /* ADRF6780 Register Map */
0023 #define ADRF6780_REG_CONTROL            0x00
0024 #define ADRF6780_REG_ALARM_READBACK     0x01
0025 #define ADRF6780_REG_ALARM_MASKS        0x02
0026 #define ADRF6780_REG_ENABLE         0x03
0027 #define ADRF6780_REG_LINEARIZE          0x04
0028 #define ADRF6780_REG_LO_PATH            0x05
0029 #define ADRF6780_REG_ADC_CONTROL        0x06
0030 #define ADRF6780_REG_ADC_OUTPUT         0x0C
0031
0032 /* ADRF6780_REG_CONTROL Map */
0033 #define ADRF6780_PARITY_EN_MSK          BIT(15)
0034 #define ADRF6780_SOFT_RESET_MSK         BIT(14)
0035 #define ADRF6780_CHIP_ID_MSK            GENMASK(11, 4)
0036 #define ADRF6780_CHIP_ID            0xA
0037 #define ADRF6780_CHIP_REVISION_MSK      GENMASK(3, 0)
0038
0039 /* ADRF6780_REG_ALARM_READBACK Map */
0040 #define ADRF6780_PARITY_ERROR_MSK       BIT(15)
0041 #define ADRF6780_TOO_FEW_ERRORS_MSK     BIT(14)
0042 #define ADRF6780_TOO_MANY_ERRORS_MSK        BIT(13)
0043 #define ADRF6780_ADDRESS_RANGE_ERROR_MSK    BIT(12)
0044
0045 /* ADRF6780_REG_ENABLE Map */
0046 #define ADRF6780_VGA_BUFFER_EN_MSK      BIT(8)
0047 #define ADRF6780_DETECTOR_EN_MSK        BIT(7)
0048 #define ADRF6780_LO_BUFFER_EN_MSK       BIT(6)
0049 #define ADRF6780_IF_MODE_EN_MSK         BIT(5)
0050 #define ADRF6780_IQ_MODE_EN_MSK         BIT(4)
0051 #define ADRF6780_LO_X2_EN_MSK           BIT(3)
0052 #define ADRF6780_LO_PPF_EN_MSK          BIT(2)
0053 #define ADRF6780_LO_EN_MSK          BIT(1)
0054 #define ADRF6780_UC_BIAS_EN_MSK         BIT(0)
0055
0056 /* ADRF6780_REG_LINEARIZE Map */
0057 #define ADRF6780_RDAC_LINEARIZE_MSK     GENMASK(7, 0)
0058
0059 /* ADRF6780_REG_LO_PATH Map */
0060 #define ADRF6780_LO_SIDEBAND_MSK        BIT(10)
0061 #define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK  GENMASK(7, 4)
0062 #define ADRF6780_I_PATH_PHASE_ACCURACY_MSK  GENMASK(3, 0)
0063
0064 /* ADRF6780_REG_ADC_CONTROL Map */
0065 #define ADRF6780_VDET_OUTPUT_SELECT_MSK     BIT(3)
0066 #define ADRF6780_ADC_START_MSK          BIT(2)
0067 #define ADRF6780_ADC_EN_MSK         BIT(1)
0068 #define ADRF6780_ADC_CLOCK_EN_MSK       BIT(0)
0069
0070 /* ADRF6780_REG_ADC_OUTPUT Map */
0071 #define ADRF6780_ADC_STATUS_MSK         BIT(8)
0072 #define ADRF6780_ADC_VALUE_MSK          GENMASK(7, 0)
0073
0074 struct adrf6780_state {
0075     struct spi_device   *spi;
0076     struct clk      *clkin;
0077     /* Protect against concurrent accesses to the device */
0078     struct mutex        lock;
0079     bool            vga_buff_en;
0080     bool            lo_buff_en;
0081     bool            if_mode_en;
0082     bool            iq_mode_en;
0083     bool            lo_x2_en;
0084     bool            lo_ppf_en;
0085     bool            lo_en;
0086     bool            uc_bias_en;
0087     bool            lo_sideband;
0088     bool            vdet_out_en;
0089     u8          data[3] __aligned(IIO_DMA_MINALIGN);
0090 };
0091
0092 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
0093                    unsigned int *val)
0094 {
0095     int ret;
0096     struct spi_transfer t = {0};
0097
0098     st->data[0] = 0x80 | (reg << 1);
0099     st->data[1] = 0x0;
0100     st->data[2] = 0x0;
0101
0102     t.rx_buf = &st->data[0];
0103     t.tx_buf = &st->data[0];
0104     t.len = 3;
0105
0106     ret = spi_sync_transfer(st->spi, &t, 1);
0107     if (ret)
0108         return ret;
0109
0110     *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0);
0111
0112     return ret;
0113 }
0114
0115 static int adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
0116                  unsigned int *val)
0117 {
0118     int ret;
0119
0120     mutex_lock(&st->lock);
0121     ret = __adrf6780_spi_read(st, reg, val);
0122     mutex_unlock(&st->lock);
0123
0124     return ret;
0125 }
0126
0127 static int __adrf6780_spi_write(struct adrf6780_state *st,
0128                 unsigned int reg,
0129                 unsigned int val)
0130 {
0131     put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]);
0132
0133     return spi_write(st->spi, &st->data[0], 3);
0134 }
0135
0136 static int adrf6780_spi_write(struct adrf6780_state *st, unsigned int reg,
0137                   unsigned int val)
0138 {
0139     int ret;
0140
0141     mutex_lock(&st->lock);
0142     ret = __adrf6780_spi_write(st, reg, val);
0143     mutex_unlock(&st->lock);
0144
0145     return ret;
0146 }
0147
0148 static int __adrf6780_spi_update_bits(struct adrf6780_state *st,
0149                       unsigned int reg, unsigned int mask,
0150                       unsigned int val)
0151 {
0152     int ret;
0153     unsigned int data, temp;
0154
0155     ret = __adrf6780_spi_read(st, reg, &data);
0156     if (ret)
0157         return ret;
0158
0159     temp = (data & ~mask) | (val & mask);
0160
0161     return __adrf6780_spi_write(st, reg, temp);
0162 }
0163
0164 static int adrf6780_spi_update_bits(struct adrf6780_state *st, unsigned int reg,
0165                     unsigned int mask, unsigned int val)
0166 {
0167     int ret;
0168
0169     mutex_lock(&st->lock);
0170     ret = __adrf6780_spi_update_bits(st, reg, mask, val);
0171     mutex_unlock(&st->lock);
0172
0173     return ret;
0174 }
0175
0176 static int adrf6780_read_adc_raw(struct adrf6780_state *st, unsigned int *read_val)
0177 {
0178     int ret;
0179
0180     mutex_lock(&st->lock);
0181
0182     ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
0183                      ADRF6780_ADC_EN_MSK |
0184                      ADRF6780_ADC_CLOCK_EN_MSK |
0185                      ADRF6780_ADC_START_MSK,
0186                      FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) |
0187                      FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) |
0188                      FIELD_PREP(ADRF6780_ADC_START_MSK, 1));
0189     if (ret)
0190         goto exit;
0191
0192     /* Recommended delay for the ADC to be ready*/
0193     usleep_range(200, 250);
0194
0195     ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);
0196     if (ret)
0197         goto exit;
0198
0199     if (!(*read_val & ADRF6780_ADC_STATUS_MSK)) {
0200         ret = -EINVAL;
0201         goto exit;
0202     }
0203
0204     ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
0205                      ADRF6780_ADC_START_MSK,
0206                      FIELD_PREP(ADRF6780_ADC_START_MSK, 0));
0207     if (ret)
0208         goto exit;
0209
0210     ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);
0211
0212 exit:
0213     mutex_unlock(&st->lock);
0214     return ret;
0215 }
0216
0217 static int adrf6780_read_raw(struct iio_dev *indio_dev,
0218                  struct iio_chan_spec const *chan,
0219                  int *val, int *val2, long info)
0220 {
0221     struct adrf6780_state *dev = iio_priv(indio_dev);
0222     unsigned int data;
0223     int ret;
0224
0225     switch (info) {
0226     case IIO_CHAN_INFO_RAW:
0227         ret = adrf6780_read_adc_raw(dev, &data);
0228         if (ret)
0229             return ret;
0230
0231         *val = data & ADRF6780_ADC_VALUE_MSK;
0232
0233         return IIO_VAL_INT;
0234
0235     case IIO_CHAN_INFO_SCALE:
0236         ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data);
0237         if (ret)
0238             return ret;
0239
0240         *val = data & ADRF6780_RDAC_LINEARIZE_MSK;
0241
0242         return IIO_VAL_INT;
0243     case IIO_CHAN_INFO_PHASE:
0244         ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data);
0245         if (ret)
0246             return ret;
0247
0248         switch (chan->channel2) {
0249         case IIO_MOD_I:
0250             *val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK;
0251
0252             return IIO_VAL_INT;
0253         case IIO_MOD_Q:
0254             *val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,
0255                      data);
0256
0257             return IIO_VAL_INT;
0258         default:
0259             return -EINVAL;
0260         }
0261     default:
0262         return -EINVAL;
0263     }
0264 }
0265
0266 static int adrf6780_write_raw(struct iio_dev *indio_dev,
0267                   struct iio_chan_spec const *chan,
0268                   int val, int val2, long info)
0269 {
0270     struct adrf6780_state *st = iio_priv(indio_dev);
0271
0272     switch (info) {
0273     case IIO_CHAN_INFO_SCALE:
0274         return adrf6780_spi_write(st, ADRF6780_REG_LINEARIZE, val);
0275     case IIO_CHAN_INFO_PHASE:
0276         switch (chan->channel2) {
0277         case IIO_MOD_I:
0278             return adrf6780_spi_update_bits(st,
0279                 ADRF6780_REG_LO_PATH,
0280                 ADRF6780_I_PATH_PHASE_ACCURACY_MSK,
0281                 FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val));
0282         case IIO_MOD_Q:
0283             return adrf6780_spi_update_bits(st,
0284                 ADRF6780_REG_LO_PATH,
0285                 ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,
0286                 FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val));
0287         default:
0288             return -EINVAL;
0289         }
0290     default:
0291         return -EINVAL;
0292     }
0293 }
0294
0295 static int adrf6780_reg_access(struct iio_dev *indio_dev,
0296                    unsigned int reg,
0297                    unsigned int write_val,
0298                    unsigned int *read_val)
0299 {
0300     struct adrf6780_state *st = iio_priv(indio_dev);
0301
0302     if (read_val)
0303         return adrf6780_spi_read(st, reg, read_val);
0304     else
0305         return adrf6780_spi_write(st, reg, write_val);
0306 }
0307
0308 static const struct iio_info adrf6780_info = {
0309     .read_raw = adrf6780_read_raw,
0310     .write_raw = adrf6780_write_raw,
0311     .debugfs_reg_access = &adrf6780_reg_access,
0312 };
0313
0314 #define ADRF6780_CHAN_ADC(_channel) {           \
0315     .type = IIO_ALTVOLTAGE,             \
0316     .output = 0,                    \
0317     .indexed = 1,                   \
0318     .channel = _channel,                \
0319     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)    \
0320 }
0321
0322 #define ADRF6780_CHAN_RDAC(_channel) {          \
0323     .type = IIO_ALTVOLTAGE,             \
0324     .output = 1,                    \
0325     .indexed = 1,                   \
0326     .channel = _channel,                \
0327     .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE)  \
0328 }
0329
0330 #define ADRF6780_CHAN_IQ_PHASE(_channel, rf_comp) {     \
0331     .type = IIO_ALTVOLTAGE,                 \
0332     .modified = 1,                      \
0333     .output = 1,                        \
0334     .indexed = 1,                       \
0335     .channel2 = IIO_MOD_##rf_comp,              \
0336     .channel = _channel,                    \
0337     .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE)      \
0338 }
0339
0340 static const struct iio_chan_spec adrf6780_channels[] = {
0341     ADRF6780_CHAN_ADC(0),
0342     ADRF6780_CHAN_RDAC(0),
0343     ADRF6780_CHAN_IQ_PHASE(0, I),
0344     ADRF6780_CHAN_IQ_PHASE(0, Q),
0345 };
0346
0347 static int adrf6780_reset(struct adrf6780_state *st)
0348 {
0349     int ret;
0350     struct spi_device *spi = st->spi;
0351
0352     ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,
0353                      ADRF6780_SOFT_RESET_MSK,
0354                      FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1));
0355     if (ret) {
0356         dev_err(&spi->dev, "ADRF6780 SPI software reset failed.\n");
0357         return ret;
0358     }
0359
0360     ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,
0361                      ADRF6780_SOFT_RESET_MSK,
0362                      FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0));
0363     if (ret) {
0364         dev_err(&spi->dev, "ADRF6780 SPI software reset disable failed.\n");
0365         return ret;
0366     }
0367
0368     return 0;
0369 }
0370
0371 static int adrf6780_init(struct adrf6780_state *st)
0372 {
0373     int ret;
0374     unsigned int chip_id, enable_reg, enable_reg_msk;
0375     struct spi_device *spi = st->spi;
0376
0377     /* Perform a software reset */
0378     ret = adrf6780_reset(st);
0379     if (ret)
0380         return ret;
0381
0382     ret = __adrf6780_spi_read(st, ADRF6780_REG_CONTROL, &chip_id);
0383     if (ret)
0384         return ret;
0385
0386     chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id);
0387     if (chip_id != ADRF6780_CHIP_ID) {
0388         dev_err(&spi->dev, "ADRF6780 Invalid Chip ID.\n");
0389         return -EINVAL;
0390     }
0391
0392     enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK |
0393             ADRF6780_DETECTOR_EN_MSK |
0394             ADRF6780_LO_BUFFER_EN_MSK |
0395             ADRF6780_IF_MODE_EN_MSK |
0396             ADRF6780_IQ_MODE_EN_MSK |
0397             ADRF6780_LO_X2_EN_MSK |
0398             ADRF6780_LO_PPF_EN_MSK |
0399             ADRF6780_LO_EN_MSK |
0400             ADRF6780_UC_BIAS_EN_MSK;
0401
0402     enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, st->vga_buff_en) |
0403             FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) |
0404             FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, st->lo_buff_en) |
0405             FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, st->if_mode_en) |
0406             FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, st->iq_mode_en) |
0407             FIELD_PREP(ADRF6780_LO_X2_EN_MSK, st->lo_x2_en) |
0408             FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, st->lo_ppf_en) |
0409             FIELD_PREP(ADRF6780_LO_EN_MSK, st->lo_en) |
0410             FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, st->uc_bias_en);
0411
0412     ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ENABLE,
0413                      enable_reg_msk, enable_reg);
0414     if (ret)
0415         return ret;
0416
0417     ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_LO_PATH,
0418                      ADRF6780_LO_SIDEBAND_MSK,
0419                      FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, st->lo_sideband));
0420     if (ret)
0421         return ret;
0422
0423     return __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
0424         ADRF6780_VDET_OUTPUT_SELECT_MSK,
0425         FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, st->vdet_out_en));
0426 }
0427
0428 static void adrf6780_properties_parse(struct adrf6780_state *st)
0429 {
0430     struct spi_device *spi = st->spi;
0431
0432     st->vga_buff_en = device_property_read_bool(&spi->dev, "adi,vga-buff-en");
0433     st->lo_buff_en = device_property_read_bool(&spi->dev, "adi,lo-buff-en");
0434     st->if_mode_en = device_property_read_bool(&spi->dev, "adi,if-mode-en");
0435     st->iq_mode_en = device_property_read_bool(&spi->dev, "adi,iq-mode-en");
0436     st->lo_x2_en = device_property_read_bool(&spi->dev, "adi,lo-x2-en");
0437     st->lo_ppf_en = device_property_read_bool(&spi->dev, "adi,lo-ppf-en");
0438     st->lo_en = device_property_read_bool(&spi->dev, "adi,lo-en");
0439     st->uc_bias_en = device_property_read_bool(&spi->dev, "adi,uc-bias-en");
0440     st->lo_sideband = device_property_read_bool(&spi->dev, "adi,lo-sideband");
0441     st->vdet_out_en = device_property_read_bool(&spi->dev, "adi,vdet-out-en");
0442 }
0443
0444 static void adrf6780_clk_disable(void *data)
0445 {
0446     clk_disable_unprepare(data);
0447 }
0448
0449 static void adrf6780_powerdown(void *data)
0450 {
0451     /* Disable all components in the Enable Register */
0452     adrf6780_spi_write(data, ADRF6780_REG_ENABLE, 0x0);
0453 }
0454
0455 static int adrf6780_probe(struct spi_device *spi)
0456 {
0457     struct iio_dev *indio_dev;
0458     struct adrf6780_state *st;
0459     int ret;
0460
0461     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0462     if (!indio_dev)
0463         return -ENOMEM;
0464
0465     st = iio_priv(indio_dev);
0466
0467     indio_dev->info = &adrf6780_info;
0468     indio_dev->name = "adrf6780";
0469     indio_dev->channels = adrf6780_channels;
0470     indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels);
0471
0472     st->spi = spi;
0473
0474     adrf6780_properties_parse(st);
0475
0476     st->clkin = devm_clk_get(&spi->dev, "lo_in");
0477     if (IS_ERR(st->clkin))
0478         return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
0479                      "failed to get the LO input clock\n");
0480
0481     ret = clk_prepare_enable(st->clkin);
0482     if (ret)
0483         return ret;
0484
0485     ret = devm_add_action_or_reset(&spi->dev, adrf6780_clk_disable,
0486                        st->clkin);
0487     if (ret)
0488         return ret;
0489
0490     mutex_init(&st->lock);
0491
0492     ret = adrf6780_init(st);
0493     if (ret)
0494         return ret;
0495
0496     ret = devm_add_action_or_reset(&spi->dev, adrf6780_powerdown, st);
0497     if (ret)
0498         return ret;
0499
0500     return devm_iio_device_register(&spi->dev, indio_dev);
0501 }
0502
0503 static const struct spi_device_id adrf6780_id[] = {
0504     { "adrf6780", 0 },
0505     {}
0506 };
0507 MODULE_DEVICE_TABLE(spi, adrf6780_id);
0508
0509 static const struct of_device_id adrf6780_of_match[] = {
0510     { .compatible = "adi,adrf6780" },
0511     {}
0512 };
0513 MODULE_DEVICE_TABLE(of, adrf6780_of_match);
0514
0515 static struct spi_driver adrf6780_driver = {
0516     .driver = {
0517         .name = "adrf6780",
0518         .of_match_table = adrf6780_of_match,
0519     },
0520     .probe = adrf6780_probe,
0521     .id_table = adrf6780_id,
0522 };
0523 module_spi_driver(adrf6780_driver);
0524
0525 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
0526 MODULE_DESCRIPTION("Analog Devices ADRF6780");
0527 MODULE_LICENSE("GPL v2");