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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADMV1014 driver
0004  *
0005  * Copyright 2022 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/device.h>
0013 #include <linux/iio/iio.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/notifier.h>
0017 #include <linux/property.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/units.h>
0021 
0022 #include <asm/unaligned.h>
0023 
0024 /* ADMV1014 Register Map */
0025 #define ADMV1014_REG_SPI_CONTROL        0x00
0026 #define ADMV1014_REG_ALARM          0x01
0027 #define ADMV1014_REG_ALARM_MASKS        0x02
0028 #define ADMV1014_REG_ENABLE         0x03
0029 #define ADMV1014_REG_QUAD           0x04
0030 #define ADMV1014_REG_LO_AMP_PHASE_ADJUST1   0x05
0031 #define ADMV1014_REG_MIXER          0x07
0032 #define ADMV1014_REG_IF_AMP         0x08
0033 #define ADMV1014_REG_IF_AMP_BB_AMP      0x09
0034 #define ADMV1014_REG_BB_AMP_AGC         0x0A
0035 #define ADMV1014_REG_VVA_TEMP_COMP      0x0B
0036 
0037 /* ADMV1014_REG_SPI_CONTROL Map */
0038 #define ADMV1014_PARITY_EN_MSK          BIT(15)
0039 #define ADMV1014_SPI_SOFT_RESET_MSK     BIT(14)
0040 #define ADMV1014_CHIP_ID_MSK            GENMASK(11, 4)
0041 #define ADMV1014_CHIP_ID            0x9
0042 #define ADMV1014_REVISION_ID_MSK        GENMASK(3, 0)
0043 
0044 /* ADMV1014_REG_ALARM Map */
0045 #define ADMV1014_PARITY_ERROR_MSK       BIT(15)
0046 #define ADMV1014_TOO_FEW_ERRORS_MSK     BIT(14)
0047 #define ADMV1014_TOO_MANY_ERRORS_MSK        BIT(13)
0048 #define ADMV1014_ADDRESS_RANGE_ERROR_MSK    BIT(12)
0049 
0050 /* ADMV1014_REG_ENABLE Map */
0051 #define ADMV1014_IBIAS_PD_MSK           BIT(14)
0052 #define ADMV1014_P1DB_COMPENSATION_MSK      GENMASK(13, 12)
0053 #define ADMV1014_IF_AMP_PD_MSK          BIT(11)
0054 #define ADMV1014_QUAD_BG_PD_MSK         BIT(9)
0055 #define ADMV1014_BB_AMP_PD_MSK          BIT(8)
0056 #define ADMV1014_QUAD_IBIAS_PD_MSK      BIT(7)
0057 #define ADMV1014_DET_EN_MSK         BIT(6)
0058 #define ADMV1014_BG_PD_MSK          BIT(5)
0059 
0060 /* ADMV1014_REG_QUAD Map */
0061 #define ADMV1014_QUAD_SE_MODE_MSK       GENMASK(9, 6)
0062 #define ADMV1014_QUAD_FILTERS_MSK       GENMASK(3, 0)
0063 
0064 /* ADMV1014_REG_LO_AMP_PHASE_ADJUST1 Map */
0065 #define ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK    GENMASK(15, 9)
0066 #define ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK    GENMASK(8, 2)
0067 
0068 /* ADMV1014_REG_MIXER Map */
0069 #define ADMV1014_MIXER_VGATE_MSK        GENMASK(15, 9)
0070 #define ADMV1014_DET_PROG_MSK           GENMASK(6, 0)
0071 
0072 /* ADMV1014_REG_IF_AMP Map */
0073 #define ADMV1014_IF_AMP_COARSE_GAIN_I_MSK   GENMASK(11, 8)
0074 #define ADMV1014_IF_AMP_FINE_GAIN_Q_MSK     GENMASK(7, 4)
0075 #define ADMV1014_IF_AMP_FINE_GAIN_I_MSK     GENMASK(3, 0)
0076 
0077 /* ADMV1014_REG_IF_AMP_BB_AMP Map */
0078 #define ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK   GENMASK(15, 12)
0079 #define ADMV1014_BB_AMP_OFFSET_Q_MSK        GENMASK(9, 5)
0080 #define ADMV1014_BB_AMP_OFFSET_I_MSK        GENMASK(4, 0)
0081 
0082 /* ADMV1014_REG_BB_AMP_AGC Map */
0083 #define ADMV1014_BB_AMP_REF_GEN_MSK     GENMASK(6, 3)
0084 #define ADMV1014_BB_AMP_GAIN_CTRL_MSK       GENMASK(2, 1)
0085 #define ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK  BIT(0)
0086 
0087 /* ADMV1014_REG_VVA_TEMP_COMP Map */
0088 #define ADMV1014_VVA_TEMP_COMP_MSK      GENMASK(15, 0)
0089 
0090 /* ADMV1014 Miscellaneous Defines */
0091 #define ADMV1014_READ               BIT(7)
0092 #define ADMV1014_REG_ADDR_READ_MSK      GENMASK(6, 1)
0093 #define ADMV1014_REG_ADDR_WRITE_MSK     GENMASK(22, 17)
0094 #define ADMV1014_REG_DATA_MSK           GENMASK(16, 1)
0095 #define ADMV1014_NUM_REGULATORS         9
0096 
0097 enum {
0098     ADMV1014_IQ_MODE,
0099     ADMV1014_IF_MODE,
0100 };
0101 
0102 enum {
0103     ADMV1014_SE_MODE_POS = 6,
0104     ADMV1014_SE_MODE_NEG = 9,
0105     ADMV1014_SE_MODE_DIFF = 12,
0106 };
0107 
0108 enum {
0109     ADMV1014_CALIBSCALE_COARSE,
0110     ADMV1014_CALIBSCALE_FINE,
0111 };
0112 
0113 static const int detector_table[] = {0, 1, 2, 4, 8, 16, 32, 64};
0114 
0115 static const char * const input_mode_names[] = { "iq", "if" };
0116 
0117 static const char * const quad_se_mode_names[] = { "se-pos", "se-neg", "diff" };
0118 
0119 struct admv1014_state {
0120     struct spi_device       *spi;
0121     struct clk          *clkin;
0122     struct notifier_block       nb;
0123     /* Protect against concurrent accesses to the device and to data*/
0124     struct mutex            lock;
0125     struct regulator_bulk_data  regulators[ADMV1014_NUM_REGULATORS];
0126     unsigned int            input_mode;
0127     unsigned int            quad_se_mode;
0128     unsigned int            p1db_comp;
0129     bool                det_en;
0130     u8              data[3] __aligned(IIO_DMA_MINALIGN);
0131 };
0132 
0133 static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114,
0134                     117, 118, 119, 120, 122, 123, 44, 45};
0135 
0136 static int __admv1014_spi_read(struct admv1014_state *st, unsigned int reg,
0137                    unsigned int *val)
0138 {
0139     struct spi_transfer t = {};
0140     int ret;
0141 
0142     st->data[0] = ADMV1014_READ | FIELD_PREP(ADMV1014_REG_ADDR_READ_MSK, reg);
0143     st->data[1] = 0;
0144     st->data[2] = 0;
0145 
0146     t.rx_buf = &st->data[0];
0147     t.tx_buf = &st->data[0];
0148     t.len = sizeof(st->data);
0149 
0150     ret = spi_sync_transfer(st->spi, &t, 1);
0151     if (ret)
0152         return ret;
0153 
0154     *val = FIELD_GET(ADMV1014_REG_DATA_MSK, get_unaligned_be24(&st->data[0]));
0155 
0156     return ret;
0157 }
0158 
0159 static int admv1014_spi_read(struct admv1014_state *st, unsigned int reg,
0160                  unsigned int *val)
0161 {
0162     int ret;
0163 
0164     mutex_lock(&st->lock);
0165     ret = __admv1014_spi_read(st, reg, val);
0166     mutex_unlock(&st->lock);
0167 
0168     return ret;
0169 }
0170 
0171 static int __admv1014_spi_write(struct admv1014_state *st,
0172                 unsigned int reg,
0173                 unsigned int val)
0174 {
0175     put_unaligned_be24(FIELD_PREP(ADMV1014_REG_DATA_MSK, val) |
0176                FIELD_PREP(ADMV1014_REG_ADDR_WRITE_MSK, reg), &st->data[0]);
0177 
0178     return spi_write(st->spi, &st->data[0], 3);
0179 }
0180 
0181 static int admv1014_spi_write(struct admv1014_state *st, unsigned int reg,
0182                   unsigned int val)
0183 {
0184     int ret;
0185 
0186     mutex_lock(&st->lock);
0187     ret = __admv1014_spi_write(st, reg, val);
0188     mutex_unlock(&st->lock);
0189 
0190     return ret;
0191 }
0192 
0193 static int __admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg,
0194                       unsigned int mask, unsigned int val)
0195 {
0196     unsigned int data, temp;
0197     int ret;
0198 
0199     ret = __admv1014_spi_read(st, reg, &data);
0200     if (ret)
0201         return ret;
0202 
0203     temp = (data & ~mask) | (val & mask);
0204 
0205     return __admv1014_spi_write(st, reg, temp);
0206 }
0207 
0208 static int admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg,
0209                     unsigned int mask, unsigned int val)
0210 {
0211     int ret;
0212 
0213     mutex_lock(&st->lock);
0214     ret = __admv1014_spi_update_bits(st, reg, mask, val);
0215     mutex_unlock(&st->lock);
0216 
0217     return ret;
0218 }
0219 
0220 static int admv1014_update_quad_filters(struct admv1014_state *st)
0221 {
0222     unsigned int filt_raw;
0223     u64 rate = clk_get_rate(st->clkin);
0224 
0225     if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ))
0226         filt_raw = 15;
0227     else if (rate > (7000 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ))
0228         filt_raw = 10;
0229     else if (rate > (8000 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ))
0230         filt_raw = 5;
0231     else
0232         filt_raw = 0;
0233 
0234     return __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD,
0235                     ADMV1014_QUAD_FILTERS_MSK,
0236                     FIELD_PREP(ADMV1014_QUAD_FILTERS_MSK, filt_raw));
0237 }
0238 
0239 static int admv1014_update_vcm_settings(struct admv1014_state *st)
0240 {
0241     unsigned int i, vcm_mv, vcm_comp, bb_sw_hl_cm;
0242     int ret;
0243 
0244     vcm_mv = regulator_get_voltage(st->regulators[0].consumer) / 1000;
0245     for (i = 0; i < ARRAY_SIZE(mixer_vgate_table); i++) {
0246         vcm_comp = 1050 + mult_frac(i, 450, 8);
0247         if (vcm_mv != vcm_comp)
0248             continue;
0249 
0250         ret = __admv1014_spi_update_bits(st, ADMV1014_REG_MIXER,
0251                          ADMV1014_MIXER_VGATE_MSK,
0252                          FIELD_PREP(ADMV1014_MIXER_VGATE_MSK,
0253                                 mixer_vgate_table[i]));
0254         if (ret)
0255             return ret;
0256 
0257         bb_sw_hl_cm = ~(i / 8);
0258         bb_sw_hl_cm = FIELD_PREP(ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, bb_sw_hl_cm);
0259 
0260         return __admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC,
0261                           ADMV1014_BB_AMP_REF_GEN_MSK |
0262                           ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK,
0263                           FIELD_PREP(ADMV1014_BB_AMP_REF_GEN_MSK, i) |
0264                           bb_sw_hl_cm);
0265     }
0266 
0267     return -EINVAL;
0268 }
0269 
0270 static int admv1014_read_raw(struct iio_dev *indio_dev,
0271                  struct iio_chan_spec const *chan,
0272                  int *val, int *val2, long info)
0273 {
0274     struct admv1014_state *st = iio_priv(indio_dev);
0275     unsigned int data;
0276     int ret;
0277 
0278     switch (info) {
0279     case IIO_CHAN_INFO_OFFSET:
0280         ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data);
0281         if (ret)
0282             return ret;
0283 
0284         if (chan->channel2 == IIO_MOD_I)
0285             *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_I_MSK, data);
0286         else
0287             *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_Q_MSK, data);
0288 
0289         return IIO_VAL_INT;
0290     case IIO_CHAN_INFO_PHASE:
0291         ret = admv1014_spi_read(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, &data);
0292         if (ret)
0293             return ret;
0294 
0295         if (chan->channel2 == IIO_MOD_I)
0296             *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, data);
0297         else
0298             *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, data);
0299 
0300         return IIO_VAL_INT;
0301     case IIO_CHAN_INFO_SCALE:
0302         ret = admv1014_spi_read(st, ADMV1014_REG_MIXER, &data);
0303         if (ret)
0304             return ret;
0305 
0306         *val = FIELD_GET(ADMV1014_DET_PROG_MSK, data);
0307         return IIO_VAL_INT;
0308     case IIO_CHAN_INFO_CALIBSCALE:
0309         ret = admv1014_spi_read(st, ADMV1014_REG_BB_AMP_AGC, &data);
0310         if (ret)
0311             return ret;
0312 
0313         *val = FIELD_GET(ADMV1014_BB_AMP_GAIN_CTRL_MSK, data);
0314         return IIO_VAL_INT;
0315     default:
0316         return -EINVAL;
0317     }
0318 }
0319 
0320 static int admv1014_write_raw(struct iio_dev *indio_dev,
0321                   struct iio_chan_spec const *chan,
0322                   int val, int val2, long info)
0323 {
0324     int data;
0325     unsigned int msk;
0326     struct admv1014_state *st = iio_priv(indio_dev);
0327 
0328     switch (info) {
0329     case IIO_CHAN_INFO_OFFSET:
0330         if (chan->channel2 == IIO_MOD_I) {
0331             msk = ADMV1014_BB_AMP_OFFSET_I_MSK;
0332             data = FIELD_PREP(ADMV1014_BB_AMP_OFFSET_I_MSK, val);
0333         } else {
0334             msk = ADMV1014_BB_AMP_OFFSET_Q_MSK;
0335             data = FIELD_PREP(ADMV1014_BB_AMP_OFFSET_Q_MSK, val);
0336         }
0337 
0338         return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, msk, data);
0339     case IIO_CHAN_INFO_PHASE:
0340         if (chan->channel2 == IIO_MOD_I) {
0341             msk = ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK;
0342             data = FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, val);
0343         } else {
0344             msk = ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK;
0345             data = FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, val);
0346         }
0347 
0348         return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, msk, data);
0349     case IIO_CHAN_INFO_SCALE:
0350         return admv1014_spi_update_bits(st, ADMV1014_REG_MIXER,
0351                         ADMV1014_DET_PROG_MSK,
0352                         FIELD_PREP(ADMV1014_DET_PROG_MSK, val));
0353     case IIO_CHAN_INFO_CALIBSCALE:
0354         return admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC,
0355                         ADMV1014_BB_AMP_GAIN_CTRL_MSK,
0356                         FIELD_PREP(ADMV1014_BB_AMP_GAIN_CTRL_MSK, val));
0357     default:
0358         return -EINVAL;
0359     }
0360 }
0361 
0362 static ssize_t admv1014_read(struct iio_dev *indio_dev,
0363                  uintptr_t private,
0364                  const struct iio_chan_spec *chan,
0365                  char *buf)
0366 {
0367     struct admv1014_state *st = iio_priv(indio_dev);
0368     unsigned int data;
0369     int ret;
0370 
0371     switch (private) {
0372     case ADMV1014_CALIBSCALE_COARSE:
0373         if (chan->channel2 == IIO_MOD_I) {
0374             ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data);
0375             if (ret)
0376                 return ret;
0377 
0378             data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data);
0379         } else {
0380             ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data);
0381             if (ret)
0382                 return ret;
0383 
0384             data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data);
0385         }
0386         break;
0387     case ADMV1014_CALIBSCALE_FINE:
0388         ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data);
0389         if (ret)
0390             return ret;
0391 
0392         if (chan->channel2 == IIO_MOD_I)
0393             data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data);
0394         else
0395             data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data);
0396         break;
0397     default:
0398         return -EINVAL;
0399     }
0400 
0401     return sysfs_emit(buf, "%u\n", data);
0402 }
0403 
0404 static ssize_t admv1014_write(struct iio_dev *indio_dev,
0405                   uintptr_t private,
0406                   const struct iio_chan_spec *chan,
0407                   const char *buf, size_t len)
0408 {
0409     struct admv1014_state *st = iio_priv(indio_dev);
0410     unsigned int data, addr, msk;
0411     int ret;
0412 
0413     ret = kstrtouint(buf, 10, &data);
0414     if (ret)
0415         return ret;
0416 
0417     switch (private) {
0418     case ADMV1014_CALIBSCALE_COARSE:
0419         if (chan->channel2 == IIO_MOD_I) {
0420             addr = ADMV1014_REG_IF_AMP;
0421             msk = ADMV1014_IF_AMP_COARSE_GAIN_I_MSK;
0422             data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data);
0423         } else {
0424             addr = ADMV1014_REG_IF_AMP_BB_AMP;
0425             msk = ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK;
0426             data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data);
0427         }
0428         break;
0429     case ADMV1014_CALIBSCALE_FINE:
0430         addr = ADMV1014_REG_IF_AMP;
0431 
0432         if (chan->channel2 == IIO_MOD_I) {
0433             msk = ADMV1014_IF_AMP_FINE_GAIN_I_MSK;
0434             data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data);
0435         } else {
0436             msk = ADMV1014_IF_AMP_FINE_GAIN_Q_MSK;
0437             data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data);
0438         }
0439         break;
0440     default:
0441         return -EINVAL;
0442     }
0443 
0444     ret = admv1014_spi_update_bits(st, addr, msk, data);
0445 
0446     return ret ? ret : len;
0447 }
0448 
0449 static int admv1014_read_avail(struct iio_dev *indio_dev,
0450                    struct iio_chan_spec const *chan,
0451                    const int **vals, int *type, int *length,
0452                    long info)
0453 {
0454     switch (info) {
0455     case IIO_CHAN_INFO_SCALE:
0456         *vals = detector_table;
0457         *type = IIO_VAL_INT;
0458         *length = ARRAY_SIZE(detector_table);
0459 
0460         return IIO_AVAIL_LIST;
0461     default:
0462         return -EINVAL;
0463     }
0464 }
0465 
0466 static int admv1014_reg_access(struct iio_dev *indio_dev,
0467                    unsigned int reg,
0468                    unsigned int write_val,
0469                    unsigned int *read_val)
0470 {
0471     struct admv1014_state *st = iio_priv(indio_dev);
0472 
0473     if (read_val)
0474         return admv1014_spi_read(st, reg, read_val);
0475     else
0476         return admv1014_spi_write(st, reg, write_val);
0477 }
0478 
0479 static const struct iio_info admv1014_info = {
0480     .read_raw = admv1014_read_raw,
0481     .write_raw = admv1014_write_raw,
0482     .read_avail = &admv1014_read_avail,
0483     .debugfs_reg_access = &admv1014_reg_access,
0484 };
0485 
0486 static const char * const admv1014_reg_name[] = {
0487      "vcm", "vcc-if-bb", "vcc-vga", "vcc-vva", "vcc-lna-3p3",
0488      "vcc-lna-1p5", "vcc-bg", "vcc-quad", "vcc-mixer"
0489 };
0490 
0491 static int admv1014_freq_change(struct notifier_block *nb, unsigned long action, void *data)
0492 {
0493     struct admv1014_state *st = container_of(nb, struct admv1014_state, nb);
0494     int ret;
0495 
0496     if (action == POST_RATE_CHANGE) {
0497         mutex_lock(&st->lock);
0498         ret = notifier_from_errno(admv1014_update_quad_filters(st));
0499         mutex_unlock(&st->lock);
0500         return ret;
0501     }
0502 
0503     return NOTIFY_OK;
0504 }
0505 
0506 #define _ADMV1014_EXT_INFO(_name, _shared, _ident) { \
0507         .name = _name, \
0508         .read = admv1014_read, \
0509         .write = admv1014_write, \
0510         .private = _ident, \
0511         .shared = _shared, \
0512 }
0513 
0514 static const struct iio_chan_spec_ext_info admv1014_ext_info[] = {
0515     _ADMV1014_EXT_INFO("calibscale_coarse", IIO_SEPARATE, ADMV1014_CALIBSCALE_COARSE),
0516     _ADMV1014_EXT_INFO("calibscale_fine", IIO_SEPARATE, ADMV1014_CALIBSCALE_FINE),
0517     { }
0518 };
0519 
0520 #define ADMV1014_CHAN_IQ(_channel, rf_comp) {               \
0521     .type = IIO_ALTVOLTAGE,                     \
0522     .modified = 1,                          \
0523     .output = 0,                            \
0524     .indexed = 1,                           \
0525     .channel2 = IIO_MOD_##rf_comp,                  \
0526     .channel = _channel,                        \
0527     .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) |        \
0528         BIT(IIO_CHAN_INFO_OFFSET),              \
0529     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE),  \
0530     }
0531 
0532 #define ADMV1014_CHAN_IF(_channel, rf_comp) {               \
0533     .type = IIO_ALTVOLTAGE,                     \
0534     .modified = 1,                          \
0535     .output = 0,                            \
0536     .indexed = 1,                           \
0537     .channel2 = IIO_MOD_##rf_comp,                  \
0538     .channel = _channel,                        \
0539     .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) |        \
0540         BIT(IIO_CHAN_INFO_OFFSET),              \
0541     }
0542 
0543 #define ADMV1014_CHAN_POWER(_channel) {                 \
0544     .type = IIO_POWER,                      \
0545     .output = 0,                            \
0546     .indexed = 1,                           \
0547     .channel = _channel,                        \
0548     .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE),         \
0549     .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
0550     }
0551 
0552 #define ADMV1014_CHAN_CALIBSCALE(_channel, rf_comp, _admv1014_ext_info) {   \
0553     .type = IIO_ALTVOLTAGE,                         \
0554     .modified = 1,                              \
0555     .output = 0,                                \
0556     .indexed = 1,                               \
0557     .channel2 = IIO_MOD_##rf_comp,                      \
0558     .channel = _channel,                            \
0559     .ext_info = _admv1014_ext_info,                     \
0560     }
0561 
0562 static const struct iio_chan_spec admv1014_channels_iq[] = {
0563     ADMV1014_CHAN_IQ(0, I),
0564     ADMV1014_CHAN_IQ(0, Q),
0565     ADMV1014_CHAN_POWER(0),
0566 };
0567 
0568 static const struct iio_chan_spec admv1014_channels_if[] = {
0569     ADMV1014_CHAN_IF(0, I),
0570     ADMV1014_CHAN_IF(0, Q),
0571     ADMV1014_CHAN_CALIBSCALE(0, I, admv1014_ext_info),
0572     ADMV1014_CHAN_CALIBSCALE(0, Q, admv1014_ext_info),
0573     ADMV1014_CHAN_POWER(0),
0574 };
0575 
0576 static void admv1014_clk_disable(void *data)
0577 {
0578     clk_disable_unprepare(data);
0579 }
0580 
0581 static void admv1014_reg_disable(void *data)
0582 {
0583     regulator_bulk_disable(ADMV1014_NUM_REGULATORS, data);
0584 }
0585 
0586 static void admv1014_powerdown(void *data)
0587 {
0588     unsigned int enable_reg, enable_reg_msk;
0589 
0590     /* Disable all components in the Enable Register */
0591     enable_reg_msk = ADMV1014_IBIAS_PD_MSK |
0592             ADMV1014_IF_AMP_PD_MSK |
0593             ADMV1014_QUAD_BG_PD_MSK |
0594             ADMV1014_BB_AMP_PD_MSK |
0595             ADMV1014_QUAD_IBIAS_PD_MSK |
0596             ADMV1014_BG_PD_MSK;
0597 
0598     enable_reg = FIELD_PREP(ADMV1014_IBIAS_PD_MSK, 1) |
0599             FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, 1) |
0600             FIELD_PREP(ADMV1014_QUAD_BG_PD_MSK, 1) |
0601             FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, 1) |
0602             FIELD_PREP(ADMV1014_QUAD_IBIAS_PD_MSK, 1) |
0603             FIELD_PREP(ADMV1014_BG_PD_MSK, 1);
0604 
0605     admv1014_spi_update_bits(data, ADMV1014_REG_ENABLE,
0606                  enable_reg_msk, enable_reg);
0607 }
0608 
0609 static int admv1014_init(struct admv1014_state *st)
0610 {
0611     unsigned int chip_id, enable_reg, enable_reg_msk;
0612     struct spi_device *spi = st->spi;
0613     int ret;
0614 
0615     ret = regulator_bulk_enable(ADMV1014_NUM_REGULATORS, st->regulators);
0616     if (ret) {
0617         dev_err(&spi->dev, "Failed to enable regulators");
0618         return ret;
0619     }
0620 
0621     ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->regulators);
0622     if (ret)
0623         return ret;
0624 
0625     ret = clk_prepare_enable(st->clkin);
0626     if (ret)
0627         return ret;
0628 
0629     ret = devm_add_action_or_reset(&spi->dev, admv1014_clk_disable, st->clkin);
0630     if (ret)
0631         return ret;
0632 
0633     st->nb.notifier_call = admv1014_freq_change;
0634     ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);
0635     if (ret)
0636         return ret;
0637 
0638     ret = devm_add_action_or_reset(&spi->dev, admv1014_powerdown, st);
0639     if (ret)
0640         return ret;
0641 
0642     /* Perform a software reset */
0643     ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL,
0644                      ADMV1014_SPI_SOFT_RESET_MSK,
0645                      FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1));
0646     if (ret) {
0647         dev_err(&spi->dev, "ADMV1014 SPI software reset failed.\n");
0648         return ret;
0649     }
0650 
0651     ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL,
0652                      ADMV1014_SPI_SOFT_RESET_MSK,
0653                      FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0));
0654     if (ret) {
0655         dev_err(&spi->dev, "ADMV1014 SPI software reset disable failed.\n");
0656         return ret;
0657     }
0658 
0659     ret = __admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C);
0660     if (ret) {
0661         dev_err(&spi->dev, "Writing default Temperature Compensation value failed.\n");
0662         return ret;
0663     }
0664 
0665     ret = __admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id);
0666     if (ret)
0667         return ret;
0668 
0669     chip_id = FIELD_GET(ADMV1014_CHIP_ID_MSK, chip_id);
0670     if (chip_id != ADMV1014_CHIP_ID) {
0671         dev_err(&spi->dev, "Invalid Chip ID.\n");
0672         ret = -EINVAL;
0673         return ret;
0674     }
0675 
0676     ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD,
0677                      ADMV1014_QUAD_SE_MODE_MSK,
0678                      FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK,
0679                             st->quad_se_mode));
0680     if (ret) {
0681         dev_err(&spi->dev, "Writing Quad SE Mode failed.\n");
0682         return ret;
0683     }
0684 
0685     ret = admv1014_update_quad_filters(st);
0686     if (ret) {
0687         dev_err(&spi->dev, "Update Quad Filters failed.\n");
0688         return ret;
0689     }
0690 
0691     ret = admv1014_update_vcm_settings(st);
0692     if (ret) {
0693         dev_err(&spi->dev, "Update VCM Settings failed.\n");
0694         return ret;
0695     }
0696 
0697     enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK |
0698              ADMV1014_IF_AMP_PD_MSK |
0699              ADMV1014_BB_AMP_PD_MSK |
0700              ADMV1014_DET_EN_MSK;
0701 
0702     enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp ? 3 : 0) |
0703              FIELD_PREP(ADMV1014_IF_AMP_PD_MSK,
0704                 (st->input_mode == ADMV1014_IF_MODE) ? 0 : 1) |
0705              FIELD_PREP(ADMV1014_BB_AMP_PD_MSK,
0706                 (st->input_mode == ADMV1014_IF_MODE) ? 1 : 0) |
0707              FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en);
0708 
0709     return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg);
0710 }
0711 
0712 static int admv1014_properties_parse(struct admv1014_state *st)
0713 {
0714     const char *str;
0715     unsigned int i;
0716     struct spi_device *spi = st->spi;
0717     int ret;
0718 
0719     st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable");
0720 
0721     st->p1db_comp = device_property_read_bool(&spi->dev, "adi,p1db-compensation-enable");
0722 
0723     ret = device_property_read_string(&spi->dev, "adi,input-mode", &str);
0724     if (ret) {
0725         st->input_mode = ADMV1014_IQ_MODE;
0726     } else {
0727         ret = match_string(input_mode_names, ARRAY_SIZE(input_mode_names), str);
0728         if (ret < 0)
0729             return ret;
0730 
0731         st->input_mode = ret;
0732     }
0733 
0734     ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str);
0735     if (ret) {
0736         st->quad_se_mode = ADMV1014_SE_MODE_POS;
0737     } else {
0738         ret = match_string(quad_se_mode_names, ARRAY_SIZE(quad_se_mode_names), str);
0739         if (ret < 0)
0740             return ret;
0741 
0742         st->quad_se_mode = ADMV1014_SE_MODE_POS + (ret * 3);
0743     }
0744 
0745     for (i = 0; i < ADMV1014_NUM_REGULATORS; ++i)
0746         st->regulators[i].supply = admv1014_reg_name[i];
0747 
0748     ret = devm_regulator_bulk_get(&st->spi->dev, ADMV1014_NUM_REGULATORS,
0749                       st->regulators);
0750     if (ret) {
0751         dev_err(&spi->dev, "Failed to request regulators");
0752         return ret;
0753     }
0754 
0755     st->clkin = devm_clk_get(&spi->dev, "lo_in");
0756     if (IS_ERR(st->clkin))
0757         return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
0758                      "failed to get the LO input clock\n");
0759 
0760     return 0;
0761 }
0762 
0763 static int admv1014_probe(struct spi_device *spi)
0764 {
0765     struct iio_dev *indio_dev;
0766     struct admv1014_state *st;
0767     int ret;
0768 
0769     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0770     if (!indio_dev)
0771         return -ENOMEM;
0772 
0773     st = iio_priv(indio_dev);
0774 
0775     ret = admv1014_properties_parse(st);
0776     if (ret)
0777         return ret;
0778 
0779     indio_dev->info = &admv1014_info;
0780     indio_dev->name = "admv1014";
0781 
0782     if (st->input_mode == ADMV1014_IQ_MODE) {
0783         indio_dev->channels = admv1014_channels_iq;
0784         indio_dev->num_channels = ARRAY_SIZE(admv1014_channels_iq);
0785     } else {
0786         indio_dev->channels = admv1014_channels_if;
0787         indio_dev->num_channels = ARRAY_SIZE(admv1014_channels_if);
0788     }
0789 
0790     st->spi = spi;
0791 
0792     mutex_init(&st->lock);
0793 
0794     ret = admv1014_init(st);
0795     if (ret)
0796         return ret;
0797 
0798     return devm_iio_device_register(&spi->dev, indio_dev);
0799 }
0800 
0801 static const struct spi_device_id admv1014_id[] = {
0802     { "admv1014", 0 },
0803     {}
0804 };
0805 MODULE_DEVICE_TABLE(spi, admv1014_id);
0806 
0807 static const struct of_device_id admv1014_of_match[] = {
0808     { .compatible = "adi,admv1014" },
0809     {}
0810 };
0811 MODULE_DEVICE_TABLE(of, admv1014_of_match);
0812 
0813 static struct spi_driver admv1014_driver = {
0814     .driver = {
0815         .name = "admv1014",
0816         .of_match_table = admv1014_of_match,
0817     },
0818     .probe = admv1014_probe,
0819     .id_table = admv1014_id,
0820 };
0821 module_spi_driver(admv1014_driver);
0822 
0823 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
0824 MODULE_DESCRIPTION("Analog Devices ADMV1014");
0825 MODULE_LICENSE("GPL v2");
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