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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADMV1013 driver
0004  *
0005  * Copyright 2021 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/device.h>
0012 #include <linux/iio/iio.h>
0013 #include <linux/module.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/notifier.h>
0016 #include <linux/property.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/units.h>
0020 
0021 #include <asm/unaligned.h>
0022 
0023 /* ADMV1013 Register Map */
0024 #define ADMV1013_REG_SPI_CONTROL        0x00
0025 #define ADMV1013_REG_ALARM          0x01
0026 #define ADMV1013_REG_ALARM_MASKS        0x02
0027 #define ADMV1013_REG_ENABLE         0x03
0028 #define ADMV1013_REG_LO_AMP_I           0x05
0029 #define ADMV1013_REG_LO_AMP_Q           0x06
0030 #define ADMV1013_REG_OFFSET_ADJUST_I        0x07
0031 #define ADMV1013_REG_OFFSET_ADJUST_Q        0x08
0032 #define ADMV1013_REG_QUAD           0x09
0033 #define ADMV1013_REG_VVA_TEMP_COMP      0x0A
0034 
0035 /* ADMV1013_REG_SPI_CONTROL Map */
0036 #define ADMV1013_PARITY_EN_MSK          BIT(15)
0037 #define ADMV1013_SPI_SOFT_RESET_MSK     BIT(14)
0038 #define ADMV1013_CHIP_ID_MSK            GENMASK(11, 4)
0039 #define ADMV1013_CHIP_ID            0xA
0040 #define ADMV1013_REVISION_ID_MSK        GENMASK(3, 0)
0041 
0042 /* ADMV1013_REG_ALARM Map */
0043 #define ADMV1013_PARITY_ERROR_MSK       BIT(15)
0044 #define ADMV1013_TOO_FEW_ERRORS_MSK     BIT(14)
0045 #define ADMV1013_TOO_MANY_ERRORS_MSK        BIT(13)
0046 #define ADMV1013_ADDRESS_RANGE_ERROR_MSK    BIT(12)
0047 
0048 /* ADMV1013_REG_ENABLE Map */
0049 #define ADMV1013_VGA_PD_MSK         BIT(15)
0050 #define ADMV1013_MIXER_PD_MSK           BIT(14)
0051 #define ADMV1013_QUAD_PD_MSK            GENMASK(13, 11)
0052 #define ADMV1013_BG_PD_MSK          BIT(10)
0053 #define ADMV1013_MIXER_IF_EN_MSK        BIT(7)
0054 #define ADMV1013_DET_EN_MSK         BIT(5)
0055 
0056 /* ADMV1013_REG_LO_AMP Map */
0057 #define ADMV1013_LOAMP_PH_ADJ_FINE_MSK      GENMASK(13, 7)
0058 #define ADMV1013_MIXER_VGATE_MSK        GENMASK(6, 0)
0059 
0060 /* ADMV1013_REG_OFFSET_ADJUST Map */
0061 #define ADMV1013_MIXER_OFF_ADJ_P_MSK        GENMASK(15, 9)
0062 #define ADMV1013_MIXER_OFF_ADJ_N_MSK        GENMASK(8, 2)
0063 
0064 /* ADMV1013_REG_QUAD Map */
0065 #define ADMV1013_QUAD_SE_MODE_MSK       GENMASK(9, 6)
0066 #define ADMV1013_QUAD_FILTERS_MSK       GENMASK(3, 0)
0067 
0068 /* ADMV1013_REG_VVA_TEMP_COMP Map */
0069 #define ADMV1013_VVA_TEMP_COMP_MSK      GENMASK(15, 0)
0070 
0071 /* ADMV1013 Miscellaneous Defines */
0072 #define ADMV1013_READ               BIT(7)
0073 #define ADMV1013_REG_ADDR_READ_MSK      GENMASK(6, 1)
0074 #define ADMV1013_REG_ADDR_WRITE_MSK     GENMASK(22, 17)
0075 #define ADMV1013_REG_DATA_MSK           GENMASK(16, 1)
0076 
0077 enum {
0078     ADMV1013_IQ_MODE,
0079     ADMV1013_IF_MODE
0080 };
0081 
0082 enum {
0083     ADMV1013_RFMOD_I_CALIBPHASE,
0084     ADMV1013_RFMOD_Q_CALIBPHASE,
0085 };
0086 
0087 enum {
0088     ADMV1013_SE_MODE_POS = 6,
0089     ADMV1013_SE_MODE_NEG = 9,
0090     ADMV1013_SE_MODE_DIFF = 12
0091 };
0092 
0093 struct admv1013_state {
0094     struct spi_device   *spi;
0095     struct clk      *clkin;
0096     /* Protect against concurrent accesses to the device and to data */
0097     struct mutex        lock;
0098     struct regulator    *reg;
0099     struct notifier_block   nb;
0100     unsigned int        input_mode;
0101     unsigned int        quad_se_mode;
0102     bool            det_en;
0103     u8          data[3] __aligned(IIO_DMA_MINALIGN);
0104 };
0105 
0106 static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
0107                    unsigned int *val)
0108 {
0109     int ret;
0110     struct spi_transfer t = {0};
0111 
0112     st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg);
0113     st->data[1] = 0x0;
0114     st->data[2] = 0x0;
0115 
0116     t.rx_buf = &st->data[0];
0117     t.tx_buf = &st->data[0];
0118     t.len = 3;
0119 
0120     ret = spi_sync_transfer(st->spi, &t, 1);
0121     if (ret)
0122         return ret;
0123 
0124     *val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0]));
0125 
0126     return ret;
0127 }
0128 
0129 static int admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
0130                  unsigned int *val)
0131 {
0132     int ret;
0133 
0134     mutex_lock(&st->lock);
0135     ret = __admv1013_spi_read(st, reg, val);
0136     mutex_unlock(&st->lock);
0137 
0138     return ret;
0139 }
0140 
0141 static int __admv1013_spi_write(struct admv1013_state *st,
0142                 unsigned int reg,
0143                 unsigned int val)
0144 {
0145     put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) |
0146                FIELD_PREP(ADMV1013_REG_ADDR_WRITE_MSK, reg), &st->data[0]);
0147 
0148     return spi_write(st->spi, &st->data[0], 3);
0149 }
0150 
0151 static int admv1013_spi_write(struct admv1013_state *st, unsigned int reg,
0152                   unsigned int val)
0153 {
0154     int ret;
0155 
0156     mutex_lock(&st->lock);
0157     ret = __admv1013_spi_write(st, reg, val);
0158     mutex_unlock(&st->lock);
0159 
0160     return ret;
0161 }
0162 
0163 static int __admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
0164                       unsigned int mask, unsigned int val)
0165 {
0166     int ret;
0167     unsigned int data, temp;
0168 
0169     ret = __admv1013_spi_read(st, reg, &data);
0170     if (ret)
0171         return ret;
0172 
0173     temp = (data & ~mask) | (val & mask);
0174 
0175     return __admv1013_spi_write(st, reg, temp);
0176 }
0177 
0178 static int admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
0179                     unsigned int mask, unsigned int val)
0180 {
0181     int ret;
0182 
0183     mutex_lock(&st->lock);
0184     ret = __admv1013_spi_update_bits(st, reg, mask, val);
0185     mutex_unlock(&st->lock);
0186 
0187     return ret;
0188 }
0189 
0190 static int admv1013_read_raw(struct iio_dev *indio_dev,
0191                  struct iio_chan_spec const *chan,
0192                  int *val, int *val2, long info)
0193 {
0194     struct admv1013_state *st = iio_priv(indio_dev);
0195     unsigned int data, addr;
0196     int ret;
0197 
0198     switch (info) {
0199     case IIO_CHAN_INFO_CALIBBIAS:
0200         switch (chan->channel) {
0201         case IIO_MOD_I:
0202             addr = ADMV1013_REG_OFFSET_ADJUST_I;
0203             break;
0204         case IIO_MOD_Q:
0205             addr = ADMV1013_REG_OFFSET_ADJUST_Q;
0206             break;
0207         default:
0208             return -EINVAL;
0209         }
0210 
0211         ret = admv1013_spi_read(st, addr, &data);
0212         if (ret)
0213             return ret;
0214 
0215         if (!chan->channel)
0216             *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_P_MSK, data);
0217         else
0218             *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_N_MSK, data);
0219 
0220         return IIO_VAL_INT;
0221     default:
0222         return -EINVAL;
0223     }
0224 }
0225 
0226 static int admv1013_write_raw(struct iio_dev *indio_dev,
0227                   struct iio_chan_spec const *chan,
0228                   int val, int val2, long info)
0229 {
0230     struct admv1013_state *st = iio_priv(indio_dev);
0231     unsigned int addr, data, msk;
0232 
0233     switch (info) {
0234     case IIO_CHAN_INFO_CALIBBIAS:
0235         switch (chan->channel2) {
0236         case IIO_MOD_I:
0237             addr = ADMV1013_REG_OFFSET_ADJUST_I;
0238             break;
0239         case IIO_MOD_Q:
0240             addr = ADMV1013_REG_OFFSET_ADJUST_Q;
0241             break;
0242         default:
0243             return -EINVAL;
0244         }
0245 
0246         if (!chan->channel) {
0247             msk = ADMV1013_MIXER_OFF_ADJ_P_MSK;
0248             data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_P_MSK, val);
0249         } else {
0250             msk = ADMV1013_MIXER_OFF_ADJ_N_MSK;
0251             data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_N_MSK, val);
0252         }
0253 
0254         return admv1013_spi_update_bits(st, addr, msk, data);
0255     default:
0256         return -EINVAL;
0257     }
0258 }
0259 
0260 static ssize_t admv1013_read(struct iio_dev *indio_dev,
0261                  uintptr_t private,
0262                  const struct iio_chan_spec *chan,
0263                  char *buf)
0264 {
0265     struct admv1013_state *st = iio_priv(indio_dev);
0266     unsigned int data, addr;
0267     int ret;
0268 
0269     switch ((u32)private) {
0270     case ADMV1013_RFMOD_I_CALIBPHASE:
0271         addr = ADMV1013_REG_LO_AMP_I;
0272         break;
0273     case ADMV1013_RFMOD_Q_CALIBPHASE:
0274         addr = ADMV1013_REG_LO_AMP_Q;
0275         break;
0276     default:
0277         return -EINVAL;
0278     }
0279 
0280     ret = admv1013_spi_read(st, addr, &data);
0281     if (ret)
0282         return ret;
0283 
0284     data = FIELD_GET(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);
0285 
0286     return sysfs_emit(buf, "%u\n", data);
0287 }
0288 
0289 static ssize_t admv1013_write(struct iio_dev *indio_dev,
0290                   uintptr_t private,
0291                   const struct iio_chan_spec *chan,
0292                   const char *buf, size_t len)
0293 {
0294     struct admv1013_state *st = iio_priv(indio_dev);
0295     unsigned int data;
0296     int ret;
0297 
0298     ret = kstrtou32(buf, 10, &data);
0299     if (ret)
0300         return ret;
0301 
0302     data = FIELD_PREP(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);
0303 
0304     switch ((u32)private) {
0305     case ADMV1013_RFMOD_I_CALIBPHASE:
0306         ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
0307                            ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
0308                            data);
0309         if (ret)
0310             return ret;
0311         break;
0312     case ADMV1013_RFMOD_Q_CALIBPHASE:
0313         ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_Q,
0314                            ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
0315                            data);
0316         if (ret)
0317             return ret;
0318         break;
0319     default:
0320         return -EINVAL;
0321     }
0322 
0323     return ret ? ret : len;
0324 }
0325 
0326 static int admv1013_update_quad_filters(struct admv1013_state *st)
0327 {
0328     unsigned int filt_raw;
0329     u64 rate = clk_get_rate(st->clkin);
0330 
0331     if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ))
0332         filt_raw = 15;
0333     else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ))
0334         filt_raw = 10;
0335     else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ))
0336         filt_raw = 5;
0337     else
0338         filt_raw = 0;
0339 
0340     return __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
0341                     ADMV1013_QUAD_FILTERS_MSK,
0342                     FIELD_PREP(ADMV1013_QUAD_FILTERS_MSK, filt_raw));
0343 }
0344 
0345 static int admv1013_update_mixer_vgate(struct admv1013_state *st)
0346 {
0347     unsigned int vcm, mixer_vgate;
0348 
0349     vcm = regulator_get_voltage(st->reg);
0350 
0351     if (vcm < 1800000)
0352         mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;
0353     else if (vcm > 1800000 && vcm < 2600000)
0354         mixer_vgate = (2375 * vcm / 1000000 + 125) / 100;
0355     else
0356         return -EINVAL;
0357 
0358     return __admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
0359                  ADMV1013_MIXER_VGATE_MSK,
0360                  FIELD_PREP(ADMV1013_MIXER_VGATE_MSK, mixer_vgate));
0361 }
0362 
0363 static int admv1013_reg_access(struct iio_dev *indio_dev,
0364                    unsigned int reg,
0365                    unsigned int write_val,
0366                    unsigned int *read_val)
0367 {
0368     struct admv1013_state *st = iio_priv(indio_dev);
0369 
0370     if (read_val)
0371         return admv1013_spi_read(st, reg, read_val);
0372     else
0373         return admv1013_spi_write(st, reg, write_val);
0374 }
0375 
0376 static const struct iio_info admv1013_info = {
0377     .read_raw = admv1013_read_raw,
0378     .write_raw = admv1013_write_raw,
0379     .debugfs_reg_access = &admv1013_reg_access,
0380 };
0381 
0382 static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data)
0383 {
0384     struct admv1013_state *st = container_of(nb, struct admv1013_state, nb);
0385     int ret;
0386 
0387     if (action == POST_RATE_CHANGE) {
0388         mutex_lock(&st->lock);
0389         ret = notifier_from_errno(admv1013_update_quad_filters(st));
0390         mutex_unlock(&st->lock);
0391         return ret;
0392     }
0393 
0394     return NOTIFY_OK;
0395 }
0396 
0397 #define _ADMV1013_EXT_INFO(_name, _shared, _ident) { \
0398         .name = _name, \
0399         .read = admv1013_read, \
0400         .write = admv1013_write, \
0401         .private = _ident, \
0402         .shared = _shared, \
0403 }
0404 
0405 static const struct iio_chan_spec_ext_info admv1013_ext_info[] = {
0406     _ADMV1013_EXT_INFO("i_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_I_CALIBPHASE),
0407     _ADMV1013_EXT_INFO("q_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_Q_CALIBPHASE),
0408     { },
0409 };
0410 
0411 #define ADMV1013_CHAN_PHASE(_channel, _channel2, _admv1013_ext_info) {      \
0412     .type = IIO_ALTVOLTAGE,                 \
0413     .output = 0,                        \
0414     .indexed = 1,                       \
0415     .channel2 = _channel2,                  \
0416     .channel = _channel,                    \
0417     .differential = 1,                  \
0418     .ext_info = _admv1013_ext_info,             \
0419     }
0420 
0421 #define ADMV1013_CHAN_CALIB(_channel, rf_comp) {    \
0422     .type = IIO_ALTVOLTAGE,                 \
0423     .output = 0,                        \
0424     .indexed = 1,                       \
0425     .channel = _channel,                    \
0426     .channel2 = IIO_MOD_##rf_comp,              \
0427     .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS), \
0428     }
0429 
0430 static const struct iio_chan_spec admv1013_channels[] = {
0431     ADMV1013_CHAN_PHASE(0, 1, admv1013_ext_info),
0432     ADMV1013_CHAN_CALIB(0, I),
0433     ADMV1013_CHAN_CALIB(0, Q),
0434     ADMV1013_CHAN_CALIB(1, I),
0435     ADMV1013_CHAN_CALIB(1, Q),
0436 };
0437 
0438 static int admv1013_init(struct admv1013_state *st)
0439 {
0440     int ret;
0441     unsigned int data;
0442     struct spi_device *spi = st->spi;
0443 
0444     /* Perform a software reset */
0445     ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
0446                      ADMV1013_SPI_SOFT_RESET_MSK,
0447                      FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 1));
0448     if (ret)
0449         return ret;
0450 
0451     ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
0452                      ADMV1013_SPI_SOFT_RESET_MSK,
0453                      FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 0));
0454     if (ret)
0455         return ret;
0456 
0457     ret = __admv1013_spi_read(st, ADMV1013_REG_SPI_CONTROL, &data);
0458     if (ret)
0459         return ret;
0460 
0461     data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data);
0462     if (data != ADMV1013_CHIP_ID) {
0463         dev_err(&spi->dev, "Invalid Chip ID.\n");
0464         return -EINVAL;
0465     }
0466 
0467     ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700);
0468     if (ret)
0469         return ret;
0470 
0471     data = FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, st->quad_se_mode);
0472 
0473     ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
0474                      ADMV1013_QUAD_SE_MODE_MSK, data);
0475     if (ret)
0476         return ret;
0477 
0478     ret = admv1013_update_mixer_vgate(st);
0479     if (ret)
0480         return ret;
0481 
0482     ret = admv1013_update_quad_filters(st);
0483     if (ret)
0484         return ret;
0485 
0486     return __admv1013_spi_update_bits(st, ADMV1013_REG_ENABLE,
0487                       ADMV1013_DET_EN_MSK |
0488                       ADMV1013_MIXER_IF_EN_MSK,
0489                       st->det_en |
0490                       st->input_mode);
0491 }
0492 
0493 static void admv1013_clk_disable(void *data)
0494 {
0495     clk_disable_unprepare(data);
0496 }
0497 
0498 static void admv1013_reg_disable(void *data)
0499 {
0500     regulator_disable(data);
0501 }
0502 
0503 static void admv1013_powerdown(void *data)
0504 {
0505     unsigned int enable_reg, enable_reg_msk;
0506 
0507     /* Disable all components in the Enable Register */
0508     enable_reg_msk = ADMV1013_VGA_PD_MSK |
0509             ADMV1013_MIXER_PD_MSK |
0510             ADMV1013_QUAD_PD_MSK |
0511             ADMV1013_BG_PD_MSK |
0512             ADMV1013_MIXER_IF_EN_MSK |
0513             ADMV1013_DET_EN_MSK;
0514 
0515     enable_reg = FIELD_PREP(ADMV1013_VGA_PD_MSK, 1) |
0516             FIELD_PREP(ADMV1013_MIXER_PD_MSK, 1) |
0517             FIELD_PREP(ADMV1013_QUAD_PD_MSK, 7) |
0518             FIELD_PREP(ADMV1013_BG_PD_MSK, 1) |
0519             FIELD_PREP(ADMV1013_MIXER_IF_EN_MSK, 0) |
0520             FIELD_PREP(ADMV1013_DET_EN_MSK, 0);
0521 
0522     admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg);
0523 }
0524 
0525 static int admv1013_properties_parse(struct admv1013_state *st)
0526 {
0527     int ret;
0528     const char *str;
0529     struct spi_device *spi = st->spi;
0530 
0531     st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable");
0532 
0533     ret = device_property_read_string(&spi->dev, "adi,input-mode", &str);
0534     if (ret)
0535         st->input_mode = ADMV1013_IQ_MODE;
0536 
0537     if (!strcmp(str, "iq"))
0538         st->input_mode = ADMV1013_IQ_MODE;
0539     else if (!strcmp(str, "if"))
0540         st->input_mode = ADMV1013_IF_MODE;
0541     else
0542         return -EINVAL;
0543 
0544     ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str);
0545     if (ret)
0546         st->quad_se_mode = ADMV1013_SE_MODE_DIFF;
0547 
0548     if (!strcmp(str, "diff"))
0549         st->quad_se_mode = ADMV1013_SE_MODE_DIFF;
0550     else if (!strcmp(str, "se-pos"))
0551         st->quad_se_mode = ADMV1013_SE_MODE_POS;
0552     else if (!strcmp(str, "se-neg"))
0553         st->quad_se_mode = ADMV1013_SE_MODE_NEG;
0554     else
0555         return -EINVAL;
0556 
0557     st->reg = devm_regulator_get(&spi->dev, "vcm");
0558     if (IS_ERR(st->reg))
0559         return dev_err_probe(&spi->dev, PTR_ERR(st->reg),
0560                      "failed to get the common-mode voltage\n");
0561 
0562     st->clkin = devm_clk_get(&spi->dev, "lo_in");
0563     if (IS_ERR(st->clkin))
0564         return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
0565                      "failed to get the LO input clock\n");
0566 
0567     return 0;
0568 }
0569 
0570 static int admv1013_probe(struct spi_device *spi)
0571 {
0572     struct iio_dev *indio_dev;
0573     struct admv1013_state *st;
0574     int ret;
0575 
0576     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0577     if (!indio_dev)
0578         return -ENOMEM;
0579 
0580     st = iio_priv(indio_dev);
0581 
0582     indio_dev->info = &admv1013_info;
0583     indio_dev->name = "admv1013";
0584     indio_dev->channels = admv1013_channels;
0585     indio_dev->num_channels = ARRAY_SIZE(admv1013_channels);
0586 
0587     st->spi = spi;
0588 
0589     ret = admv1013_properties_parse(st);
0590     if (ret)
0591         return ret;
0592 
0593     ret = regulator_enable(st->reg);
0594     if (ret) {
0595         dev_err(&spi->dev, "Failed to enable specified Common-Mode Voltage!\n");
0596         return ret;
0597     }
0598 
0599     ret = devm_add_action_or_reset(&spi->dev, admv1013_reg_disable,
0600                        st->reg);
0601     if (ret)
0602         return ret;
0603 
0604     ret = clk_prepare_enable(st->clkin);
0605     if (ret)
0606         return ret;
0607 
0608     ret = devm_add_action_or_reset(&spi->dev, admv1013_clk_disable, st->clkin);
0609     if (ret)
0610         return ret;
0611 
0612     st->nb.notifier_call = admv1013_freq_change;
0613     ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);
0614     if (ret)
0615         return ret;
0616 
0617     mutex_init(&st->lock);
0618 
0619     ret = admv1013_init(st);
0620     if (ret) {
0621         dev_err(&spi->dev, "admv1013 init failed\n");
0622         return ret;
0623     }
0624 
0625     ret = devm_add_action_or_reset(&spi->dev, admv1013_powerdown, st);
0626     if (ret)
0627         return ret;
0628 
0629     return devm_iio_device_register(&spi->dev, indio_dev);
0630 }
0631 
0632 static const struct spi_device_id admv1013_id[] = {
0633     { "admv1013", 0 },
0634     {}
0635 };
0636 MODULE_DEVICE_TABLE(spi, admv1013_id);
0637 
0638 static const struct of_device_id admv1013_of_match[] = {
0639     { .compatible = "adi,admv1013" },
0640     {},
0641 };
0642 MODULE_DEVICE_TABLE(of, admv1013_of_match);
0643 
0644 static struct spi_driver admv1013_driver = {
0645     .driver = {
0646         .name = "admv1013",
0647         .of_match_table = admv1013_of_match,
0648     },
0649     .probe = admv1013_probe,
0650     .id_table = admv1013_id,
0651 };
0652 module_spi_driver(admv1013_driver);
0653 
0654 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
0655 MODULE_DESCRIPTION("Analog Devices ADMV1013");
0656 MODULE_LICENSE("GPL v2");
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