Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Analog Devices ADF4371 SPI Wideband Synthesizer driver
0004  *
0005  * Copyright 2019 Analog Devices Inc.
0006  */
0007 #include <linux/bitfield.h>
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/err.h>
0011 #include <linux/gcd.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/regmap.h>
0015 #include <linux/sysfs.h>
0016 #include <linux/spi/spi.h>
0017 
0018 #include <linux/iio/iio.h>
0019 
0020 /* Registers address macro */
0021 #define ADF4371_REG(x)          (x)
0022 
0023 /* ADF4371_REG0 */
0024 #define ADF4371_ADDR_ASC_MSK        BIT(2)
0025 #define ADF4371_ADDR_ASC(x)     FIELD_PREP(ADF4371_ADDR_ASC_MSK, x)
0026 #define ADF4371_ADDR_ASC_R_MSK      BIT(5)
0027 #define ADF4371_ADDR_ASC_R(x)       FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x)
0028 #define ADF4371_RESET_CMD       0x81
0029 
0030 /* ADF4371_REG17 */
0031 #define ADF4371_FRAC2WORD_L_MSK     GENMASK(7, 1)
0032 #define ADF4371_FRAC2WORD_L(x)      FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x)
0033 #define ADF4371_FRAC1WORD_MSK       BIT(0)
0034 #define ADF4371_FRAC1WORD(x)        FIELD_PREP(ADF4371_FRAC1WORD_MSK, x)
0035 
0036 /* ADF4371_REG18 */
0037 #define ADF4371_FRAC2WORD_H_MSK     GENMASK(6, 0)
0038 #define ADF4371_FRAC2WORD_H(x)      FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x)
0039 
0040 /* ADF4371_REG1A */
0041 #define ADF4371_MOD2WORD_MSK        GENMASK(5, 0)
0042 #define ADF4371_MOD2WORD(x)     FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
0043 
0044 /* ADF4371_REG24 */
0045 #define ADF4371_RF_DIV_SEL_MSK      GENMASK(6, 4)
0046 #define ADF4371_RF_DIV_SEL(x)       FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
0047 
0048 /* ADF4371_REG25 */
0049 #define ADF4371_MUTE_LD_MSK     BIT(7)
0050 #define ADF4371_MUTE_LD(x)      FIELD_PREP(ADF4371_MUTE_LD_MSK, x)
0051 
0052 /* ADF4371_REG32 */
0053 #define ADF4371_TIMEOUT_MSK     GENMASK(1, 0)
0054 #define ADF4371_TIMEOUT(x)      FIELD_PREP(ADF4371_TIMEOUT_MSK, x)
0055 
0056 /* ADF4371_REG34 */
0057 #define ADF4371_VCO_ALC_TOUT_MSK    GENMASK(4, 0)
0058 #define ADF4371_VCO_ALC_TOUT(x)     FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x)
0059 
0060 /* Specifications */
0061 #define ADF4371_MIN_VCO_FREQ        4000000000ULL /* 4000 MHz */
0062 #define ADF4371_MAX_VCO_FREQ        8000000000ULL /* 8000 MHz */
0063 #define ADF4371_MAX_OUT_RF8_FREQ    ADF4371_MAX_VCO_FREQ /* Hz */
0064 #define ADF4371_MIN_OUT_RF8_FREQ    (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
0065 #define ADF4371_MAX_OUT_RF16_FREQ   (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
0066 #define ADF4371_MIN_OUT_RF16_FREQ   (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
0067 #define ADF4371_MAX_OUT_RF32_FREQ   (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
0068 #define ADF4371_MIN_OUT_RF32_FREQ   (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
0069 
0070 #define ADF4371_MAX_FREQ_PFD        250000000UL /* Hz */
0071 #define ADF4371_MAX_FREQ_REFIN      600000000UL /* Hz */
0072 
0073 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
0074 #define ADF4371_MODULUS1        33554432ULL
0075 /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
0076 #define ADF4371_MAX_MODULUS2        BIT(14)
0077 
0078 #define ADF4371_CHECK_RANGE(freq, range) \
0079     ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range))
0080 
0081 enum {
0082     ADF4371_FREQ,
0083     ADF4371_POWER_DOWN,
0084     ADF4371_CHANNEL_NAME
0085 };
0086 
0087 enum {
0088     ADF4371_CH_RF8,
0089     ADF4371_CH_RFAUX8,
0090     ADF4371_CH_RF16,
0091     ADF4371_CH_RF32
0092 };
0093 
0094 enum adf4371_variant {
0095     ADF4371,
0096     ADF4372
0097 };
0098 
0099 struct adf4371_pwrdown {
0100     unsigned int reg;
0101     unsigned int bit;
0102 };
0103 
0104 static const char * const adf4371_ch_names[] = {
0105     "RF8x", "RFAUX8x", "RF16x", "RF32x"
0106 };
0107 
0108 static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = {
0109     [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 },
0110     [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 },
0111     [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 },
0112     [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 },
0113 };
0114 
0115 static const struct reg_sequence adf4371_reg_defaults[] = {
0116     { ADF4371_REG(0x0),  0x18 },
0117     { ADF4371_REG(0x12), 0x40 },
0118     { ADF4371_REG(0x1E), 0x48 },
0119     { ADF4371_REG(0x20), 0x14 },
0120     { ADF4371_REG(0x22), 0x00 },
0121     { ADF4371_REG(0x23), 0x00 },
0122     { ADF4371_REG(0x24), 0x80 },
0123     { ADF4371_REG(0x25), 0x07 },
0124     { ADF4371_REG(0x27), 0xC5 },
0125     { ADF4371_REG(0x28), 0x83 },
0126     { ADF4371_REG(0x2C), 0x44 },
0127     { ADF4371_REG(0x2D), 0x11 },
0128     { ADF4371_REG(0x2E), 0x12 },
0129     { ADF4371_REG(0x2F), 0x94 },
0130     { ADF4371_REG(0x32), 0x04 },
0131     { ADF4371_REG(0x35), 0xFA },
0132     { ADF4371_REG(0x36), 0x30 },
0133     { ADF4371_REG(0x39), 0x07 },
0134     { ADF4371_REG(0x3A), 0x55 },
0135     { ADF4371_REG(0x3E), 0x0C },
0136     { ADF4371_REG(0x3F), 0x80 },
0137     { ADF4371_REG(0x40), 0x50 },
0138     { ADF4371_REG(0x41), 0x28 },
0139     { ADF4371_REG(0x47), 0xC0 },
0140     { ADF4371_REG(0x52), 0xF4 },
0141     { ADF4371_REG(0x70), 0x03 },
0142     { ADF4371_REG(0x71), 0x60 },
0143     { ADF4371_REG(0x72), 0x32 },
0144 };
0145 
0146 static const struct regmap_config adf4371_regmap_config = {
0147     .reg_bits = 16,
0148     .val_bits = 8,
0149     .read_flag_mask = BIT(7),
0150 };
0151 
0152 struct adf4371_chip_info {
0153     unsigned int num_channels;
0154     const struct iio_chan_spec *channels;
0155 };
0156 
0157 struct adf4371_state {
0158     struct spi_device *spi;
0159     struct regmap *regmap;
0160     struct clk *clkin;
0161     /*
0162      * Lock for accessing device registers. Some operations require
0163      * multiple consecutive R/W operations, during which the device
0164      * shouldn't be interrupted. The buffers are also shared across
0165      * all operations so need to be protected on stand alone reads and
0166      * writes.
0167      */
0168     struct mutex lock;
0169     const struct adf4371_chip_info *chip_info;
0170     unsigned long clkin_freq;
0171     unsigned long fpfd;
0172     unsigned int integer;
0173     unsigned int fract1;
0174     unsigned int fract2;
0175     unsigned int mod2;
0176     unsigned int rf_div_sel;
0177     unsigned int ref_div_factor;
0178     u8 buf[10] __aligned(IIO_DMA_MINALIGN);
0179 };
0180 
0181 static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,
0182                                u32 channel)
0183 {
0184     unsigned long long val, tmp;
0185     unsigned int ref_div_sel;
0186 
0187     val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd;
0188     tmp = (u64)st->fract2 * st->fpfd;
0189     do_div(tmp, st->mod2);
0190     val += tmp + ADF4371_MODULUS1 / 2;
0191 
0192     if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8)
0193         ref_div_sel = st->rf_div_sel;
0194     else
0195         ref_div_sel = 0;
0196 
0197     do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel));
0198 
0199     if (channel == ADF4371_CH_RF16)
0200         val <<= 1;
0201     else if (channel == ADF4371_CH_RF32)
0202         val <<= 2;
0203 
0204     return val;
0205 }
0206 
0207 static void adf4371_pll_fract_n_compute(unsigned long long vco,
0208                        unsigned long long pfd,
0209                        unsigned int *integer,
0210                        unsigned int *fract1,
0211                        unsigned int *fract2,
0212                        unsigned int *mod2)
0213 {
0214     unsigned long long tmp;
0215     u32 gcd_div;
0216 
0217     tmp = do_div(vco, pfd);
0218     tmp = tmp * ADF4371_MODULUS1;
0219     *fract2 = do_div(tmp, pfd);
0220 
0221     *integer = vco;
0222     *fract1 = tmp;
0223 
0224     *mod2 = pfd;
0225 
0226     while (*mod2 > ADF4371_MAX_MODULUS2) {
0227         *mod2 >>= 1;
0228         *fract2 >>= 1;
0229     }
0230 
0231     gcd_div = gcd(*fract2, *mod2);
0232     *mod2 /= gcd_div;
0233     *fract2 /= gcd_div;
0234 }
0235 
0236 static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq,
0237                 unsigned int channel)
0238 {
0239     u32 cp_bleed;
0240     u8 int_mode = 0;
0241     int ret;
0242 
0243     switch (channel) {
0244     case ADF4371_CH_RF8:
0245     case ADF4371_CH_RFAUX8:
0246         if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ))
0247             return -EINVAL;
0248 
0249         st->rf_div_sel = 0;
0250 
0251         while (freq < ADF4371_MIN_VCO_FREQ) {
0252             freq <<= 1;
0253             st->rf_div_sel++;
0254         }
0255         break;
0256     case ADF4371_CH_RF16:
0257         /* ADF4371 RF16 8000...16000 MHz */
0258         if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ))
0259             return -EINVAL;
0260 
0261         freq >>= 1;
0262         break;
0263     case ADF4371_CH_RF32:
0264         /* ADF4371 RF32 16000...32000 MHz */
0265         if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ))
0266             return -EINVAL;
0267 
0268         freq >>= 2;
0269         break;
0270     default:
0271         return -EINVAL;
0272     }
0273 
0274     adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1,
0275                     &st->fract2, &st->mod2);
0276     st->buf[0] = st->integer >> 8;
0277     st->buf[1] = 0x40; /* REG12 default */
0278     st->buf[2] = 0x00;
0279     st->buf[3] = st->fract1 & 0xFF;
0280     st->buf[4] = st->fract1 >> 8;
0281     st->buf[5] = st->fract1 >> 16;
0282     st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) |
0283              ADF4371_FRAC1WORD(st->fract1 >> 24);
0284     st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7);
0285     st->buf[8] = st->mod2 & 0xFF;
0286     st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8);
0287 
0288     ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10);
0289     if (ret < 0)
0290         return ret;
0291     /*
0292      * The R counter allows the input reference frequency to be
0293      * divided down to produce the reference clock to the PFD
0294      */
0295     ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor);
0296     if (ret < 0)
0297         return ret;
0298 
0299     ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24),
0300                  ADF4371_RF_DIV_SEL_MSK,
0301                  ADF4371_RF_DIV_SEL(st->rf_div_sel));
0302     if (ret < 0)
0303         return ret;
0304 
0305     cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375);
0306     cp_bleed = clamp(cp_bleed, 1U, 255U);
0307     ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed);
0308     if (ret < 0)
0309         return ret;
0310     /*
0311      * Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0),
0312      * and set to 0 when in FRAC mode.
0313      */
0314     if (st->fract1 == 0 && st->fract2 == 0)
0315         int_mode = 0x01;
0316 
0317     ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode);
0318     if (ret < 0)
0319         return ret;
0320 
0321     return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF);
0322 }
0323 
0324 static ssize_t adf4371_read(struct iio_dev *indio_dev,
0325                 uintptr_t private,
0326                 const struct iio_chan_spec *chan,
0327                 char *buf)
0328 {
0329     struct adf4371_state *st = iio_priv(indio_dev);
0330     unsigned long long val = 0;
0331     unsigned int readval, reg, bit;
0332     int ret;
0333 
0334     switch ((u32)private) {
0335     case ADF4371_FREQ:
0336         val = adf4371_pll_fract_n_get_rate(st, chan->channel);
0337         ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval);
0338         if (ret < 0)
0339             break;
0340 
0341         if (readval == 0x00) {
0342             dev_dbg(&st->spi->dev, "PLL un-locked\n");
0343             ret = -EBUSY;
0344         }
0345         break;
0346     case ADF4371_POWER_DOWN:
0347         reg = adf4371_pwrdown_ch[chan->channel].reg;
0348         bit = adf4371_pwrdown_ch[chan->channel].bit;
0349 
0350         ret = regmap_read(st->regmap, reg, &readval);
0351         if (ret < 0)
0352             break;
0353 
0354         val = !(readval & BIT(bit));
0355         break;
0356     case ADF4371_CHANNEL_NAME:
0357         return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]);
0358     default:
0359         ret = -EINVAL;
0360         val = 0;
0361         break;
0362     }
0363 
0364     return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
0365 }
0366 
0367 static ssize_t adf4371_write(struct iio_dev *indio_dev,
0368                  uintptr_t private,
0369                  const struct iio_chan_spec *chan,
0370                  const char *buf, size_t len)
0371 {
0372     struct adf4371_state *st = iio_priv(indio_dev);
0373     unsigned long long freq;
0374     bool power_down;
0375     unsigned int bit, readval, reg;
0376     int ret;
0377 
0378     mutex_lock(&st->lock);
0379     switch ((u32)private) {
0380     case ADF4371_FREQ:
0381         ret = kstrtoull(buf, 10, &freq);
0382         if (ret)
0383             break;
0384 
0385         ret = adf4371_set_freq(st, freq, chan->channel);
0386         break;
0387     case ADF4371_POWER_DOWN:
0388         ret = kstrtobool(buf, &power_down);
0389         if (ret)
0390             break;
0391 
0392         reg = adf4371_pwrdown_ch[chan->channel].reg;
0393         bit = adf4371_pwrdown_ch[chan->channel].bit;
0394         ret = regmap_read(st->regmap, reg, &readval);
0395         if (ret < 0)
0396             break;
0397 
0398         readval &= ~BIT(bit);
0399         readval |= (!power_down << bit);
0400 
0401         ret = regmap_write(st->regmap, reg, readval);
0402         break;
0403     default:
0404         ret = -EINVAL;
0405         break;
0406     }
0407     mutex_unlock(&st->lock);
0408 
0409     return ret ? ret : len;
0410 }
0411 
0412 #define _ADF4371_EXT_INFO(_name, _ident) { \
0413         .name = _name, \
0414         .read = adf4371_read, \
0415         .write = adf4371_write, \
0416         .private = _ident, \
0417         .shared = IIO_SEPARATE, \
0418 }
0419 
0420 static const struct iio_chan_spec_ext_info adf4371_ext_info[] = {
0421     /*
0422      * Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
0423      * values > 2^32 in order to support the entire frequency range
0424      * in Hz. Using scale is a bit ugly.
0425      */
0426     _ADF4371_EXT_INFO("frequency", ADF4371_FREQ),
0427     _ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN),
0428     _ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME),
0429     { },
0430 };
0431 
0432 #define ADF4371_CHANNEL(index) { \
0433         .type = IIO_ALTVOLTAGE, \
0434         .output = 1, \
0435         .channel = index, \
0436         .ext_info = adf4371_ext_info, \
0437         .indexed = 1, \
0438     }
0439 
0440 static const struct iio_chan_spec adf4371_chan[] = {
0441     ADF4371_CHANNEL(ADF4371_CH_RF8),
0442     ADF4371_CHANNEL(ADF4371_CH_RFAUX8),
0443     ADF4371_CHANNEL(ADF4371_CH_RF16),
0444     ADF4371_CHANNEL(ADF4371_CH_RF32),
0445 };
0446 
0447 static const struct adf4371_chip_info adf4371_chip_info[] = {
0448     [ADF4371] = {
0449         .channels = adf4371_chan,
0450         .num_channels = 4,
0451     },
0452     [ADF4372] = {
0453         .channels = adf4371_chan,
0454         .num_channels = 3,
0455     }
0456 };
0457 
0458 static int adf4371_reg_access(struct iio_dev *indio_dev,
0459                   unsigned int reg,
0460                   unsigned int writeval,
0461                   unsigned int *readval)
0462 {
0463     struct adf4371_state *st = iio_priv(indio_dev);
0464 
0465     if (readval)
0466         return regmap_read(st->regmap, reg, readval);
0467     else
0468         return regmap_write(st->regmap, reg, writeval);
0469 }
0470 
0471 static const struct iio_info adf4371_info = {
0472     .debugfs_reg_access = &adf4371_reg_access,
0473 };
0474 
0475 static int adf4371_setup(struct adf4371_state *st)
0476 {
0477     unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
0478     unsigned int vco_band_div, tmp;
0479     int ret;
0480 
0481     /* Perform a software reset */
0482     ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD);
0483     if (ret < 0)
0484         return ret;
0485 
0486     ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults,
0487                      ARRAY_SIZE(adf4371_reg_defaults));
0488     if (ret < 0)
0489         return ret;
0490 
0491     /* Mute to Lock Detect */
0492     if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) {
0493         ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25),
0494                      ADF4371_MUTE_LD_MSK,
0495                      ADF4371_MUTE_LD(1));
0496         if (ret < 0)
0497             return ret;
0498     }
0499 
0500     /* Set address in ascending order, so the bulk_write() will work */
0501     ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
0502                  ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
0503                  ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
0504     if (ret < 0)
0505         return ret;
0506     /*
0507      * Calculate and maximize PFD frequency
0508      * fPFD = REFIN × ((1 + D)/(R × (1 + T)))
0509      * Where D is the REFIN doubler bit, T is the reference divide by 2,
0510      * R is the reference division factor
0511      * TODO: it is assumed D and T equal 0.
0512      */
0513     do {
0514         st->ref_div_factor++;
0515         st->fpfd = st->clkin_freq / st->ref_div_factor;
0516     } while (st->fpfd > ADF4371_MAX_FREQ_PFD);
0517 
0518     /* Calculate Timeouts */
0519     vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U);
0520 
0521     tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U);
0522     do {
0523         timeout++;
0524         if (timeout > 1023) {
0525             timeout = 2;
0526             synth_timeout++;
0527         }
0528     } while (synth_timeout * 1024 + timeout <= 20 * tmp);
0529 
0530     do {
0531         vco_alc_timeout++;
0532     } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp);
0533 
0534     st->buf[0] = vco_band_div;
0535     st->buf[1] = timeout & 0xFF;
0536     st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04;
0537     st->buf[3] = synth_timeout;
0538     st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout);
0539 
0540     return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5);
0541 }
0542 
0543 static void adf4371_clk_disable(void *data)
0544 {
0545     struct adf4371_state *st = data;
0546 
0547     clk_disable_unprepare(st->clkin);
0548 }
0549 
0550 static int adf4371_probe(struct spi_device *spi)
0551 {
0552     const struct spi_device_id *id = spi_get_device_id(spi);
0553     struct iio_dev *indio_dev;
0554     struct adf4371_state *st;
0555     struct regmap *regmap;
0556     int ret;
0557 
0558     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0559     if (!indio_dev)
0560         return -ENOMEM;
0561 
0562     regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config);
0563     if (IS_ERR(regmap)) {
0564         dev_err(&spi->dev, "Error initializing spi regmap: %ld\n",
0565             PTR_ERR(regmap));
0566         return PTR_ERR(regmap);
0567     }
0568 
0569     st = iio_priv(indio_dev);
0570     spi_set_drvdata(spi, indio_dev);
0571     st->spi = spi;
0572     st->regmap = regmap;
0573     mutex_init(&st->lock);
0574 
0575     st->chip_info = &adf4371_chip_info[id->driver_data];
0576     indio_dev->name = id->name;
0577     indio_dev->info = &adf4371_info;
0578     indio_dev->modes = INDIO_DIRECT_MODE;
0579     indio_dev->channels = st->chip_info->channels;
0580     indio_dev->num_channels = st->chip_info->num_channels;
0581 
0582     st->clkin = devm_clk_get(&spi->dev, "clkin");
0583     if (IS_ERR(st->clkin))
0584         return PTR_ERR(st->clkin);
0585 
0586     ret = clk_prepare_enable(st->clkin);
0587     if (ret < 0)
0588         return ret;
0589 
0590     ret = devm_add_action_or_reset(&spi->dev, adf4371_clk_disable, st);
0591     if (ret)
0592         return ret;
0593 
0594     st->clkin_freq = clk_get_rate(st->clkin);
0595 
0596     ret = adf4371_setup(st);
0597     if (ret < 0) {
0598         dev_err(&spi->dev, "ADF4371 setup failed\n");
0599         return ret;
0600     }
0601 
0602     return devm_iio_device_register(&spi->dev, indio_dev);
0603 }
0604 
0605 static const struct spi_device_id adf4371_id_table[] = {
0606     { "adf4371", ADF4371 },
0607     { "adf4372", ADF4372 },
0608     {}
0609 };
0610 MODULE_DEVICE_TABLE(spi, adf4371_id_table);
0611 
0612 static const struct of_device_id adf4371_of_match[] = {
0613     { .compatible = "adi,adf4371" },
0614     { .compatible = "adi,adf4372" },
0615     { },
0616 };
0617 MODULE_DEVICE_TABLE(of, adf4371_of_match);
0618 
0619 static struct spi_driver adf4371_driver = {
0620     .driver = {
0621         .name = "adf4371",
0622         .of_match_table = adf4371_of_match,
0623     },
0624     .probe = adf4371_probe,
0625     .id_table = adf4371_id_table,
0626 };
0627 module_spi_driver(adf4371_driver);
0628 
0629 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
0630 MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL");
0631 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!