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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADF4350/ADF4351 SPI Wideband Synthesizer driver
0004  *
0005  * Copyright 2012-2013 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/device.h>
0009 #include <linux/kernel.h>
0010 #include <linux/mod_devicetable.h>
0011 #include <linux/module.h>
0012 #include <linux/property.h>
0013 #include <linux/slab.h>
0014 #include <linux/sysfs.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/err.h>
0018 #include <linux/gcd.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <asm/div64.h>
0021 #include <linux/clk.h>
0022 
0023 #include <linux/iio/iio.h>
0024 #include <linux/iio/sysfs.h>
0025 #include <linux/iio/frequency/adf4350.h>
0026 
0027 enum {
0028     ADF4350_FREQ,
0029     ADF4350_FREQ_REFIN,
0030     ADF4350_FREQ_RESOLUTION,
0031     ADF4350_PWRDOWN,
0032 };
0033 
0034 struct adf4350_state {
0035     struct spi_device       *spi;
0036     struct regulator        *reg;
0037     struct gpio_desc        *lock_detect_gpiod;
0038     struct adf4350_platform_data    *pdata;
0039     struct clk          *clk;
0040     unsigned long           clkin;
0041     unsigned long           chspc; /* Channel Spacing */
0042     unsigned long           fpfd; /* Phase Frequency Detector */
0043     unsigned long           min_out_freq;
0044     unsigned            r0_fract;
0045     unsigned            r0_int;
0046     unsigned            r1_mod;
0047     unsigned            r4_rf_div_sel;
0048     unsigned long           regs[6];
0049     unsigned long           regs_hw[6];
0050     unsigned long long      freq_req;
0051     /*
0052      * Lock to protect the state of the device from potential concurrent
0053      * writes. The device is configured via a sequence of SPI writes,
0054      * and this lock is meant to prevent the start of another sequence
0055      * before another one has finished.
0056      */
0057     struct mutex            lock;
0058     /*
0059      * DMA (thus cache coherency maintenance) may require that
0060      * transfer buffers live in their own cache lines.
0061      */
0062     __be32              val __aligned(IIO_DMA_MINALIGN);
0063 };
0064 
0065 static struct adf4350_platform_data default_pdata = {
0066     .channel_spacing = 10000,
0067     .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
0068                 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
0069     .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
0070     .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
0071                 ADF4350_REG4_MUTE_TILL_LOCK_EN,
0072 };
0073 
0074 static int adf4350_sync_config(struct adf4350_state *st)
0075 {
0076     int ret, i, doublebuf = 0;
0077 
0078     for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
0079         if ((st->regs_hw[i] != st->regs[i]) ||
0080             ((i == ADF4350_REG0) && doublebuf)) {
0081             switch (i) {
0082             case ADF4350_REG1:
0083             case ADF4350_REG4:
0084                 doublebuf = 1;
0085                 break;
0086             }
0087 
0088             st->val  = cpu_to_be32(st->regs[i] | i);
0089             ret = spi_write(st->spi, &st->val, 4);
0090             if (ret < 0)
0091                 return ret;
0092             st->regs_hw[i] = st->regs[i];
0093             dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
0094                 i, (u32)st->regs[i] | i);
0095         }
0096     }
0097     return 0;
0098 }
0099 
0100 static int adf4350_reg_access(struct iio_dev *indio_dev,
0101                   unsigned reg, unsigned writeval,
0102                   unsigned *readval)
0103 {
0104     struct adf4350_state *st = iio_priv(indio_dev);
0105     int ret;
0106 
0107     if (reg > ADF4350_REG5)
0108         return -EINVAL;
0109 
0110     mutex_lock(&st->lock);
0111     if (readval == NULL) {
0112         st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
0113         ret = adf4350_sync_config(st);
0114     } else {
0115         *readval =  st->regs_hw[reg];
0116         ret = 0;
0117     }
0118     mutex_unlock(&st->lock);
0119 
0120     return ret;
0121 }
0122 
0123 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
0124 {
0125     struct adf4350_platform_data *pdata = st->pdata;
0126 
0127     do {
0128         r_cnt++;
0129         st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
0130                (r_cnt * (pdata->ref_div2_en ? 2 : 1));
0131     } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
0132 
0133     return r_cnt;
0134 }
0135 
0136 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
0137 {
0138     struct adf4350_platform_data *pdata = st->pdata;
0139     u64 tmp;
0140     u32 div_gcd, prescaler, chspc;
0141     u16 mdiv, r_cnt = 0;
0142     u8 band_sel_div;
0143 
0144     if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
0145         return -EINVAL;
0146 
0147     if (freq > ADF4350_MAX_FREQ_45_PRESC) {
0148         prescaler = ADF4350_REG1_PRESCALER;
0149         mdiv = 75;
0150     } else {
0151         prescaler = 0;
0152         mdiv = 23;
0153     }
0154 
0155     st->r4_rf_div_sel = 0;
0156 
0157     while (freq < ADF4350_MIN_VCO_FREQ) {
0158         freq <<= 1;
0159         st->r4_rf_div_sel++;
0160     }
0161 
0162     /*
0163      * Allow a predefined reference division factor
0164      * if not set, compute our own
0165      */
0166     if (pdata->ref_div_factor)
0167         r_cnt = pdata->ref_div_factor - 1;
0168 
0169     chspc = st->chspc;
0170 
0171     do  {
0172         do {
0173             do {
0174                 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
0175                 st->r1_mod = st->fpfd / chspc;
0176                 if (r_cnt > ADF4350_MAX_R_CNT) {
0177                     /* try higher spacing values */
0178                     chspc++;
0179                     r_cnt = 0;
0180                 }
0181             } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
0182         } while (r_cnt == 0);
0183 
0184         tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
0185         do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
0186         st->r0_fract = do_div(tmp, st->r1_mod);
0187         st->r0_int = tmp;
0188     } while (mdiv > st->r0_int);
0189 
0190     band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
0191 
0192     if (st->r0_fract && st->r1_mod) {
0193         div_gcd = gcd(st->r1_mod, st->r0_fract);
0194         st->r1_mod /= div_gcd;
0195         st->r0_fract /= div_gcd;
0196     } else {
0197         st->r0_fract = 0;
0198         st->r1_mod = 1;
0199     }
0200 
0201     dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
0202         "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
0203         "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
0204         freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
0205         1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
0206         band_sel_div);
0207 
0208     st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
0209                  ADF4350_REG0_FRACT(st->r0_fract);
0210 
0211     st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
0212                  ADF4350_REG1_MOD(st->r1_mod) |
0213                  prescaler;
0214 
0215     st->regs[ADF4350_REG2] =
0216         ADF4350_REG2_10BIT_R_CNT(r_cnt) |
0217         ADF4350_REG2_DOUBLE_BUFF_EN |
0218         (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
0219         (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
0220         (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
0221         ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
0222         ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
0223         ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
0224 
0225     st->regs[ADF4350_REG3] = pdata->r3_user_settings &
0226                  (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
0227                  ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
0228                  ADF4350_REG3_12BIT_CSR_EN |
0229                  ADF4351_REG3_CHARGE_CANCELLATION_EN |
0230                  ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
0231                  ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
0232 
0233     st->regs[ADF4350_REG4] =
0234         ADF4350_REG4_FEEDBACK_FUND |
0235         ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
0236         ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
0237         ADF4350_REG4_RF_OUT_EN |
0238         (pdata->r4_user_settings &
0239         (ADF4350_REG4_OUTPUT_PWR(0x3) |
0240         ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
0241         ADF4350_REG4_AUX_OUTPUT_EN |
0242         ADF4350_REG4_AUX_OUTPUT_FUND |
0243         ADF4350_REG4_MUTE_TILL_LOCK_EN));
0244 
0245     st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
0246     st->freq_req = freq;
0247 
0248     return adf4350_sync_config(st);
0249 }
0250 
0251 static ssize_t adf4350_write(struct iio_dev *indio_dev,
0252                     uintptr_t private,
0253                     const struct iio_chan_spec *chan,
0254                     const char *buf, size_t len)
0255 {
0256     struct adf4350_state *st = iio_priv(indio_dev);
0257     unsigned long long readin;
0258     unsigned long tmp;
0259     int ret;
0260 
0261     ret = kstrtoull(buf, 10, &readin);
0262     if (ret)
0263         return ret;
0264 
0265     mutex_lock(&st->lock);
0266     switch ((u32)private) {
0267     case ADF4350_FREQ:
0268         ret = adf4350_set_freq(st, readin);
0269         break;
0270     case ADF4350_FREQ_REFIN:
0271         if (readin > ADF4350_MAX_FREQ_REFIN) {
0272             ret = -EINVAL;
0273             break;
0274         }
0275 
0276         if (st->clk) {
0277             tmp = clk_round_rate(st->clk, readin);
0278             if (tmp != readin) {
0279                 ret = -EINVAL;
0280                 break;
0281             }
0282             ret = clk_set_rate(st->clk, tmp);
0283             if (ret < 0)
0284                 break;
0285         }
0286         st->clkin = readin;
0287         ret = adf4350_set_freq(st, st->freq_req);
0288         break;
0289     case ADF4350_FREQ_RESOLUTION:
0290         if (readin == 0)
0291             ret = -EINVAL;
0292         else
0293             st->chspc = readin;
0294         break;
0295     case ADF4350_PWRDOWN:
0296         if (readin)
0297             st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
0298         else
0299             st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
0300 
0301         adf4350_sync_config(st);
0302         break;
0303     default:
0304         ret = -EINVAL;
0305     }
0306     mutex_unlock(&st->lock);
0307 
0308     return ret ? ret : len;
0309 }
0310 
0311 static ssize_t adf4350_read(struct iio_dev *indio_dev,
0312                    uintptr_t private,
0313                    const struct iio_chan_spec *chan,
0314                    char *buf)
0315 {
0316     struct adf4350_state *st = iio_priv(indio_dev);
0317     unsigned long long val;
0318     int ret = 0;
0319 
0320     mutex_lock(&st->lock);
0321     switch ((u32)private) {
0322     case ADF4350_FREQ:
0323         val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
0324             (u64)st->fpfd;
0325         do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
0326         /* PLL unlocked? return error */
0327         if (st->lock_detect_gpiod)
0328             if (!gpiod_get_value(st->lock_detect_gpiod)) {
0329                 dev_dbg(&st->spi->dev, "PLL un-locked\n");
0330                 ret = -EBUSY;
0331             }
0332         break;
0333     case ADF4350_FREQ_REFIN:
0334         if (st->clk)
0335             st->clkin = clk_get_rate(st->clk);
0336 
0337         val = st->clkin;
0338         break;
0339     case ADF4350_FREQ_RESOLUTION:
0340         val = st->chspc;
0341         break;
0342     case ADF4350_PWRDOWN:
0343         val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
0344         break;
0345     default:
0346         ret = -EINVAL;
0347         val = 0;
0348     }
0349     mutex_unlock(&st->lock);
0350 
0351     return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
0352 }
0353 
0354 #define _ADF4350_EXT_INFO(_name, _ident) { \
0355     .name = _name, \
0356     .read = adf4350_read, \
0357     .write = adf4350_write, \
0358     .private = _ident, \
0359     .shared = IIO_SEPARATE, \
0360 }
0361 
0362 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
0363     /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
0364      * values > 2^32 in order to support the entire frequency range
0365      * in Hz. Using scale is a bit ugly.
0366      */
0367     _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
0368     _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
0369     _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
0370     _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
0371     { },
0372 };
0373 
0374 static const struct iio_chan_spec adf4350_chan = {
0375     .type = IIO_ALTVOLTAGE,
0376     .indexed = 1,
0377     .output = 1,
0378     .ext_info = adf4350_ext_info,
0379 };
0380 
0381 static const struct iio_info adf4350_info = {
0382     .debugfs_reg_access = &adf4350_reg_access,
0383 };
0384 
0385 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
0386 {
0387     struct adf4350_platform_data *pdata;
0388     unsigned int tmp;
0389 
0390     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
0391     if (!pdata)
0392         return NULL;
0393 
0394     snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev));
0395 
0396     tmp = 10000;
0397     device_property_read_u32(dev, "adi,channel-spacing", &tmp);
0398     pdata->channel_spacing = tmp;
0399 
0400     tmp = 0;
0401     device_property_read_u32(dev, "adi,power-up-frequency", &tmp);
0402     pdata->power_up_frequency = tmp;
0403 
0404     tmp = 0;
0405     device_property_read_u32(dev, "adi,reference-div-factor", &tmp);
0406     pdata->ref_div_factor = tmp;
0407 
0408     pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
0409     pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");
0410 
0411     /* r2_user_settings */
0412     pdata->r2_user_settings = 0;
0413     if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"))
0414         pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS;
0415     if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable"))
0416         pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns;
0417     if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable"))
0418         pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N;
0419 
0420     tmp = 2500;
0421     device_property_read_u32(dev, "adi,charge-pump-current", &tmp);
0422     pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
0423 
0424     tmp = 0;
0425     device_property_read_u32(dev, "adi,muxout-select", &tmp);
0426     pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
0427 
0428     if (device_property_read_bool(dev, "adi,low-spur-mode-enable"))
0429         pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3);
0430 
0431     /* r3_user_settings */
0432 
0433     pdata->r3_user_settings = 0;
0434     if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable"))
0435         pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN;
0436     if (device_property_read_bool(dev, "adi,charge-cancellation-enable"))
0437         pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN;
0438     if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable"))
0439         pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN;
0440     if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable"))
0441         pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH;
0442 
0443     tmp = 0;
0444     device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp);
0445     pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
0446 
0447     tmp = 0;
0448     device_property_read_u32(dev, "adi,clk-divider-mode", &tmp);
0449     pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
0450 
0451     /* r4_user_settings */
0452 
0453     pdata->r4_user_settings = 0;
0454     if (device_property_read_bool(dev, "adi,aux-output-enable"))
0455         pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN;
0456     if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable"))
0457         pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND;
0458     if (device_property_read_bool(dev, "adi,mute-till-lock-enable"))
0459         pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN;
0460 
0461     tmp = 0;
0462     device_property_read_u32(dev, "adi,output-power", &tmp);
0463     pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
0464 
0465     tmp = 0;
0466     device_property_read_u32(dev, "adi,aux-output-power", &tmp);
0467     pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
0468 
0469     return pdata;
0470 }
0471 
0472 static int adf4350_probe(struct spi_device *spi)
0473 {
0474     struct adf4350_platform_data *pdata;
0475     struct iio_dev *indio_dev;
0476     struct adf4350_state *st;
0477     struct clk *clk = NULL;
0478     int ret;
0479 
0480     if (dev_fwnode(&spi->dev)) {
0481         pdata = adf4350_parse_dt(&spi->dev);
0482         if (pdata == NULL)
0483             return -EINVAL;
0484     } else {
0485         pdata = spi->dev.platform_data;
0486     }
0487 
0488     if (!pdata) {
0489         dev_warn(&spi->dev, "no platform data? using default\n");
0490         pdata = &default_pdata;
0491     }
0492 
0493     if (!pdata->clkin) {
0494         clk = devm_clk_get(&spi->dev, "clkin");
0495         if (IS_ERR(clk))
0496             return -EPROBE_DEFER;
0497 
0498         ret = clk_prepare_enable(clk);
0499         if (ret < 0)
0500             return ret;
0501     }
0502 
0503     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0504     if (indio_dev == NULL) {
0505         ret =  -ENOMEM;
0506         goto error_disable_clk;
0507     }
0508 
0509     st = iio_priv(indio_dev);
0510 
0511     st->reg = devm_regulator_get(&spi->dev, "vcc");
0512     if (!IS_ERR(st->reg)) {
0513         ret = regulator_enable(st->reg);
0514         if (ret)
0515             goto error_disable_clk;
0516     }
0517 
0518     spi_set_drvdata(spi, indio_dev);
0519     st->spi = spi;
0520     st->pdata = pdata;
0521 
0522     indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
0523         spi_get_device_id(spi)->name;
0524 
0525     indio_dev->info = &adf4350_info;
0526     indio_dev->modes = INDIO_DIRECT_MODE;
0527     indio_dev->channels = &adf4350_chan;
0528     indio_dev->num_channels = 1;
0529 
0530     mutex_init(&st->lock);
0531 
0532     st->chspc = pdata->channel_spacing;
0533     if (clk) {
0534         st->clk = clk;
0535         st->clkin = clk_get_rate(clk);
0536     } else {
0537         st->clkin = pdata->clkin;
0538     }
0539 
0540     st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
0541         ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
0542 
0543     memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
0544 
0545     st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
0546                             GPIOD_IN);
0547     if (IS_ERR(st->lock_detect_gpiod)) {
0548         ret = PTR_ERR(st->lock_detect_gpiod);
0549         goto error_disable_reg;
0550     }
0551 
0552     if (pdata->power_up_frequency) {
0553         ret = adf4350_set_freq(st, pdata->power_up_frequency);
0554         if (ret)
0555             goto error_disable_reg;
0556     }
0557 
0558     ret = iio_device_register(indio_dev);
0559     if (ret)
0560         goto error_disable_reg;
0561 
0562     return 0;
0563 
0564 error_disable_reg:
0565     if (!IS_ERR(st->reg))
0566         regulator_disable(st->reg);
0567 error_disable_clk:
0568     clk_disable_unprepare(clk);
0569 
0570     return ret;
0571 }
0572 
0573 static void adf4350_remove(struct spi_device *spi)
0574 {
0575     struct iio_dev *indio_dev = spi_get_drvdata(spi);
0576     struct adf4350_state *st = iio_priv(indio_dev);
0577     struct regulator *reg = st->reg;
0578 
0579     st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
0580     adf4350_sync_config(st);
0581 
0582     iio_device_unregister(indio_dev);
0583 
0584     clk_disable_unprepare(st->clk);
0585 
0586     if (!IS_ERR(reg))
0587         regulator_disable(reg);
0588 }
0589 
0590 static const struct of_device_id adf4350_of_match[] = {
0591     { .compatible = "adi,adf4350", },
0592     { .compatible = "adi,adf4351", },
0593     { /* sentinel */ },
0594 };
0595 MODULE_DEVICE_TABLE(of, adf4350_of_match);
0596 
0597 static const struct spi_device_id adf4350_id[] = {
0598     {"adf4350", 4350},
0599     {"adf4351", 4351},
0600     {}
0601 };
0602 MODULE_DEVICE_TABLE(spi, adf4350_id);
0603 
0604 static struct spi_driver adf4350_driver = {
0605     .driver = {
0606         .name   = "adf4350",
0607         .of_match_table = adf4350_of_match,
0608     },
0609     .probe      = adf4350_probe,
0610     .remove     = adf4350_remove,
0611     .id_table   = adf4350_id,
0612 };
0613 module_spi_driver(adf4350_driver);
0614 
0615 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0616 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
0617 MODULE_LICENSE("GPL v2");
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