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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD9523 SPI Low Jitter Clock Generator
0004  *
0005  * Copyright 2012 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/device.h>
0009 #include <linux/kernel.h>
0010 #include <linux/slab.h>
0011 #include <linux/sysfs.h>
0012 #include <linux/spi/spi.h>
0013 #include <linux/regulator/consumer.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/err.h>
0016 #include <linux/module.h>
0017 #include <linux/delay.h>
0018 
0019 #include <linux/iio/iio.h>
0020 #include <linux/iio/sysfs.h>
0021 #include <linux/iio/frequency/ad9523.h>
0022 
0023 #define AD9523_READ (1 << 15)
0024 #define AD9523_WRITE    (0 << 15)
0025 #define AD9523_CNT(x)   (((x) - 1) << 13)
0026 #define AD9523_ADDR(x)  ((x) & 0xFFF)
0027 
0028 #define AD9523_R1B  (1 << 16)
0029 #define AD9523_R2B  (2 << 16)
0030 #define AD9523_R3B  (3 << 16)
0031 #define AD9523_TRANSF_LEN(x)            ((x) >> 16)
0032 
0033 #define AD9523_SERIAL_PORT_CONFIG       (AD9523_R1B | 0x0)
0034 #define AD9523_VERSION_REGISTER         (AD9523_R1B | 0x2)
0035 #define AD9523_PART_REGISTER            (AD9523_R1B | 0x3)
0036 #define AD9523_READBACK_CTRL            (AD9523_R1B | 0x4)
0037 
0038 #define AD9523_EEPROM_CUSTOMER_VERSION_ID   (AD9523_R2B | 0x6)
0039 
0040 #define AD9523_PLL1_REF_A_DIVIDER       (AD9523_R2B | 0x11)
0041 #define AD9523_PLL1_REF_B_DIVIDER       (AD9523_R2B | 0x13)
0042 #define AD9523_PLL1_REF_TEST_DIVIDER        (AD9523_R1B | 0x14)
0043 #define AD9523_PLL1_FEEDBACK_DIVIDER        (AD9523_R2B | 0x17)
0044 #define AD9523_PLL1_CHARGE_PUMP_CTRL        (AD9523_R2B | 0x19)
0045 #define AD9523_PLL1_INPUT_RECEIVERS_CTRL    (AD9523_R1B | 0x1A)
0046 #define AD9523_PLL1_REF_CTRL            (AD9523_R1B | 0x1B)
0047 #define AD9523_PLL1_MISC_CTRL           (AD9523_R1B | 0x1C)
0048 #define AD9523_PLL1_LOOP_FILTER_CTRL        (AD9523_R1B | 0x1D)
0049 
0050 #define AD9523_PLL2_CHARGE_PUMP         (AD9523_R1B | 0xF0)
0051 #define AD9523_PLL2_FEEDBACK_DIVIDER_AB     (AD9523_R1B | 0xF1)
0052 #define AD9523_PLL2_CTRL            (AD9523_R1B | 0xF2)
0053 #define AD9523_PLL2_VCO_CTRL            (AD9523_R1B | 0xF3)
0054 #define AD9523_PLL2_VCO_DIVIDER         (AD9523_R1B | 0xF4)
0055 #define AD9523_PLL2_LOOP_FILTER_CTRL        (AD9523_R2B | 0xF6)
0056 #define AD9523_PLL2_R2_DIVIDER          (AD9523_R1B | 0xF7)
0057 
0058 #define AD9523_CHANNEL_CLOCK_DIST(ch)       (AD9523_R3B | (0x192 + 3 * ch))
0059 
0060 #define AD9523_PLL1_OUTPUT_CTRL         (AD9523_R1B | 0x1BA)
0061 #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL     (AD9523_R1B | 0x1BB)
0062 
0063 #define AD9523_READBACK_0           (AD9523_R1B | 0x22C)
0064 #define AD9523_READBACK_1           (AD9523_R1B | 0x22D)
0065 
0066 #define AD9523_STATUS_SIGNALS           (AD9523_R3B | 0x232)
0067 #define AD9523_POWER_DOWN_CTRL          (AD9523_R1B | 0x233)
0068 #define AD9523_IO_UPDATE            (AD9523_R1B | 0x234)
0069 
0070 #define AD9523_EEPROM_DATA_XFER_STATUS      (AD9523_R1B | 0xB00)
0071 #define AD9523_EEPROM_ERROR_READBACK        (AD9523_R1B | 0xB01)
0072 #define AD9523_EEPROM_CTRL1         (AD9523_R1B | 0xB02)
0073 #define AD9523_EEPROM_CTRL2         (AD9523_R1B | 0xB03)
0074 
0075 /* AD9523_SERIAL_PORT_CONFIG */
0076 
0077 #define AD9523_SER_CONF_SDO_ACTIVE      (1 << 7)
0078 #define AD9523_SER_CONF_SOFT_RESET      (1 << 5)
0079 
0080 /* AD9523_READBACK_CTRL */
0081 #define AD9523_READBACK_CTRL_READ_BUFFERED  (1 << 0)
0082 
0083 /* AD9523_PLL1_CHARGE_PUMP_CTRL */
0084 #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x)   (((x) / 500) & 0x7F)
0085 #define AD9523_PLL1_CHARGE_PUMP_TRISTATE    (1 << 7)
0086 #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
0087 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN  (2 << 8)
0088 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP    (1 << 8)
0089 #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE   (0 << 8)
0090 #define AD9523_PLL1_BACKLASH_PW_MIN     (0 << 10)
0091 #define AD9523_PLL1_BACKLASH_PW_LOW     (1 << 10)
0092 #define AD9523_PLL1_BACKLASH_PW_HIGH        (2 << 10)
0093 #define AD9523_PLL1_BACKLASH_PW_MAX     (3 << 10)
0094 
0095 /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
0096 #define AD9523_PLL1_REF_TEST_RCV_EN     (1 << 7)
0097 #define AD9523_PLL1_REFB_DIFF_RCV_EN        (1 << 6)
0098 #define AD9523_PLL1_REFA_DIFF_RCV_EN        (1 << 5)
0099 #define AD9523_PLL1_REFB_RCV_EN         (1 << 4)
0100 #define AD9523_PLL1_REFA_RCV_EN         (1 << 3)
0101 #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN   (1 << 2)
0102 #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN  (1 << 1)
0103 #define AD9523_PLL1_OSC_IN_DIFF_EN      (1 << 0)
0104 
0105 /* AD9523_PLL1_REF_CTRL */
0106 #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN  (1 << 7)
0107 #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN  (1 << 6)
0108 #define AD9523_PLL1_ZERO_DELAY_MODE_INT     (1 << 5)
0109 #define AD9523_PLL1_ZERO_DELAY_MODE_EXT     (0 << 5)
0110 #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN  (1 << 4)
0111 #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN   (1 << 3)
0112 #define AD9523_PLL1_ZD_IN_DIFF_EN       (1 << 2)
0113 #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN    (1 << 1)
0114 #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN    (1 << 0)
0115 
0116 /* AD9523_PLL1_MISC_CTRL */
0117 #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN  (1 << 7)
0118 #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN    (1 << 6)
0119 #define AD9523_PLL1_REF_MODE(x)         ((x) << 2)
0120 #define AD9523_PLL1_BYPASS_REFB_DIV     (1 << 1)
0121 #define AD9523_PLL1_BYPASS_REFA_DIV     (1 << 0)
0122 
0123 /* AD9523_PLL1_LOOP_FILTER_CTRL */
0124 #define AD9523_PLL1_LOOP_FILTER_RZERO(x)    ((x) & 0xF)
0125 
0126 /* AD9523_PLL2_CHARGE_PUMP */
0127 #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x)   ((x) / 3500)
0128 
0129 /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
0130 #define AD9523_PLL2_FB_NDIV_A_CNT(x)        (((x) & 0x3) << 6)
0131 #define AD9523_PLL2_FB_NDIV_B_CNT(x)        (((x) & 0x3F) << 0)
0132 #define AD9523_PLL2_FB_NDIV(a, b)       (4 * (b) + (a))
0133 
0134 /* AD9523_PLL2_CTRL */
0135 #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
0136 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN  (2 << 0)
0137 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP    (1 << 0)
0138 #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE   (0 << 0)
0139 #define AD9523_PLL2_BACKLASH_PW_MIN     (0 << 2)
0140 #define AD9523_PLL2_BACKLASH_PW_LOW     (1 << 2)
0141 #define AD9523_PLL2_BACKLASH_PW_HIGH        (2 << 2)
0142 #define AD9523_PLL2_BACKLASH_PW_MAX     (3 << 1)
0143 #define AD9523_PLL2_BACKLASH_CTRL_EN        (1 << 4)
0144 #define AD9523_PLL2_FREQ_DOUBLER_EN     (1 << 5)
0145 #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
0146 
0147 /* AD9523_PLL2_VCO_CTRL */
0148 #define AD9523_PLL2_VCO_CALIBRATE       (1 << 1)
0149 #define AD9523_PLL2_FORCE_VCO_MIDSCALE      (1 << 2)
0150 #define AD9523_PLL2_FORCE_REFERENCE_VALID   (1 << 3)
0151 #define AD9523_PLL2_FORCE_RELEASE_SYNC      (1 << 4)
0152 
0153 /* AD9523_PLL2_VCO_DIVIDER */
0154 #define AD9523_PLL2_VCO_DIV_M1(x)       ((((x) - 3) & 0x3) << 0)
0155 #define AD9523_PLL2_VCO_DIV_M2(x)       ((((x) - 3) & 0x3) << 4)
0156 #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN  (1 << 2)
0157 #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN  (1 << 6)
0158 
0159 /* AD9523_PLL2_LOOP_FILTER_CTRL */
0160 #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x)   (((x) & 0x7) << 0)
0161 #define AD9523_PLL2_LOOP_FILTER_RZERO(x)    (((x) & 0x7) << 3)
0162 #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x)   (((x) & 0x7) << 6)
0163 #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
0164 
0165 /* AD9523_PLL2_R2_DIVIDER */
0166 #define AD9523_PLL2_R2_DIVIDER_VAL(x)       (((x) & 0x1F) << 0)
0167 
0168 /* AD9523_CHANNEL_CLOCK_DIST */
0169 #define AD9523_CLK_DIST_DIV_PHASE(x)        (((x) & 0x3F) << 18)
0170 #define AD9523_CLK_DIST_DIV_PHASE_REV(x)    ((ret >> 18) & 0x3F)
0171 #define AD9523_CLK_DIST_DIV(x)          ((((x) - 1) & 0x3FF) << 8)
0172 #define AD9523_CLK_DIST_DIV_REV(x)      (((ret >> 8) & 0x3FF) + 1)
0173 #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN   (1 << 7)
0174 #define AD9523_CLK_DIST_IGNORE_SYNC_EN      (1 << 6)
0175 #define AD9523_CLK_DIST_PWR_DOWN_EN     (1 << 5)
0176 #define AD9523_CLK_DIST_LOW_PWR_MODE_EN     (1 << 4)
0177 #define AD9523_CLK_DIST_DRIVER_MODE(x)      (((x) & 0xF) << 0)
0178 
0179 /* AD9523_PLL1_OUTPUT_CTRL */
0180 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2    (1 << 7)
0181 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2    (1 << 6)
0182 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2    (1 << 5)
0183 #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK     (1 << 4)
0184 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1      (0 << 0)
0185 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2      (1 << 0)
0186 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4      (2 << 0)
0187 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8      (4 << 0)
0188 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16     (8 << 0)
0189 
0190 /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
0191 #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)
0192 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)
0193 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)
0194 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)
0195 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3   (1 << 3)
0196 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2   (1 << 2)
0197 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1   (1 << 1)
0198 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0   (1 << 0)
0199 
0200 /* AD9523_READBACK_0 */
0201 #define AD9523_READBACK_0_STAT_PLL2_REF_CLK     (1 << 7)
0202 #define AD9523_READBACK_0_STAT_PLL2_FB_CLK      (1 << 6)
0203 #define AD9523_READBACK_0_STAT_VCXO         (1 << 5)
0204 #define AD9523_READBACK_0_STAT_REF_TEST         (1 << 4)
0205 #define AD9523_READBACK_0_STAT_REFB         (1 << 3)
0206 #define AD9523_READBACK_0_STAT_REFA         (1 << 2)
0207 #define AD9523_READBACK_0_STAT_PLL2_LD          (1 << 1)
0208 #define AD9523_READBACK_0_STAT_PLL1_LD          (1 << 0)
0209 
0210 /* AD9523_READBACK_1 */
0211 #define AD9523_READBACK_1_HOLDOVER_ACTIVE       (1 << 3)
0212 #define AD9523_READBACK_1_AUTOMODE_SEL_REFB     (1 << 2)
0213 #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS     (1 << 0)
0214 
0215 /* AD9523_STATUS_SIGNALS */
0216 #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL     (1 << 16)
0217 #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED       (0x302)
0218 /* AD9523_POWER_DOWN_CTRL */
0219 #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN        (1 << 2)
0220 #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN        (1 << 1)
0221 #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN        (1 << 0)
0222 
0223 /* AD9523_IO_UPDATE */
0224 #define AD9523_IO_UPDATE_EN             (1 << 0)
0225 
0226 /* AD9523_EEPROM_DATA_XFER_STATUS */
0227 #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS     (1 << 0)
0228 
0229 /* AD9523_EEPROM_ERROR_READBACK */
0230 #define AD9523_EEPROM_ERROR_READBACK_FAIL       (1 << 0)
0231 
0232 /* AD9523_EEPROM_CTRL1 */
0233 #define AD9523_EEPROM_CTRL1_SOFT_EEPROM         (1 << 1)
0234 #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS   (1 << 0)
0235 
0236 /* AD9523_EEPROM_CTRL2 */
0237 #define AD9523_EEPROM_CTRL2_REG2EEPROM          (1 << 0)
0238 
0239 #define AD9523_NUM_CHAN                 14
0240 #define AD9523_NUM_CHAN_ALT_CLK_SRC         10
0241 
0242 /* Helpers to avoid excess line breaks */
0243 #define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)
0244 #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
0245 
0246 enum {
0247     AD9523_STAT_PLL1_LD,
0248     AD9523_STAT_PLL2_LD,
0249     AD9523_STAT_REFA,
0250     AD9523_STAT_REFB,
0251     AD9523_STAT_REF_TEST,
0252     AD9523_STAT_VCXO,
0253     AD9523_STAT_PLL2_FB_CLK,
0254     AD9523_STAT_PLL2_REF_CLK,
0255     AD9523_SYNC,
0256     AD9523_EEPROM,
0257 };
0258 
0259 enum {
0260     AD9523_VCO1,
0261     AD9523_VCO2,
0262     AD9523_VCXO,
0263     AD9523_NUM_CLK_SRC,
0264 };
0265 
0266 struct ad9523_state {
0267     struct spi_device       *spi;
0268     struct regulator        *reg;
0269     struct ad9523_platform_data *pdata;
0270     struct iio_chan_spec        ad9523_channels[AD9523_NUM_CHAN];
0271     struct gpio_desc        *pwrdown_gpio;
0272     struct gpio_desc        *reset_gpio;
0273     struct gpio_desc        *sync_gpio;
0274 
0275     unsigned long       vcxo_freq;
0276     unsigned long       vco_freq;
0277     unsigned long       vco_out_freq[AD9523_NUM_CLK_SRC];
0278     unsigned char       vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC];
0279 
0280     /*
0281      * Lock for accessing device registers. Some operations require
0282      * multiple consecutive R/W operations, during which the device
0283      * shouldn't be interrupted.  The buffers are also shared across
0284      * all operations so need to be protected on stand alone reads and
0285      * writes.
0286      */
0287     struct mutex        lock;
0288 
0289     /*
0290      * DMA (thus cache coherency maintenance) may require that
0291      * transfer buffers live in their own cache lines.
0292      */
0293     union {
0294         __be32 d32;
0295         u8 d8[4];
0296     } data[2] __aligned(IIO_DMA_MINALIGN);
0297 };
0298 
0299 static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)
0300 {
0301     struct ad9523_state *st = iio_priv(indio_dev);
0302     int ret;
0303 
0304     /* We encode the register size 1..3 bytes into the register address.
0305      * On transfer we get the size from the register datum, and make sure
0306      * the result is properly aligned.
0307      */
0308 
0309     struct spi_transfer t[] = {
0310         {
0311             .tx_buf = &st->data[0].d8[2],
0312             .len = 2,
0313         }, {
0314             .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
0315             .len = AD9523_TRANSF_LEN(addr),
0316         },
0317     };
0318 
0319     st->data[0].d32 = cpu_to_be32(AD9523_READ |
0320                       AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
0321                       AD9523_ADDR(addr));
0322 
0323     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0324     if (ret < 0)
0325         dev_err(&indio_dev->dev, "read failed (%d)", ret);
0326     else
0327         ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
0328                   (8 * (3 - AD9523_TRANSF_LEN(addr))));
0329 
0330     return ret;
0331 };
0332 
0333 static int ad9523_write(struct iio_dev *indio_dev,
0334         unsigned int addr, unsigned int val)
0335 {
0336     struct ad9523_state *st = iio_priv(indio_dev);
0337     int ret;
0338     struct spi_transfer t[] = {
0339         {
0340             .tx_buf = &st->data[0].d8[2],
0341             .len = 2,
0342         }, {
0343             .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
0344             .len = AD9523_TRANSF_LEN(addr),
0345         },
0346     };
0347 
0348     st->data[0].d32 = cpu_to_be32(AD9523_WRITE |
0349                       AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
0350                       AD9523_ADDR(addr));
0351     st->data[1].d32 = cpu_to_be32(val);
0352 
0353     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0354 
0355     if (ret < 0)
0356         dev_err(&indio_dev->dev, "write failed (%d)", ret);
0357 
0358     return ret;
0359 }
0360 
0361 static int ad9523_io_update(struct iio_dev *indio_dev)
0362 {
0363     return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN);
0364 }
0365 
0366 static int ad9523_vco_out_map(struct iio_dev *indio_dev,
0367                   unsigned int ch, unsigned int out)
0368 {
0369     struct ad9523_state *st = iio_priv(indio_dev);
0370     int ret;
0371     unsigned int mask;
0372 
0373     switch (ch) {
0374     case 0 ... 3:
0375         ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
0376         if (ret < 0)
0377             break;
0378         mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch;
0379         if (out) {
0380             ret |= mask;
0381             out = 2;
0382         } else {
0383             ret &= ~mask;
0384         }
0385         ret = ad9523_write(indio_dev,
0386                    AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
0387         break;
0388     case 4 ... 6:
0389         ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
0390         if (ret < 0)
0391             break;
0392         mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4);
0393         if (out)
0394             ret |= mask;
0395         else
0396             ret &= ~mask;
0397         ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
0398         break;
0399     case 7 ... 9:
0400         ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
0401         if (ret < 0)
0402             break;
0403         mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7);
0404         if (out)
0405             ret |= mask;
0406         else
0407             ret &= ~mask;
0408         ret = ad9523_write(indio_dev,
0409                    AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
0410         break;
0411     default:
0412         return 0;
0413     }
0414 
0415     st->vco_out_map[ch] = out;
0416 
0417     return ret;
0418 }
0419 
0420 static int ad9523_set_clock_provider(struct iio_dev *indio_dev,
0421                   unsigned int ch, unsigned long freq)
0422 {
0423     struct ad9523_state *st = iio_priv(indio_dev);
0424     long tmp1, tmp2;
0425     bool use_alt_clk_src;
0426 
0427     switch (ch) {
0428     case 0 ... 3:
0429         use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]);
0430         break;
0431     case 4 ... 9:
0432         tmp1 = st->vco_out_freq[AD9523_VCO1] / freq;
0433         tmp2 = st->vco_out_freq[AD9523_VCO2] / freq;
0434         tmp1 *= freq;
0435         tmp2 *= freq;
0436         use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq));
0437         break;
0438     default:
0439         /* Ch 10..14: No action required, return success */
0440         return 0;
0441     }
0442 
0443     return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src);
0444 }
0445 
0446 static int ad9523_store_eeprom(struct iio_dev *indio_dev)
0447 {
0448     int ret, tmp;
0449 
0450     ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
0451                AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS);
0452     if (ret < 0)
0453         return ret;
0454     ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
0455                AD9523_EEPROM_CTRL2_REG2EEPROM);
0456     if (ret < 0)
0457         return ret;
0458 
0459     tmp = 4;
0460     do {
0461         msleep(20);
0462         ret = ad9523_read(indio_dev,
0463                   AD9523_EEPROM_DATA_XFER_STATUS);
0464         if (ret < 0)
0465             return ret;
0466     } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
0467 
0468     ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
0469     if (ret < 0)
0470         return ret;
0471 
0472     ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
0473     if (ret < 0)
0474         return ret;
0475 
0476     if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
0477         dev_err(&indio_dev->dev, "Verify EEPROM failed");
0478         ret = -EIO;
0479     }
0480 
0481     return ret;
0482 }
0483 
0484 static int ad9523_sync(struct iio_dev *indio_dev)
0485 {
0486     int ret, tmp;
0487 
0488     ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
0489     if (ret < 0)
0490         return ret;
0491 
0492     tmp = ret;
0493     tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
0494 
0495     ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
0496     if (ret < 0)
0497         return ret;
0498 
0499     ad9523_io_update(indio_dev);
0500     tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
0501 
0502     ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
0503     if (ret < 0)
0504         return ret;
0505 
0506     return ad9523_io_update(indio_dev);
0507 }
0508 
0509 static ssize_t ad9523_store(struct device *dev,
0510                 struct device_attribute *attr,
0511                 const char *buf, size_t len)
0512 {
0513     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0514     struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
0515     struct ad9523_state *st = iio_priv(indio_dev);
0516     bool state;
0517     int ret;
0518 
0519     ret = kstrtobool(buf, &state);
0520     if (ret < 0)
0521         return ret;
0522 
0523     if (!state)
0524         return len;
0525 
0526     mutex_lock(&st->lock);
0527     switch ((u32)this_attr->address) {
0528     case AD9523_SYNC:
0529         ret = ad9523_sync(indio_dev);
0530         break;
0531     case AD9523_EEPROM:
0532         ret = ad9523_store_eeprom(indio_dev);
0533         break;
0534     default:
0535         ret = -ENODEV;
0536     }
0537     mutex_unlock(&st->lock);
0538 
0539     return ret ? ret : len;
0540 }
0541 
0542 static ssize_t ad9523_show(struct device *dev,
0543             struct device_attribute *attr,
0544             char *buf)
0545 {
0546     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0547     struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
0548     struct ad9523_state *st = iio_priv(indio_dev);
0549     int ret;
0550 
0551     mutex_lock(&st->lock);
0552     ret = ad9523_read(indio_dev, AD9523_READBACK_0);
0553     if (ret >= 0) {
0554         ret = sysfs_emit(buf, "%d\n", !!(ret & (1 <<
0555             (u32)this_attr->address)));
0556     }
0557     mutex_unlock(&st->lock);
0558 
0559     return ret;
0560 }
0561 
0562 static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO,
0563             ad9523_show,
0564             NULL,
0565             AD9523_STAT_PLL1_LD);
0566 
0567 static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO,
0568             ad9523_show,
0569             NULL,
0570             AD9523_STAT_PLL2_LD);
0571 
0572 static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO,
0573             ad9523_show,
0574             NULL,
0575             AD9523_STAT_REFA);
0576 
0577 static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO,
0578             ad9523_show,
0579             NULL,
0580             AD9523_STAT_REFB);
0581 
0582 static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO,
0583             ad9523_show,
0584             NULL,
0585             AD9523_STAT_REF_TEST);
0586 
0587 static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO,
0588             ad9523_show,
0589             NULL,
0590             AD9523_STAT_VCXO);
0591 
0592 static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO,
0593             ad9523_show,
0594             NULL,
0595             AD9523_STAT_PLL2_FB_CLK);
0596 
0597 static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO,
0598             ad9523_show,
0599             NULL,
0600             AD9523_STAT_PLL2_REF_CLK);
0601 
0602 static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR,
0603             NULL,
0604             ad9523_store,
0605             AD9523_SYNC);
0606 
0607 static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR,
0608             NULL,
0609             ad9523_store,
0610             AD9523_EEPROM);
0611 
0612 static struct attribute *ad9523_attributes[] = {
0613     &iio_dev_attr_sync_dividers.dev_attr.attr,
0614     &iio_dev_attr_store_eeprom.dev_attr.attr,
0615     &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr,
0616     &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr,
0617     &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr,
0618     &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr,
0619     &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr,
0620     &iio_dev_attr_vcxo_clk_present.dev_attr.attr,
0621     &iio_dev_attr_pll1_locked.dev_attr.attr,
0622     &iio_dev_attr_pll2_locked.dev_attr.attr,
0623     NULL,
0624 };
0625 
0626 static const struct attribute_group ad9523_attribute_group = {
0627     .attrs = ad9523_attributes,
0628 };
0629 
0630 static int ad9523_read_raw(struct iio_dev *indio_dev,
0631                struct iio_chan_spec const *chan,
0632                int *val,
0633                int *val2,
0634                long m)
0635 {
0636     struct ad9523_state *st = iio_priv(indio_dev);
0637     unsigned int code;
0638     int ret;
0639 
0640     mutex_lock(&st->lock);
0641     ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
0642     mutex_unlock(&st->lock);
0643 
0644     if (ret < 0)
0645         return ret;
0646 
0647     switch (m) {
0648     case IIO_CHAN_INFO_RAW:
0649         *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
0650         return IIO_VAL_INT;
0651     case IIO_CHAN_INFO_FREQUENCY:
0652         *val = st->vco_out_freq[st->vco_out_map[chan->channel]] /
0653             AD9523_CLK_DIST_DIV_REV(ret);
0654         return IIO_VAL_INT;
0655     case IIO_CHAN_INFO_PHASE:
0656         code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
0657             AD9523_CLK_DIST_DIV_REV(ret);
0658         *val = code / 1000000;
0659         *val2 = code % 1000000;
0660         return IIO_VAL_INT_PLUS_MICRO;
0661     default:
0662         return -EINVAL;
0663     }
0664 };
0665 
0666 static int ad9523_write_raw(struct iio_dev *indio_dev,
0667                 struct iio_chan_spec const *chan,
0668                 int val,
0669                 int val2,
0670                 long mask)
0671 {
0672     struct ad9523_state *st = iio_priv(indio_dev);
0673     unsigned int reg;
0674     int ret, tmp, code;
0675 
0676     mutex_lock(&st->lock);
0677     ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
0678     if (ret < 0)
0679         goto out;
0680 
0681     reg = ret;
0682 
0683     switch (mask) {
0684     case IIO_CHAN_INFO_RAW:
0685         if (val)
0686             reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN;
0687         else
0688             reg |= AD9523_CLK_DIST_PWR_DOWN_EN;
0689         break;
0690     case IIO_CHAN_INFO_FREQUENCY:
0691         if (val <= 0) {
0692             ret = -EINVAL;
0693             goto out;
0694         }
0695         ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
0696         if (ret < 0)
0697             goto out;
0698         tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val;
0699         tmp = clamp(tmp, 1, 1024);
0700         reg &= ~(0x3FF << 8);
0701         reg |= AD9523_CLK_DIST_DIV(tmp);
0702         break;
0703     case IIO_CHAN_INFO_PHASE:
0704         code = val * 1000000 + val2 % 1000000;
0705         tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
0706         tmp = clamp(tmp, 0, 63);
0707         reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0);
0708         reg |= AD9523_CLK_DIST_DIV_PHASE(tmp);
0709         break;
0710     default:
0711         ret = -EINVAL;
0712         goto out;
0713     }
0714 
0715     ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
0716                reg);
0717     if (ret < 0)
0718         goto out;
0719 
0720     ad9523_io_update(indio_dev);
0721 out:
0722     mutex_unlock(&st->lock);
0723     return ret;
0724 }
0725 
0726 static int ad9523_reg_access(struct iio_dev *indio_dev,
0727                   unsigned int reg, unsigned int writeval,
0728                   unsigned int *readval)
0729 {
0730     struct ad9523_state *st = iio_priv(indio_dev);
0731     int ret;
0732 
0733     mutex_lock(&st->lock);
0734     if (readval == NULL) {
0735         ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
0736         ad9523_io_update(indio_dev);
0737     } else {
0738         ret = ad9523_read(indio_dev, reg | AD9523_R1B);
0739         if (ret < 0)
0740             goto out_unlock;
0741         *readval = ret;
0742         ret = 0;
0743     }
0744 
0745 out_unlock:
0746     mutex_unlock(&st->lock);
0747 
0748     return ret;
0749 }
0750 
0751 static const struct iio_info ad9523_info = {
0752     .read_raw = &ad9523_read_raw,
0753     .write_raw = &ad9523_write_raw,
0754     .debugfs_reg_access = &ad9523_reg_access,
0755     .attrs = &ad9523_attribute_group,
0756 };
0757 
0758 static int ad9523_setup(struct iio_dev *indio_dev)
0759 {
0760     struct ad9523_state *st = iio_priv(indio_dev);
0761     struct ad9523_platform_data *pdata = st->pdata;
0762     struct ad9523_channel_spec *chan;
0763     unsigned long active_mask = 0;
0764     int ret, i;
0765 
0766     ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
0767                AD9523_SER_CONF_SOFT_RESET |
0768               (st->spi->mode & SPI_3WIRE ? 0 :
0769               AD9523_SER_CONF_SDO_ACTIVE));
0770     if (ret < 0)
0771         return ret;
0772 
0773     ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
0774               AD9523_READBACK_CTRL_READ_BUFFERED);
0775     if (ret < 0)
0776         return ret;
0777 
0778     ret = ad9523_io_update(indio_dev);
0779     if (ret < 0)
0780         return ret;
0781 
0782     /*
0783      * PLL1 Setup
0784      */
0785     ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
0786         pdata->refa_r_div);
0787     if (ret < 0)
0788         return ret;
0789 
0790     ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
0791         pdata->refb_r_div);
0792     if (ret < 0)
0793         return ret;
0794 
0795     ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
0796         pdata->pll1_feedback_div);
0797     if (ret < 0)
0798         return ret;
0799 
0800     ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
0801         AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->
0802             pll1_charge_pump_current_nA) |
0803         AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL |
0804         AD9523_PLL1_BACKLASH_PW_MIN);
0805     if (ret < 0)
0806         return ret;
0807 
0808     ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
0809         AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) |
0810         AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) |
0811         AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) |
0812         AD_IF(osc_in_cmos_neg_inp_en,
0813               AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) |
0814         AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) |
0815         AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN));
0816     if (ret < 0)
0817         return ret;
0818 
0819     ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
0820         AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) |
0821         AD_IF(zd_in_cmos_neg_inp_en,
0822               AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) |
0823         AD_IF(zero_delay_mode_internal_en,
0824               AD9523_PLL1_ZERO_DELAY_MODE_INT) |
0825         AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) |
0826         AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) |
0827         AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN));
0828     if (ret < 0)
0829         return ret;
0830 
0831     ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
0832         AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN |
0833         AD9523_PLL1_REF_MODE(pdata->ref_mode));
0834     if (ret < 0)
0835         return ret;
0836 
0837     ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
0838         AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero));
0839     if (ret < 0)
0840         return ret;
0841     /*
0842      * PLL2 Setup
0843      */
0844 
0845     ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
0846         AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->
0847             pll2_charge_pump_current_nA));
0848     if (ret < 0)
0849         return ret;
0850 
0851     ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
0852         AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) |
0853         AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt));
0854     if (ret < 0)
0855         return ret;
0856 
0857     ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
0858         AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL |
0859         AD9523_PLL2_BACKLASH_CTRL_EN |
0860         AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN));
0861     if (ret < 0)
0862         return ret;
0863 
0864     st->vco_freq = div_u64((unsigned long long)pdata->vcxo_freq *
0865                    (pdata->pll2_freq_doubler_en ? 2 : 1) *
0866                    AD9523_PLL2_FB_NDIV(pdata->pll2_ndiv_a_cnt,
0867                            pdata->pll2_ndiv_b_cnt),
0868                    pdata->pll2_r2_div);
0869 
0870     ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
0871         AD9523_PLL2_VCO_CALIBRATE);
0872     if (ret < 0)
0873         return ret;
0874 
0875     ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
0876         AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_div_m1) |
0877         AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_div_m2) |
0878         AD_IFE(pll2_vco_div_m1, 0,
0879                AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
0880         AD_IFE(pll2_vco_div_m2, 0,
0881                AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
0882     if (ret < 0)
0883         return ret;
0884 
0885     if (pdata->pll2_vco_div_m1)
0886         st->vco_out_freq[AD9523_VCO1] =
0887             st->vco_freq / pdata->pll2_vco_div_m1;
0888 
0889     if (pdata->pll2_vco_div_m2)
0890         st->vco_out_freq[AD9523_VCO2] =
0891             st->vco_freq / pdata->pll2_vco_div_m2;
0892 
0893     st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
0894 
0895     ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
0896         AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div));
0897     if (ret < 0)
0898         return ret;
0899 
0900     ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
0901         AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) |
0902         AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) |
0903         AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) |
0904         AD_IF(rzero_bypass_en,
0905               AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN));
0906     if (ret < 0)
0907         return ret;
0908 
0909     for (i = 0; i < pdata->num_channels; i++) {
0910         chan = &pdata->channels[i];
0911         if (chan->channel_num < AD9523_NUM_CHAN) {
0912             __set_bit(chan->channel_num, &active_mask);
0913             ret = ad9523_write(indio_dev,
0914                 AD9523_CHANNEL_CLOCK_DIST(chan->channel_num),
0915                 AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) |
0916                 AD9523_CLK_DIST_DIV(chan->channel_divider) |
0917                 AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) |
0918                 (chan->sync_ignore_en ?
0919                     AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) |
0920                 (chan->divider_output_invert_en ?
0921                     AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) |
0922                 (chan->low_power_mode_en ?
0923                     AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) |
0924                 (chan->output_dis ?
0925                     AD9523_CLK_DIST_PWR_DOWN_EN : 0));
0926             if (ret < 0)
0927                 return ret;
0928 
0929             ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
0930                        chan->use_alt_clock_src);
0931             if (ret < 0)
0932                 return ret;
0933 
0934             st->ad9523_channels[i].type = IIO_ALTVOLTAGE;
0935             st->ad9523_channels[i].output = 1;
0936             st->ad9523_channels[i].indexed = 1;
0937             st->ad9523_channels[i].channel = chan->channel_num;
0938             st->ad9523_channels[i].extend_name =
0939                 chan->extended_name;
0940             st->ad9523_channels[i].info_mask_separate =
0941                 BIT(IIO_CHAN_INFO_RAW) |
0942                 BIT(IIO_CHAN_INFO_PHASE) |
0943                 BIT(IIO_CHAN_INFO_FREQUENCY);
0944         }
0945     }
0946 
0947     for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) {
0948         ret = ad9523_write(indio_dev,
0949                  AD9523_CHANNEL_CLOCK_DIST(i),
0950                  AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) |
0951                  AD9523_CLK_DIST_PWR_DOWN_EN);
0952         if (ret < 0)
0953             return ret;
0954     }
0955 
0956     ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
0957     if (ret < 0)
0958         return ret;
0959 
0960     ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
0961                AD9523_STATUS_MONITOR_01_PLL12_LOCKED);
0962     if (ret < 0)
0963         return ret;
0964 
0965     ret = ad9523_io_update(indio_dev);
0966     if (ret < 0)
0967         return ret;
0968 
0969     return 0;
0970 }
0971 
0972 static void ad9523_reg_disable(void *data)
0973 {
0974     struct regulator *reg = data;
0975 
0976     regulator_disable(reg);
0977 }
0978 
0979 static int ad9523_probe(struct spi_device *spi)
0980 {
0981     struct ad9523_platform_data *pdata = spi->dev.platform_data;
0982     struct iio_dev *indio_dev;
0983     struct ad9523_state *st;
0984     int ret;
0985 
0986     if (!pdata) {
0987         dev_err(&spi->dev, "no platform data?\n");
0988         return -EINVAL;
0989     }
0990 
0991     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0992     if (indio_dev == NULL)
0993         return -ENOMEM;
0994 
0995     st = iio_priv(indio_dev);
0996 
0997     mutex_init(&st->lock);
0998 
0999     st->reg = devm_regulator_get(&spi->dev, "vcc");
1000     if (!IS_ERR(st->reg)) {
1001         ret = regulator_enable(st->reg);
1002         if (ret)
1003             return ret;
1004 
1005         ret = devm_add_action_or_reset(&spi->dev, ad9523_reg_disable,
1006                            st->reg);
1007         if (ret)
1008             return ret;
1009     }
1010 
1011     st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
1012         GPIOD_OUT_HIGH);
1013     if (IS_ERR(st->pwrdown_gpio))
1014         return PTR_ERR(st->pwrdown_gpio);
1015 
1016     st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1017         GPIOD_OUT_LOW);
1018     if (IS_ERR(st->reset_gpio))
1019         return PTR_ERR(st->reset_gpio);
1020 
1021     if (st->reset_gpio) {
1022         udelay(1);
1023         gpiod_direction_output(st->reset_gpio, 1);
1024     }
1025 
1026     st->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync",
1027         GPIOD_OUT_HIGH);
1028     if (IS_ERR(st->sync_gpio))
1029         return PTR_ERR(st->sync_gpio);
1030 
1031     spi_set_drvdata(spi, indio_dev);
1032     st->spi = spi;
1033     st->pdata = pdata;
1034 
1035     indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
1036               spi_get_device_id(spi)->name;
1037     indio_dev->info = &ad9523_info;
1038     indio_dev->modes = INDIO_DIRECT_MODE;
1039     indio_dev->channels = st->ad9523_channels;
1040     indio_dev->num_channels = pdata->num_channels;
1041 
1042     ret = ad9523_setup(indio_dev);
1043     if (ret < 0)
1044         return ret;
1045 
1046     return devm_iio_device_register(&spi->dev, indio_dev);
1047 }
1048 
1049 static const struct spi_device_id ad9523_id[] = {
1050     {"ad9523-1", 9523},
1051     {}
1052 };
1053 MODULE_DEVICE_TABLE(spi, ad9523_id);
1054 
1055 static struct spi_driver ad9523_driver = {
1056     .driver = {
1057         .name   = "ad9523",
1058     },
1059     .probe      = ad9523_probe,
1060     .id_table   = ad9523_id,
1061 };
1062 module_spi_driver(ad9523_driver);
1063 
1064 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1065 MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL");
1066 MODULE_LICENSE("GPL v2");
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