iio/dac/stm32-dac.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * This file is part of STM32 DAC driver
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Authors: Amelie Delaunay <amelie.delaunay@st.com>
0007  *      Fabrice Gasnier <fabrice.gasnier@st.com>
0008  */
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/delay.h>
0012 #include <linux/iio/iio.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/of.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/string_helpers.h>
0020
0021 #include "stm32-dac-core.h"
0022
0023 #define STM32_DAC_CHANNEL_1     1
0024 #define STM32_DAC_CHANNEL_2     2
0025 #define STM32_DAC_IS_CHAN_1(ch)     ((ch) & STM32_DAC_CHANNEL_1)
0026
0027 #define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000
0028
0029 /**
0030  * struct stm32_dac - private data of DAC driver
0031  * @common:     reference to DAC common data
0032  * @lock:       lock to protect against potential races when reading
0033  *          and update CR, to keep it in sync with pm_runtime
0034  */
0035 struct stm32_dac {
0036     struct stm32_dac_common *common;
0037     struct mutex        lock;
0038 };
0039
0040 static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
0041 {
0042     struct stm32_dac *dac = iio_priv(indio_dev);
0043     u32 en, val;
0044     int ret;
0045
0046     ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
0047     if (ret < 0)
0048         return ret;
0049     if (STM32_DAC_IS_CHAN_1(channel))
0050         en = FIELD_GET(STM32_DAC_CR_EN1, val);
0051     else
0052         en = FIELD_GET(STM32_DAC_CR_EN2, val);
0053
0054     return !!en;
0055 }
0056
0057 static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
0058                       bool enable)
0059 {
0060     struct stm32_dac *dac = iio_priv(indio_dev);
0061     struct device *dev = indio_dev->dev.parent;
0062     u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
0063     u32 en = enable ? msk : 0;
0064     int ret;
0065
0066     /* already enabled / disabled ? */
0067     mutex_lock(&dac->lock);
0068     ret = stm32_dac_is_enabled(indio_dev, ch);
0069     if (ret < 0 || enable == !!ret) {
0070         mutex_unlock(&dac->lock);
0071         return ret < 0 ? ret : 0;
0072     }
0073
0074     if (enable) {
0075         ret = pm_runtime_resume_and_get(dev);
0076         if (ret < 0) {
0077             mutex_unlock(&dac->lock);
0078             return ret;
0079         }
0080     }
0081
0082     ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
0083     mutex_unlock(&dac->lock);
0084     if (ret < 0) {
0085         dev_err(&indio_dev->dev, "%s failed\n", str_enable_disable(en));
0086         goto err_put_pm;
0087     }
0088
0089     /*
0090      * When HFSEL is set, it is not allowed to write the DHRx register
0091      * during 8 clock cycles after the ENx bit is set. It is not allowed
0092      * to make software/hardware trigger during this period either.
0093      */
0094     if (en && dac->common->hfsel)
0095         udelay(1);
0096
0097     if (!enable) {
0098         pm_runtime_mark_last_busy(dev);
0099         pm_runtime_put_autosuspend(dev);
0100     }
0101
0102     return 0;
0103
0104 err_put_pm:
0105     if (enable) {
0106         pm_runtime_mark_last_busy(dev);
0107         pm_runtime_put_autosuspend(dev);
0108     }
0109
0110     return ret;
0111 }
0112
0113 static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
0114 {
0115     int ret;
0116
0117     if (STM32_DAC_IS_CHAN_1(channel))
0118         ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
0119     else
0120         ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
0121
0122     return ret ? ret : IIO_VAL_INT;
0123 }
0124
0125 static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
0126 {
0127     int ret;
0128
0129     if (STM32_DAC_IS_CHAN_1(channel))
0130         ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
0131     else
0132         ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
0133
0134     return ret;
0135 }
0136
0137 static int stm32_dac_read_raw(struct iio_dev *indio_dev,
0138                   struct iio_chan_spec const *chan,
0139                   int *val, int *val2, long mask)
0140 {
0141     struct stm32_dac *dac = iio_priv(indio_dev);
0142
0143     switch (mask) {
0144     case IIO_CHAN_INFO_RAW:
0145         return stm32_dac_get_value(dac, chan->channel, val);
0146     case IIO_CHAN_INFO_SCALE:
0147         *val = dac->common->vref_mv;
0148         *val2 = chan->scan_type.realbits;
0149         return IIO_VAL_FRACTIONAL_LOG2;
0150     default:
0151         return -EINVAL;
0152     }
0153 }
0154
0155 static int stm32_dac_write_raw(struct iio_dev *indio_dev,
0156                    struct iio_chan_spec const *chan,
0157                    int val, int val2, long mask)
0158 {
0159     struct stm32_dac *dac = iio_priv(indio_dev);
0160
0161     switch (mask) {
0162     case IIO_CHAN_INFO_RAW:
0163         return stm32_dac_set_value(dac, chan->channel, val);
0164     default:
0165         return -EINVAL;
0166     }
0167 }
0168
0169 static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
0170                     unsigned reg, unsigned writeval,
0171                     unsigned *readval)
0172 {
0173     struct stm32_dac *dac = iio_priv(indio_dev);
0174
0175     if (!readval)
0176         return regmap_write(dac->common->regmap, reg, writeval);
0177     else
0178         return regmap_read(dac->common->regmap, reg, readval);
0179 }
0180
0181 static const struct iio_info stm32_dac_iio_info = {
0182     .read_raw = stm32_dac_read_raw,
0183     .write_raw = stm32_dac_write_raw,
0184     .debugfs_reg_access = stm32_dac_debugfs_reg_access,
0185 };
0186
0187 static const char * const stm32_dac_powerdown_modes[] = {
0188     "three_state",
0189 };
0190
0191 static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
0192                     const struct iio_chan_spec *chan)
0193 {
0194     return 0;
0195 }
0196
0197 static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
0198                     const struct iio_chan_spec *chan,
0199                     unsigned int type)
0200 {
0201     return 0;
0202 }
0203
0204 static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
0205                     uintptr_t private,
0206                     const struct iio_chan_spec *chan,
0207                     char *buf)
0208 {
0209     int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
0210
0211     if (ret < 0)
0212         return ret;
0213
0214     return sysfs_emit(buf, "%d\n", ret ? 0 : 1);
0215 }
0216
0217 static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
0218                      uintptr_t private,
0219                      const struct iio_chan_spec *chan,
0220                      const char *buf, size_t len)
0221 {
0222     bool powerdown;
0223     int ret;
0224
0225     ret = kstrtobool(buf, &powerdown);
0226     if (ret)
0227         return ret;
0228
0229     ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
0230     if (ret)
0231         return ret;
0232
0233     return len;
0234 }
0235
0236 static const struct iio_enum stm32_dac_powerdown_mode_en = {
0237     .items = stm32_dac_powerdown_modes,
0238     .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
0239     .get = stm32_dac_get_powerdown_mode,
0240     .set = stm32_dac_set_powerdown_mode,
0241 };
0242
0243 static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
0244     {
0245         .name = "powerdown",
0246         .read = stm32_dac_read_powerdown,
0247         .write = stm32_dac_write_powerdown,
0248         .shared = IIO_SEPARATE,
0249     },
0250     IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
0251     IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &stm32_dac_powerdown_mode_en),
0252     {},
0253 };
0254
0255 #define STM32_DAC_CHANNEL(chan, name) {         \
0256     .type = IIO_VOLTAGE,                \
0257     .indexed = 1,                   \
0258     .output = 1,                    \
0259     .channel = chan,                \
0260     .info_mask_separate =               \
0261         BIT(IIO_CHAN_INFO_RAW) |        \
0262         BIT(IIO_CHAN_INFO_SCALE),       \
0263     /* scan_index is always 0 as num_channels is 1 */ \
0264     .scan_type = {                  \
0265         .sign = 'u',                \
0266         .realbits = 12,             \
0267         .storagebits = 16,          \
0268     },                      \
0269     .datasheet_name = name,             \
0270     .ext_info = stm32_dac_ext_info          \
0271 }
0272
0273 static const struct iio_chan_spec stm32_dac_channels[] = {
0274     STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
0275     STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
0276 };
0277
0278 static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
0279 {
0280     struct device_node *np = indio_dev->dev.of_node;
0281     unsigned int i;
0282     u32 channel;
0283     int ret;
0284
0285     ret = of_property_read_u32(np, "reg", &channel);
0286     if (ret) {
0287         dev_err(&indio_dev->dev, "Failed to read reg property\n");
0288         return ret;
0289     }
0290
0291     for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
0292         if (stm32_dac_channels[i].channel == channel)
0293             break;
0294     }
0295     if (i >= ARRAY_SIZE(stm32_dac_channels)) {
0296         dev_err(&indio_dev->dev, "Invalid reg property\n");
0297         return -EINVAL;
0298     }
0299
0300     indio_dev->channels = &stm32_dac_channels[i];
0301     /*
0302      * Expose only one channel here, as they can be used independently,
0303      * with separate trigger. Then separate IIO devices are instantiated
0304      * to manage this.
0305      */
0306     indio_dev->num_channels = 1;
0307
0308     return 0;
0309 };
0310
0311 static int stm32_dac_probe(struct platform_device *pdev)
0312 {
0313     struct device_node *np = pdev->dev.of_node;
0314     struct device *dev = &pdev->dev;
0315     struct iio_dev *indio_dev;
0316     struct stm32_dac *dac;
0317     int ret;
0318
0319     if (!np)
0320         return -ENODEV;
0321
0322     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
0323     if (!indio_dev)
0324         return -ENOMEM;
0325     platform_set_drvdata(pdev, indio_dev);
0326
0327     dac = iio_priv(indio_dev);
0328     dac->common = dev_get_drvdata(pdev->dev.parent);
0329     indio_dev->name = dev_name(&pdev->dev);
0330     indio_dev->dev.of_node = pdev->dev.of_node;
0331     indio_dev->info = &stm32_dac_iio_info;
0332     indio_dev->modes = INDIO_DIRECT_MODE;
0333
0334     mutex_init(&dac->lock);
0335
0336     ret = stm32_dac_chan_of_init(indio_dev);
0337     if (ret < 0)
0338         return ret;
0339
0340     /* Get stm32-dac-core PM online */
0341     pm_runtime_get_noresume(dev);
0342     pm_runtime_set_active(dev);
0343     pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
0344     pm_runtime_use_autosuspend(dev);
0345     pm_runtime_enable(dev);
0346
0347     ret = iio_device_register(indio_dev);
0348     if (ret)
0349         goto err_pm_put;
0350
0351     pm_runtime_mark_last_busy(dev);
0352     pm_runtime_put_autosuspend(dev);
0353
0354     return 0;
0355
0356 err_pm_put:
0357     pm_runtime_disable(dev);
0358     pm_runtime_set_suspended(dev);
0359     pm_runtime_put_noidle(dev);
0360
0361     return ret;
0362 }
0363
0364 static int stm32_dac_remove(struct platform_device *pdev)
0365 {
0366     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0367
0368     pm_runtime_get_sync(&pdev->dev);
0369     iio_device_unregister(indio_dev);
0370     pm_runtime_disable(&pdev->dev);
0371     pm_runtime_set_suspended(&pdev->dev);
0372     pm_runtime_put_noidle(&pdev->dev);
0373
0374     return 0;
0375 }
0376
0377 static int stm32_dac_suspend(struct device *dev)
0378 {
0379     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0380     int channel = indio_dev->channels[0].channel;
0381     int ret;
0382
0383     /* Ensure DAC is disabled before suspend */
0384     ret = stm32_dac_is_enabled(indio_dev, channel);
0385     if (ret)
0386         return ret < 0 ? ret : -EBUSY;
0387
0388     return pm_runtime_force_suspend(dev);
0389 }
0390
0391 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dac_pm_ops, stm32_dac_suspend,
0392                 pm_runtime_force_resume);
0393
0394 static const struct of_device_id stm32_dac_of_match[] = {
0395     { .compatible = "st,stm32-dac", },
0396     {},
0397 };
0398 MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
0399
0400 static struct platform_driver stm32_dac_driver = {
0401     .probe = stm32_dac_probe,
0402     .remove = stm32_dac_remove,
0403     .driver = {
0404         .name = "stm32-dac",
0405         .of_match_table = stm32_dac_of_match,
0406         .pm = pm_sleep_ptr(&stm32_dac_pm_ops),
0407     },
0408 };
0409 module_platform_driver(stm32_dac_driver);
0410
0411 MODULE_ALIAS("platform:stm32-dac");
0412 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
0413 MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
0414 MODULE_LICENSE("GPL v2");