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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD7293 driver
0004  *
0005  * Copyright 2021 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/bits.h>
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/iio/iio.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/module.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/spi/spi.h>
0018 
0019 #include <asm/unaligned.h>
0020 
0021 #define AD7293_R1B              BIT(16)
0022 #define AD7293_R2B              BIT(17)
0023 #define AD7293_PAGE_ADDR_MSK            GENMASK(15, 8)
0024 #define AD7293_PAGE(x)              FIELD_PREP(AD7293_PAGE_ADDR_MSK, x)
0025 
0026 /* AD7293 Register Map Common */
0027 #define AD7293_REG_NO_OP            (AD7293_R1B | AD7293_PAGE(0x0) | 0x0)
0028 #define AD7293_REG_PAGE_SELECT          (AD7293_R1B | AD7293_PAGE(0x0) | 0x1)
0029 #define AD7293_REG_CONV_CMD         (AD7293_R2B | AD7293_PAGE(0x0) | 0x2)
0030 #define AD7293_REG_RESULT           (AD7293_R1B | AD7293_PAGE(0x0) | 0x3)
0031 #define AD7293_REG_DAC_EN           (AD7293_R1B | AD7293_PAGE(0x0) | 0x4)
0032 #define AD7293_REG_DEVICE_ID            (AD7293_R2B | AD7293_PAGE(0x0) | 0xC)
0033 #define AD7293_REG_SOFT_RESET           (AD7293_R2B | AD7293_PAGE(0x0) | 0xF)
0034 
0035 /* AD7293 Register Map Page 0x0 */
0036 #define AD7293_REG_VIN0             (AD7293_R2B | AD7293_PAGE(0x0) | 0x10)
0037 #define AD7293_REG_VIN1             (AD7293_R2B | AD7293_PAGE(0x0) | 0x11)
0038 #define AD7293_REG_VIN2             (AD7293_R2B | AD7293_PAGE(0x0) | 0x12)
0039 #define AD7293_REG_VIN3             (AD7293_R2B | AD7293_PAGE(0x0) | 0x13)
0040 #define AD7293_REG_TSENSE_INT           (AD7293_R2B | AD7293_PAGE(0x0) | 0x20)
0041 #define AD7293_REG_TSENSE_D0            (AD7293_R2B | AD7293_PAGE(0x0) | 0x21)
0042 #define AD7293_REG_TSENSE_D1            (AD7293_R2B | AD7293_PAGE(0x0) | 0x22)
0043 #define AD7293_REG_ISENSE_0         (AD7293_R2B | AD7293_PAGE(0x0) | 0x28)
0044 #define AD7293_REG_ISENSE_1         (AD7293_R2B | AD7293_PAGE(0x0) | 0x29)
0045 #define AD7293_REG_ISENSE_2         (AD7293_R2B | AD7293_PAGE(0x0) | 0x2A)
0046 #define AD7293_REG_ISENSE_3         (AD7293_R2B | AD7293_PAGE(0x0) | 0x2B)
0047 #define AD7293_REG_UNI_VOUT0            (AD7293_R2B | AD7293_PAGE(0x0) | 0x30)
0048 #define AD7293_REG_UNI_VOUT1            (AD7293_R2B | AD7293_PAGE(0x0) | 0x31)
0049 #define AD7293_REG_UNI_VOUT2            (AD7293_R2B | AD7293_PAGE(0x0) | 0x32)
0050 #define AD7293_REG_UNI_VOUT3            (AD7293_R2B | AD7293_PAGE(0x0) | 0x33)
0051 #define AD7293_REG_BI_VOUT0         (AD7293_R2B | AD7293_PAGE(0x0) | 0x34)
0052 #define AD7293_REG_BI_VOUT1         (AD7293_R2B | AD7293_PAGE(0x0) | 0x35)
0053 #define AD7293_REG_BI_VOUT2         (AD7293_R2B | AD7293_PAGE(0x0) | 0x36)
0054 #define AD7293_REG_BI_VOUT3         (AD7293_R2B | AD7293_PAGE(0x0) | 0x37)
0055 
0056 /* AD7293 Register Map Page 0x2 */
0057 #define AD7293_REG_DIGITAL_OUT_EN       (AD7293_R2B | AD7293_PAGE(0x2) | 0x11)
0058 #define AD7293_REG_DIGITAL_INOUT_FUNC       (AD7293_R2B | AD7293_PAGE(0x2) | 0x12)
0059 #define AD7293_REG_DIGITAL_FUNC_POL     (AD7293_R2B | AD7293_PAGE(0x2) | 0x13)
0060 #define AD7293_REG_GENERAL          (AD7293_R2B | AD7293_PAGE(0x2) | 0x14)
0061 #define AD7293_REG_VINX_RANGE0          (AD7293_R2B | AD7293_PAGE(0x2) | 0x15)
0062 #define AD7293_REG_VINX_RANGE1          (AD7293_R2B | AD7293_PAGE(0x2) | 0x16)
0063 #define AD7293_REG_VINX_DIFF_SE         (AD7293_R2B | AD7293_PAGE(0x2) | 0x17)
0064 #define AD7293_REG_VINX_FILTER          (AD7293_R2B | AD7293_PAGE(0x2) | 0x18)
0065 #define AD7293_REG_BG_EN            (AD7293_R2B | AD7293_PAGE(0x2) | 0x19)
0066 #define AD7293_REG_CONV_DELAY           (AD7293_R2B | AD7293_PAGE(0x2) | 0x1A)
0067 #define AD7293_REG_TSENSE_BG_EN         (AD7293_R2B | AD7293_PAGE(0x2) | 0x1B)
0068 #define AD7293_REG_ISENSE_BG_EN         (AD7293_R2B | AD7293_PAGE(0x2) | 0x1C)
0069 #define AD7293_REG_ISENSE_GAIN          (AD7293_R2B | AD7293_PAGE(0x2) | 0x1D)
0070 #define AD7293_REG_DAC_SNOOZE_O         (AD7293_R2B | AD7293_PAGE(0x2) | 0x1F)
0071 #define AD7293_REG_DAC_SNOOZE_1         (AD7293_R2B | AD7293_PAGE(0x2) | 0x20)
0072 #define AD7293_REG_RSX_MON_BG_EN        (AD7293_R2B | AD7293_PAGE(0x2) | 0x23)
0073 #define AD7293_REG_INTEGR_CL            (AD7293_R2B | AD7293_PAGE(0x2) | 0x28)
0074 #define AD7293_REG_PA_ON_CTRL           (AD7293_R2B | AD7293_PAGE(0x2) | 0x29)
0075 #define AD7293_REG_RAMP_TIME_0          (AD7293_R2B | AD7293_PAGE(0x2) | 0x2A)
0076 #define AD7293_REG_RAMP_TIME_1          (AD7293_R2B | AD7293_PAGE(0x2) | 0x2B)
0077 #define AD7293_REG_RAMP_TIME_2          (AD7293_R2B | AD7293_PAGE(0x2) | 0x2C)
0078 #define AD7293_REG_RAMP_TIME_3          (AD7293_R2B | AD7293_PAGE(0x2) | 0x2D)
0079 #define AD7293_REG_CL_FR_IT         (AD7293_R2B | AD7293_PAGE(0x2) | 0x2E)
0080 #define AD7293_REG_INTX_AVSS_AVDD       (AD7293_R2B | AD7293_PAGE(0x2) | 0x2F)
0081 
0082 /* AD7293 Register Map Page 0x3 */
0083 #define AD7293_REG_VINX_SEQ         (AD7293_R2B | AD7293_PAGE(0x3) | 0x10)
0084 #define AD7293_REG_ISENSEX_TSENSEX_SEQ      (AD7293_R2B | AD7293_PAGE(0x3) | 0x11)
0085 #define AD7293_REG_RSX_MON_BI_VOUTX_SEQ     (AD7293_R2B | AD7293_PAGE(0x3) | 0x12)
0086 
0087 /* AD7293 Register Map Page 0xE */
0088 #define AD7293_REG_VIN0_OFFSET          (AD7293_R1B | AD7293_PAGE(0xE) | 0x10)
0089 #define AD7293_REG_VIN1_OFFSET          (AD7293_R1B | AD7293_PAGE(0xE) | 0x11)
0090 #define AD7293_REG_VIN2_OFFSET          (AD7293_R1B | AD7293_PAGE(0xE) | 0x12)
0091 #define AD7293_REG_VIN3_OFFSET          (AD7293_R1B | AD7293_PAGE(0xE) | 0x13)
0092 #define AD7293_REG_TSENSE_INT_OFFSET        (AD7293_R1B | AD7293_PAGE(0xE) | 0x20)
0093 #define AD7293_REG_TSENSE_D0_OFFSET     (AD7293_R1B | AD7293_PAGE(0xE) | 0x21)
0094 #define AD7293_REG_TSENSE_D1_OFFSET     (AD7293_R1B | AD7293_PAGE(0xE) | 0x22)
0095 #define AD7293_REG_ISENSE0_OFFSET       (AD7293_R1B | AD7293_PAGE(0xE) | 0x28)
0096 #define AD7293_REG_ISENSE1_OFFSET       (AD7293_R1B | AD7293_PAGE(0xE) | 0x29)
0097 #define AD7293_REG_ISENSE2_OFFSET       (AD7293_R1B | AD7293_PAGE(0xE) | 0x2A)
0098 #define AD7293_REG_ISENSE3_OFFSET       (AD7293_R1B | AD7293_PAGE(0xE) | 0x2B)
0099 #define AD7293_REG_UNI_VOUT0_OFFSET     (AD7293_R1B | AD7293_PAGE(0xE) | 0x30)
0100 #define AD7293_REG_UNI_VOUT1_OFFSET     (AD7293_R1B | AD7293_PAGE(0xE) | 0x31)
0101 #define AD7293_REG_UNI_VOUT2_OFFSET     (AD7293_R1B | AD7293_PAGE(0xE) | 0x32)
0102 #define AD7293_REG_UNI_VOUT3_OFFSET     (AD7293_R1B | AD7293_PAGE(0xE) | 0x33)
0103 #define AD7293_REG_BI_VOUT0_OFFSET      (AD7293_R1B | AD7293_PAGE(0xE) | 0x34)
0104 #define AD7293_REG_BI_VOUT1_OFFSET      (AD7293_R1B | AD7293_PAGE(0xE) | 0x35)
0105 #define AD7293_REG_BI_VOUT2_OFFSET      (AD7293_R1B | AD7293_PAGE(0xE) | 0x36)
0106 #define AD7293_REG_BI_VOUT3_OFFSET      (AD7293_R1B | AD7293_PAGE(0xE) | 0x37)
0107 
0108 /* AD7293 Miscellaneous Definitions */
0109 #define AD7293_READ             BIT(7)
0110 #define AD7293_TRANSF_LEN_MSK           GENMASK(17, 16)
0111 
0112 #define AD7293_REG_ADDR_MSK         GENMASK(7, 0)
0113 #define AD7293_REG_VOUT_OFFSET_MSK      GENMASK(5, 4)
0114 #define AD7293_REG_DATA_RAW_MSK         GENMASK(15, 4)
0115 #define AD7293_REG_VINX_RANGE_GET_CH_MSK(x, ch) (((x) >> (ch)) & 0x1)
0116 #define AD7293_REG_VINX_RANGE_SET_CH_MSK(x, ch) (((x) & 0x1) << (ch))
0117 #define AD7293_CHIP_ID              0x18
0118 
0119 enum ad7293_ch_type {
0120     AD7293_ADC_VINX,
0121     AD7293_ADC_TSENSE,
0122     AD7293_ADC_ISENSE,
0123     AD7293_DAC,
0124 };
0125 
0126 enum ad7293_max_offset {
0127     AD7293_TSENSE_MIN_OFFSET_CH = 4,
0128     AD7293_ISENSE_MIN_OFFSET_CH = 7,
0129     AD7293_VOUT_MIN_OFFSET_CH = 11,
0130     AD7293_VOUT_MAX_OFFSET_CH = 18,
0131 };
0132 
0133 static const int dac_offset_table[] = {0, 1, 2};
0134 
0135 static const int isense_gain_table[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
0136 
0137 static const int adc_range_table[] = {0, 1, 2, 3};
0138 
0139 struct ad7293_state {
0140     struct spi_device *spi;
0141     /* Protect against concurrent accesses to the device, page selection and data content */
0142     struct mutex lock;
0143     struct gpio_desc *gpio_reset;
0144     struct regulator *reg_avdd;
0145     struct regulator *reg_vdrive;
0146     u8 page_select;
0147     u8 data[3] __aligned(IIO_DMA_MINALIGN);
0148 };
0149 
0150 static int ad7293_page_select(struct ad7293_state *st, unsigned int reg)
0151 {
0152     int ret;
0153 
0154     if (st->page_select != FIELD_GET(AD7293_PAGE_ADDR_MSK, reg)) {
0155         st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, AD7293_REG_PAGE_SELECT);
0156         st->data[1] = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
0157 
0158         ret = spi_write(st->spi, &st->data[0], 2);
0159         if (ret)
0160             return ret;
0161 
0162         st->page_select = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
0163     }
0164 
0165     return 0;
0166 }
0167 
0168 static int __ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
0169                  u16 *val)
0170 {
0171     int ret;
0172     unsigned int length;
0173     struct spi_transfer t = {0};
0174 
0175     length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
0176 
0177     ret = ad7293_page_select(st, reg);
0178     if (ret)
0179         return ret;
0180 
0181     st->data[0] = AD7293_READ | FIELD_GET(AD7293_REG_ADDR_MSK, reg);
0182     st->data[1] = 0x0;
0183     st->data[2] = 0x0;
0184 
0185     t.tx_buf = &st->data[0];
0186     t.rx_buf = &st->data[0];
0187     t.len = length + 1;
0188 
0189     ret = spi_sync_transfer(st->spi, &t, 1);
0190     if (ret)
0191         return ret;
0192 
0193     if (length == 1)
0194         *val = st->data[1];
0195     else
0196         *val = get_unaligned_be16(&st->data[1]);
0197 
0198     return 0;
0199 }
0200 
0201 static int ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
0202                u16 *val)
0203 {
0204     int ret;
0205 
0206     mutex_lock(&st->lock);
0207     ret = __ad7293_spi_read(st, reg, val);
0208     mutex_unlock(&st->lock);
0209 
0210     return ret;
0211 }
0212 
0213 static int __ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
0214                   u16 val)
0215 {
0216     int ret;
0217     unsigned int length;
0218 
0219     length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
0220 
0221     ret = ad7293_page_select(st, reg);
0222     if (ret)
0223         return ret;
0224 
0225     st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, reg);
0226 
0227     if (length == 1)
0228         st->data[1] = val;
0229     else
0230         put_unaligned_be16(val, &st->data[1]);
0231 
0232     return spi_write(st->spi, &st->data[0], length + 1);
0233 }
0234 
0235 static int ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
0236                 u16 val)
0237 {
0238     int ret;
0239 
0240     mutex_lock(&st->lock);
0241     ret = __ad7293_spi_write(st, reg, val);
0242     mutex_unlock(&st->lock);
0243 
0244     return ret;
0245 }
0246 
0247 static int __ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
0248                     u16 mask, u16 val)
0249 {
0250     int ret;
0251     u16 data, temp;
0252 
0253     ret = __ad7293_spi_read(st, reg, &data);
0254     if (ret)
0255         return ret;
0256 
0257     temp = (data & ~mask) | (val & mask);
0258 
0259     return __ad7293_spi_write(st, reg, temp);
0260 }
0261 
0262 static int ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
0263                   u16 mask, u16 val)
0264 {
0265     int ret;
0266 
0267     mutex_lock(&st->lock);
0268     ret = __ad7293_spi_update_bits(st, reg, mask, val);
0269     mutex_unlock(&st->lock);
0270 
0271     return ret;
0272 }
0273 
0274 static int ad7293_adc_get_scale(struct ad7293_state *st, unsigned int ch,
0275                 u16 *range)
0276 {
0277     int ret;
0278     u16 data;
0279 
0280     mutex_lock(&st->lock);
0281 
0282     ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE1, &data);
0283     if (ret)
0284         goto exit;
0285 
0286     *range = AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch);
0287 
0288     ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE0, &data);
0289     if (ret)
0290         goto exit;
0291 
0292     *range |= AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch) << 1;
0293 
0294 exit:
0295     mutex_unlock(&st->lock);
0296 
0297     return ret;
0298 }
0299 
0300 static int ad7293_adc_set_scale(struct ad7293_state *st, unsigned int ch,
0301                 u16 range)
0302 {
0303     int ret;
0304     unsigned int ch_msk = BIT(ch);
0305 
0306     mutex_lock(&st->lock);
0307     ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE1, ch_msk,
0308                        AD7293_REG_VINX_RANGE_SET_CH_MSK(range, ch));
0309     if (ret)
0310         goto exit;
0311 
0312     ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE0, ch_msk,
0313                        AD7293_REG_VINX_RANGE_SET_CH_MSK((range >> 1), ch));
0314 
0315 exit:
0316     mutex_unlock(&st->lock);
0317 
0318     return ret;
0319 }
0320 
0321 static int ad7293_get_offset(struct ad7293_state *st, unsigned int ch,
0322                  u16 *offset)
0323 {
0324     if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
0325         return ad7293_spi_read(st, AD7293_REG_VIN0_OFFSET + ch, offset);
0326     else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
0327         return ad7293_spi_read(st, AD7293_REG_TSENSE_INT_OFFSET + (ch - 4), offset);
0328     else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
0329         return ad7293_spi_read(st, AD7293_REG_ISENSE0_OFFSET + (ch - 7), offset);
0330     else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
0331         return ad7293_spi_read(st, AD7293_REG_UNI_VOUT0_OFFSET + (ch - 11), offset);
0332 
0333     return -EINVAL;
0334 }
0335 
0336 static int ad7293_set_offset(struct ad7293_state *st, unsigned int ch,
0337                  u16 offset)
0338 {
0339     if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
0340         return ad7293_spi_write(st, AD7293_REG_VIN0_OFFSET + ch,
0341                     offset);
0342     else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
0343         return ad7293_spi_write(st,
0344                     AD7293_REG_TSENSE_INT_OFFSET +
0345                     (ch - AD7293_TSENSE_MIN_OFFSET_CH),
0346                     offset);
0347     else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
0348         return ad7293_spi_write(st,
0349                     AD7293_REG_ISENSE0_OFFSET +
0350                     (ch - AD7293_ISENSE_MIN_OFFSET_CH),
0351                     offset);
0352     else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
0353         return ad7293_spi_update_bits(st,
0354                           AD7293_REG_UNI_VOUT0_OFFSET +
0355                           (ch - AD7293_VOUT_MIN_OFFSET_CH),
0356                           AD7293_REG_VOUT_OFFSET_MSK,
0357                           FIELD_PREP(AD7293_REG_VOUT_OFFSET_MSK, offset));
0358 
0359     return -EINVAL;
0360 }
0361 
0362 static int ad7293_isense_set_scale(struct ad7293_state *st, unsigned int ch,
0363                    u16 gain)
0364 {
0365     unsigned int ch_msk = (0xf << (4 * ch));
0366 
0367     return ad7293_spi_update_bits(st, AD7293_REG_ISENSE_GAIN, ch_msk,
0368                       gain << (4 * ch));
0369 }
0370 
0371 static int ad7293_isense_get_scale(struct ad7293_state *st, unsigned int ch,
0372                    u16 *gain)
0373 {
0374     int ret;
0375 
0376     ret = ad7293_spi_read(st, AD7293_REG_ISENSE_GAIN, gain);
0377     if (ret)
0378         return ret;
0379 
0380     *gain = (*gain >> (4 * ch)) & 0xf;
0381 
0382     return ret;
0383 }
0384 
0385 static int ad7293_dac_write_raw(struct ad7293_state *st, unsigned int ch,
0386                 u16 raw)
0387 {
0388     int ret;
0389 
0390     mutex_lock(&st->lock);
0391 
0392     ret = __ad7293_spi_update_bits(st, AD7293_REG_DAC_EN, BIT(ch), BIT(ch));
0393     if (ret)
0394         goto exit;
0395 
0396     ret =  __ad7293_spi_write(st, AD7293_REG_UNI_VOUT0 + ch,
0397                   FIELD_PREP(AD7293_REG_DATA_RAW_MSK, raw));
0398 
0399 exit:
0400     mutex_unlock(&st->lock);
0401 
0402     return ret;
0403 }
0404 
0405 static int ad7293_ch_read_raw(struct ad7293_state *st, enum ad7293_ch_type type,
0406                   unsigned int ch, u16 *raw)
0407 {
0408     int ret;
0409     unsigned int reg_wr, reg_rd, data_wr;
0410 
0411     switch (type) {
0412     case AD7293_ADC_VINX:
0413         reg_wr = AD7293_REG_VINX_SEQ;
0414         reg_rd = AD7293_REG_VIN0 + ch;
0415         data_wr = BIT(ch);
0416 
0417         break;
0418     case AD7293_ADC_TSENSE:
0419         reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
0420         reg_rd = AD7293_REG_TSENSE_INT + ch;
0421         data_wr = BIT(ch);
0422 
0423         break;
0424     case AD7293_ADC_ISENSE:
0425         reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
0426         reg_rd = AD7293_REG_ISENSE_0 + ch;
0427         data_wr = BIT(ch) << 8;
0428 
0429         break;
0430     case AD7293_DAC:
0431         reg_rd = AD7293_REG_UNI_VOUT0 + ch;
0432 
0433         break;
0434     default:
0435         return -EINVAL;
0436     }
0437 
0438     mutex_lock(&st->lock);
0439 
0440     if (type != AD7293_DAC) {
0441         if (type == AD7293_ADC_TSENSE) {
0442             ret = __ad7293_spi_write(st, AD7293_REG_TSENSE_BG_EN,
0443                          BIT(ch));
0444             if (ret)
0445                 goto exit;
0446 
0447             usleep_range(9000, 9900);
0448         } else if (type == AD7293_ADC_ISENSE) {
0449             ret = __ad7293_spi_write(st, AD7293_REG_ISENSE_BG_EN,
0450                          BIT(ch));
0451             if (ret)
0452                 goto exit;
0453 
0454             usleep_range(2000, 7000);
0455         }
0456 
0457         ret = __ad7293_spi_write(st, reg_wr, data_wr);
0458         if (ret)
0459             goto exit;
0460 
0461         ret = __ad7293_spi_write(st, AD7293_REG_CONV_CMD, 0x82);
0462         if (ret)
0463             goto exit;
0464     }
0465 
0466     ret = __ad7293_spi_read(st, reg_rd, raw);
0467 
0468     *raw = FIELD_GET(AD7293_REG_DATA_RAW_MSK, *raw);
0469 
0470 exit:
0471     mutex_unlock(&st->lock);
0472 
0473     return ret;
0474 }
0475 
0476 static int ad7293_read_raw(struct iio_dev *indio_dev,
0477                struct iio_chan_spec const *chan,
0478                int *val, int *val2, long info)
0479 {
0480     struct ad7293_state *st = iio_priv(indio_dev);
0481     int ret;
0482     u16 data;
0483 
0484     switch (info) {
0485     case IIO_CHAN_INFO_RAW:
0486         switch (chan->type) {
0487         case IIO_VOLTAGE:
0488             if (chan->output)
0489                 ret =  ad7293_ch_read_raw(st, AD7293_DAC,
0490                               chan->channel, &data);
0491             else
0492                 ret =  ad7293_ch_read_raw(st, AD7293_ADC_VINX,
0493                               chan->channel, &data);
0494 
0495             break;
0496         case IIO_CURRENT:
0497             ret =  ad7293_ch_read_raw(st, AD7293_ADC_ISENSE,
0498                           chan->channel, &data);
0499 
0500             break;
0501         case IIO_TEMP:
0502             ret =  ad7293_ch_read_raw(st, AD7293_ADC_TSENSE,
0503                           chan->channel, &data);
0504 
0505             break;
0506         default:
0507             return -EINVAL;
0508         }
0509 
0510         if (ret)
0511             return ret;
0512 
0513         *val = data;
0514 
0515         return IIO_VAL_INT;
0516     case IIO_CHAN_INFO_OFFSET:
0517         switch (chan->type) {
0518         case IIO_VOLTAGE:
0519             if (chan->output) {
0520                 ret = ad7293_get_offset(st,
0521                             chan->channel + AD7293_VOUT_MIN_OFFSET_CH,
0522                             &data);
0523 
0524                 data = FIELD_GET(AD7293_REG_VOUT_OFFSET_MSK, data);
0525             } else {
0526                 ret = ad7293_get_offset(st, chan->channel, &data);
0527             }
0528 
0529             break;
0530         case IIO_CURRENT:
0531             ret = ad7293_get_offset(st,
0532                         chan->channel + AD7293_ISENSE_MIN_OFFSET_CH,
0533                         &data);
0534 
0535             break;
0536         case IIO_TEMP:
0537             ret = ad7293_get_offset(st,
0538                         chan->channel + AD7293_TSENSE_MIN_OFFSET_CH,
0539                         &data);
0540 
0541             break;
0542         default:
0543             return -EINVAL;
0544         }
0545         if (ret)
0546             return ret;
0547 
0548         *val = data;
0549 
0550         return IIO_VAL_INT;
0551     case IIO_CHAN_INFO_SCALE:
0552         switch (chan->type) {
0553         case IIO_VOLTAGE:
0554             ret = ad7293_adc_get_scale(st, chan->channel, &data);
0555             if (ret)
0556                 return ret;
0557 
0558             *val = data;
0559 
0560             return IIO_VAL_INT;
0561         case IIO_CURRENT:
0562             ret = ad7293_isense_get_scale(st, chan->channel, &data);
0563             if (ret)
0564                 return ret;
0565 
0566             *val = data;
0567 
0568             return IIO_VAL_INT;
0569         case IIO_TEMP:
0570             *val = 1;
0571             *val2 = 8;
0572 
0573             return IIO_VAL_FRACTIONAL;
0574         default:
0575             return -EINVAL;
0576         }
0577     default:
0578         return -EINVAL;
0579     }
0580 }
0581 
0582 static int ad7293_write_raw(struct iio_dev *indio_dev,
0583                 struct iio_chan_spec const *chan,
0584                 int val, int val2, long info)
0585 {
0586     struct ad7293_state *st = iio_priv(indio_dev);
0587 
0588     switch (info) {
0589     case IIO_CHAN_INFO_RAW:
0590         switch (chan->type) {
0591         case IIO_VOLTAGE:
0592             if (!chan->output)
0593                 return -EINVAL;
0594 
0595             return ad7293_dac_write_raw(st, chan->channel, val);
0596         default:
0597             return -EINVAL;
0598         }
0599     case IIO_CHAN_INFO_OFFSET:
0600         switch (chan->type) {
0601         case IIO_VOLTAGE:
0602             if (chan->output)
0603                 return ad7293_set_offset(st,
0604                              chan->channel +
0605                              AD7293_VOUT_MIN_OFFSET_CH,
0606                              val);
0607             else
0608                 return ad7293_set_offset(st, chan->channel, val);
0609         case IIO_CURRENT:
0610             return ad7293_set_offset(st,
0611                          chan->channel +
0612                          AD7293_ISENSE_MIN_OFFSET_CH,
0613                          val);
0614         case IIO_TEMP:
0615             return ad7293_set_offset(st,
0616                          chan->channel +
0617                          AD7293_TSENSE_MIN_OFFSET_CH,
0618                          val);
0619         default:
0620             return -EINVAL;
0621         }
0622     case IIO_CHAN_INFO_SCALE:
0623         switch (chan->type) {
0624         case IIO_VOLTAGE:
0625             return ad7293_adc_set_scale(st, chan->channel, val);
0626         case IIO_CURRENT:
0627             return ad7293_isense_set_scale(st, chan->channel, val);
0628         default:
0629             return -EINVAL;
0630         }
0631     default:
0632         return -EINVAL;
0633     }
0634 }
0635 
0636 static int ad7293_reg_access(struct iio_dev *indio_dev,
0637                  unsigned int reg,
0638                  unsigned int write_val,
0639                  unsigned int *read_val)
0640 {
0641     struct ad7293_state *st = iio_priv(indio_dev);
0642     int ret;
0643 
0644     if (read_val) {
0645         u16 temp;
0646         ret = ad7293_spi_read(st, reg, &temp);
0647         *read_val = temp;
0648     } else {
0649         ret = ad7293_spi_write(st, reg, (u16)write_val);
0650     }
0651 
0652     return ret;
0653 }
0654 
0655 static int ad7293_read_avail(struct iio_dev *indio_dev,
0656                  struct iio_chan_spec const *chan,
0657                  const int **vals, int *type, int *length,
0658                  long info)
0659 {
0660     switch (info) {
0661     case IIO_CHAN_INFO_OFFSET:
0662         *vals = dac_offset_table;
0663         *type = IIO_VAL_INT;
0664         *length = ARRAY_SIZE(dac_offset_table);
0665 
0666         return IIO_AVAIL_LIST;
0667     case IIO_CHAN_INFO_SCALE:
0668         *type = IIO_VAL_INT;
0669 
0670         switch (chan->type) {
0671         case IIO_VOLTAGE:
0672             *vals = adc_range_table;
0673             *length = ARRAY_SIZE(adc_range_table);
0674             return IIO_AVAIL_LIST;
0675         case IIO_CURRENT:
0676             *vals = isense_gain_table;
0677             *length = ARRAY_SIZE(isense_gain_table);
0678             return IIO_AVAIL_LIST;
0679         default:
0680             return -EINVAL;
0681         }
0682     default:
0683         return -EINVAL;
0684     }
0685 }
0686 
0687 #define AD7293_CHAN_ADC(_channel) {                 \
0688     .type = IIO_VOLTAGE,                        \
0689     .output = 0,                            \
0690     .indexed = 1,                           \
0691     .channel = _channel,                        \
0692     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
0693                   BIT(IIO_CHAN_INFO_SCALE) |        \
0694                   BIT(IIO_CHAN_INFO_OFFSET),        \
0695     .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE)  \
0696 }
0697 
0698 #define AD7293_CHAN_DAC(_channel) {                 \
0699     .type = IIO_VOLTAGE,                        \
0700     .output = 1,                            \
0701     .indexed = 1,                           \
0702     .channel = _channel,                        \
0703     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
0704                   BIT(IIO_CHAN_INFO_OFFSET),        \
0705     .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OFFSET) \
0706 }
0707 
0708 #define AD7293_CHAN_ISENSE(_channel) {                  \
0709     .type = IIO_CURRENT,                        \
0710     .output = 0,                            \
0711     .indexed = 1,                           \
0712     .channel = _channel,                        \
0713     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
0714                   BIT(IIO_CHAN_INFO_OFFSET) |       \
0715                   BIT(IIO_CHAN_INFO_SCALE),         \
0716     .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE)  \
0717 }
0718 
0719 #define AD7293_CHAN_TEMP(_channel) {                    \
0720     .type = IIO_TEMP,                       \
0721     .output = 0,                            \
0722     .indexed = 1,                           \
0723     .channel = _channel,                        \
0724     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
0725                   BIT(IIO_CHAN_INFO_OFFSET),        \
0726     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE)        \
0727 }
0728 
0729 static const struct iio_chan_spec ad7293_channels[] = {
0730     AD7293_CHAN_ADC(0),
0731     AD7293_CHAN_ADC(1),
0732     AD7293_CHAN_ADC(2),
0733     AD7293_CHAN_ADC(3),
0734     AD7293_CHAN_ISENSE(0),
0735     AD7293_CHAN_ISENSE(1),
0736     AD7293_CHAN_ISENSE(2),
0737     AD7293_CHAN_ISENSE(3),
0738     AD7293_CHAN_TEMP(0),
0739     AD7293_CHAN_TEMP(1),
0740     AD7293_CHAN_TEMP(2),
0741     AD7293_CHAN_DAC(0),
0742     AD7293_CHAN_DAC(1),
0743     AD7293_CHAN_DAC(2),
0744     AD7293_CHAN_DAC(3),
0745     AD7293_CHAN_DAC(4),
0746     AD7293_CHAN_DAC(5),
0747     AD7293_CHAN_DAC(6),
0748     AD7293_CHAN_DAC(7)
0749 };
0750 
0751 static int ad7293_soft_reset(struct ad7293_state *st)
0752 {
0753     int ret;
0754 
0755     ret = __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x7293);
0756     if (ret)
0757         return ret;
0758 
0759     return __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x0000);
0760 }
0761 
0762 static int ad7293_reset(struct ad7293_state *st)
0763 {
0764     if (st->gpio_reset) {
0765         gpiod_set_value(st->gpio_reset, 0);
0766         usleep_range(100, 1000);
0767         gpiod_set_value(st->gpio_reset, 1);
0768         usleep_range(100, 1000);
0769 
0770         return 0;
0771     }
0772 
0773     /* Perform a software reset */
0774     return ad7293_soft_reset(st);
0775 }
0776 
0777 static int ad7293_properties_parse(struct ad7293_state *st)
0778 {
0779     struct spi_device *spi = st->spi;
0780 
0781     st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
0782                          GPIOD_OUT_HIGH);
0783     if (IS_ERR(st->gpio_reset))
0784         return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_reset),
0785                      "failed to get the reset GPIO\n");
0786 
0787     st->reg_avdd = devm_regulator_get(&spi->dev, "avdd");
0788     if (IS_ERR(st->reg_avdd))
0789         return dev_err_probe(&spi->dev, PTR_ERR(st->reg_avdd),
0790                      "failed to get the AVDD voltage\n");
0791 
0792     st->reg_vdrive = devm_regulator_get(&spi->dev, "vdrive");
0793     if (IS_ERR(st->reg_vdrive))
0794         return dev_err_probe(&spi->dev, PTR_ERR(st->reg_vdrive),
0795                      "failed to get the VDRIVE voltage\n");
0796 
0797     return 0;
0798 }
0799 
0800 static void ad7293_reg_disable(void *data)
0801 {
0802     regulator_disable(data);
0803 }
0804 
0805 static int ad7293_init(struct ad7293_state *st)
0806 {
0807     int ret;
0808     u16 chip_id;
0809     struct spi_device *spi = st->spi;
0810 
0811     ret = ad7293_properties_parse(st);
0812     if (ret)
0813         return ret;
0814 
0815     ret = ad7293_reset(st);
0816     if (ret)
0817         return ret;
0818 
0819     ret = regulator_enable(st->reg_avdd);
0820     if (ret) {
0821         dev_err(&spi->dev,
0822             "Failed to enable specified AVDD Voltage!\n");
0823         return ret;
0824     }
0825 
0826     ret = devm_add_action_or_reset(&spi->dev, ad7293_reg_disable,
0827                        st->reg_avdd);
0828     if (ret)
0829         return ret;
0830 
0831     ret = regulator_enable(st->reg_vdrive);
0832     if (ret) {
0833         dev_err(&spi->dev,
0834             "Failed to enable specified VDRIVE Voltage!\n");
0835         return ret;
0836     }
0837 
0838     ret = devm_add_action_or_reset(&spi->dev, ad7293_reg_disable,
0839                        st->reg_vdrive);
0840     if (ret)
0841         return ret;
0842 
0843     ret = regulator_get_voltage(st->reg_avdd);
0844     if (ret < 0) {
0845         dev_err(&spi->dev, "Failed to read avdd regulator: %d\n", ret);
0846         return ret;
0847     }
0848 
0849     if (ret > 5500000 || ret < 4500000)
0850         return -EINVAL;
0851 
0852     ret = regulator_get_voltage(st->reg_vdrive);
0853     if (ret < 0) {
0854         dev_err(&spi->dev,
0855             "Failed to read vdrive regulator: %d\n", ret);
0856         return ret;
0857     }
0858     if (ret > 5500000 || ret < 1700000)
0859         return -EINVAL;
0860 
0861     /* Check Chip ID */
0862     ret = __ad7293_spi_read(st, AD7293_REG_DEVICE_ID, &chip_id);
0863     if (ret)
0864         return ret;
0865 
0866     if (chip_id != AD7293_CHIP_ID) {
0867         dev_err(&spi->dev, "Invalid Chip ID.\n");
0868         return -EINVAL;
0869     }
0870 
0871     return 0;
0872 }
0873 
0874 static const struct iio_info ad7293_info = {
0875     .read_raw = ad7293_read_raw,
0876     .write_raw = ad7293_write_raw,
0877     .read_avail = &ad7293_read_avail,
0878     .debugfs_reg_access = &ad7293_reg_access,
0879 };
0880 
0881 static int ad7293_probe(struct spi_device *spi)
0882 {
0883     struct iio_dev *indio_dev;
0884     struct ad7293_state *st;
0885     int ret;
0886 
0887     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0888     if (!indio_dev)
0889         return -ENOMEM;
0890 
0891     st = iio_priv(indio_dev);
0892 
0893     indio_dev->info = &ad7293_info;
0894     indio_dev->name = "ad7293";
0895     indio_dev->channels = ad7293_channels;
0896     indio_dev->num_channels = ARRAY_SIZE(ad7293_channels);
0897 
0898     st->spi = spi;
0899     st->page_select = 0;
0900 
0901     mutex_init(&st->lock);
0902 
0903     ret = ad7293_init(st);
0904     if (ret)
0905         return ret;
0906 
0907     return devm_iio_device_register(&spi->dev, indio_dev);
0908 }
0909 
0910 static const struct spi_device_id ad7293_id[] = {
0911     { "ad7293", 0 },
0912     {}
0913 };
0914 MODULE_DEVICE_TABLE(spi, ad7293_id);
0915 
0916 static const struct of_device_id ad7293_of_match[] = {
0917     { .compatible = "adi,ad7293" },
0918     {}
0919 };
0920 MODULE_DEVICE_TABLE(of, ad7293_of_match);
0921 
0922 static struct spi_driver ad7293_driver = {
0923     .driver = {
0924         .name = "ad7293",
0925         .of_match_table = ad7293_of_match,
0926     },
0927     .probe = ad7293_probe,
0928     .id_table = ad7293_id,
0929 };
0930 module_spi_driver(ad7293_driver);
0931 
0932 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
0933 MODULE_DESCRIPTION("Analog Devices AD7293");
0934 MODULE_LICENSE("GPL v2");
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