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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog Devices AD5766, AD5767
0004  * Digital to Analog Converters driver
0005  * Copyright 2019-2020 Analog Devices Inc.
0006  */
0007 #include <linux/bitfield.h>
0008 #include <linux/bitops.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/iio/iio.h>
0013 #include <linux/iio/triggered_buffer.h>
0014 #include <linux/iio/trigger_consumer.h>
0015 #include <linux/module.h>
0016 #include <linux/spi/spi.h>
0017 #include <asm/unaligned.h>
0018 
0019 #define AD5766_UPPER_WORD_SPI_MASK      GENMASK(31, 16)
0020 #define AD5766_LOWER_WORD_SPI_MASK      GENMASK(15, 0)
0021 #define AD5766_DITHER_SOURCE_MASK(ch)       GENMASK(((2 * ch) + 1), (2 * ch))
0022 #define AD5766_DITHER_SOURCE(ch, source)    BIT((ch * 2) + source)
0023 #define AD5766_DITHER_SCALE_MASK(x)     AD5766_DITHER_SOURCE_MASK(x)
0024 #define AD5766_DITHER_SCALE(ch, scale)      (scale << (ch * 2))
0025 #define AD5766_DITHER_ENABLE_MASK(ch)       BIT(ch)
0026 #define AD5766_DITHER_ENABLE(ch, state)     ((!state) << ch)
0027 #define AD5766_DITHER_INVERT_MASK(ch)       BIT(ch)
0028 #define AD5766_DITHER_INVERT(ch, state)     (state << ch)
0029 
0030 #define AD5766_CMD_NOP_MUX_OUT          0x00
0031 #define AD5766_CMD_SDO_CNTRL            0x01
0032 #define AD5766_CMD_WR_IN_REG(x)         (0x10 | ((x) & GENMASK(3, 0)))
0033 #define AD5766_CMD_WR_DAC_REG(x)        (0x20 | ((x) & GENMASK(3, 0)))
0034 #define AD5766_CMD_SW_LDAC          0x30
0035 #define AD5766_CMD_SPAN_REG         0x40
0036 #define AD5766_CMD_WR_PWR_DITHER        0x51
0037 #define AD5766_CMD_WR_DAC_REG_ALL       0x60
0038 #define AD5766_CMD_SW_FULL_RESET        0x70
0039 #define AD5766_CMD_READBACK_REG(x)      (0x80 | ((x) & GENMASK(3, 0)))
0040 #define AD5766_CMD_DITHER_SIG_1         0x90
0041 #define AD5766_CMD_DITHER_SIG_2         0xA0
0042 #define AD5766_CMD_INV_DITHER           0xB0
0043 #define AD5766_CMD_DITHER_SCALE_1       0xC0
0044 #define AD5766_CMD_DITHER_SCALE_2       0xD0
0045 
0046 #define AD5766_FULL_RESET_CODE          0x1234
0047 
0048 enum ad5766_type {
0049     ID_AD5766,
0050     ID_AD5767,
0051 };
0052 
0053 enum ad5766_voltage_range {
0054     AD5766_VOLTAGE_RANGE_M20V_0V,
0055     AD5766_VOLTAGE_RANGE_M16V_to_0V,
0056     AD5766_VOLTAGE_RANGE_M10V_to_0V,
0057     AD5766_VOLTAGE_RANGE_M12V_to_14V,
0058     AD5766_VOLTAGE_RANGE_M16V_to_10V,
0059     AD5766_VOLTAGE_RANGE_M10V_to_6V,
0060     AD5766_VOLTAGE_RANGE_M5V_to_5V,
0061     AD5766_VOLTAGE_RANGE_M10V_to_10V,
0062 };
0063 
0064 /**
0065  * struct ad5766_chip_info - chip specific information
0066  * @num_channels:   number of channels
0067  * @channels:           channel specification
0068  */
0069 struct ad5766_chip_info {
0070     unsigned int            num_channels;
0071     const struct iio_chan_spec  *channels;
0072 };
0073 
0074 enum {
0075     AD5766_DITHER_ENABLE,
0076     AD5766_DITHER_INVERT,
0077     AD5766_DITHER_SOURCE,
0078 };
0079 
0080 /*
0081  * Dither signal can also be scaled.
0082  * Available dither scale strings corresponding to "dither_scale" field in
0083  * "struct ad5766_state".
0084  */
0085 static const char * const ad5766_dither_scales[] = {
0086     "1",
0087     "0.75",
0088     "0.5",
0089     "0.25",
0090 };
0091 
0092 /**
0093  * struct ad5766_state - driver instance specific data
0094  * @spi:        SPI device
0095  * @lock:       Lock used to restrict concurrent access to SPI device
0096  * @chip_info:      Chip model specific constants
0097  * @gpio_reset:     Reset GPIO, used to reset the device
0098  * @crt_range:      Current selected output range
0099  * @dither_enable:  Power enable bit for each channel dither block (for
0100  *          example, D15 = DAC 15,D8 = DAC 8, and D0 = DAC 0)
0101  *          0 - Normal operation, 1 - Power down
0102  * @dither_invert:  Inverts the dither signal applied to the selected DAC
0103  *          outputs
0104  * @dither_source:  Selects between 2 possible sources:
0105  *          1: N0, 2: N1
0106  *          Two bits are used for each channel
0107  * @dither_scale:   Two bits are used for each of the 16 channels:
0108  *          0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
0109  *          3: 0.25 SCALING.
0110  * @data:       SPI transfer buffers
0111  */
0112 struct ad5766_state {
0113     struct spi_device       *spi;
0114     struct mutex            lock;
0115     const struct ad5766_chip_info   *chip_info;
0116     struct gpio_desc        *gpio_reset;
0117     enum ad5766_voltage_range   crt_range;
0118     u16     dither_enable;
0119     u16     dither_invert;
0120     u32     dither_source;
0121     u32     dither_scale;
0122     union {
0123         u32 d32;
0124         u16 w16[2];
0125         u8  b8[4];
0126     } data[3] __aligned(IIO_DMA_MINALIGN);
0127 };
0128 
0129 struct ad5766_span_tbl {
0130     int     min;
0131     int     max;
0132 };
0133 
0134 static const struct ad5766_span_tbl ad5766_span_tbl[] = {
0135     [AD5766_VOLTAGE_RANGE_M20V_0V] =    {-20, 0},
0136     [AD5766_VOLTAGE_RANGE_M16V_to_0V] = {-16, 0},
0137     [AD5766_VOLTAGE_RANGE_M10V_to_0V] = {-10, 0},
0138     [AD5766_VOLTAGE_RANGE_M12V_to_14V] =    {-12, 14},
0139     [AD5766_VOLTAGE_RANGE_M16V_to_10V] =    {-16, 10},
0140     [AD5766_VOLTAGE_RANGE_M10V_to_6V] = {-10, 6},
0141     [AD5766_VOLTAGE_RANGE_M5V_to_5V] =  {-5, 5},
0142     [AD5766_VOLTAGE_RANGE_M10V_to_10V] =    {-10, 10},
0143 };
0144 
0145 static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val)
0146 {
0147     int ret;
0148     struct spi_transfer xfers[] = {
0149         {
0150             .tx_buf = &st->data[0].d32,
0151             .bits_per_word = 8,
0152             .len = 3,
0153             .cs_change = 1,
0154         }, {
0155             .tx_buf = &st->data[1].d32,
0156             .rx_buf = &st->data[2].d32,
0157             .bits_per_word = 8,
0158             .len = 3,
0159         },
0160     };
0161 
0162     st->data[0].d32 = AD5766_CMD_READBACK_REG(dac);
0163     st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT;
0164 
0165     ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
0166     if (ret)
0167         return ret;
0168 
0169     *val = st->data[2].w16[1];
0170 
0171     return ret;
0172 }
0173 
0174 static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data)
0175 {
0176     st->data[0].b8[0] = command;
0177     put_unaligned_be16(data, &st->data[0].b8[1]);
0178 
0179     return spi_write(st->spi, &st->data[0].b8[0], 3);
0180 }
0181 
0182 static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val)
0183 {
0184     struct ad5766_state *st = iio_priv(indio_dev);
0185     int ret;
0186 
0187     mutex_lock(&st->lock);
0188     ret = __ad5766_spi_read(st, dac, val);
0189     mutex_unlock(&st->lock);
0190 
0191     return ret;
0192 }
0193 
0194 static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data)
0195 {
0196     struct ad5766_state *st = iio_priv(indio_dev);
0197     int ret;
0198 
0199     mutex_lock(&st->lock);
0200     ret = __ad5766_spi_write(st, AD5766_CMD_WR_DAC_REG(dac), data);
0201     mutex_unlock(&st->lock);
0202 
0203     return ret;
0204 }
0205 
0206 static int ad5766_reset(struct ad5766_state *st)
0207 {
0208     int ret;
0209 
0210     if (st->gpio_reset) {
0211         gpiod_set_value_cansleep(st->gpio_reset, 1);
0212         ndelay(100); /* t_reset >= 100ns */
0213         gpiod_set_value_cansleep(st->gpio_reset, 0);
0214     } else {
0215         ret = __ad5766_spi_write(st, AD5766_CMD_SW_FULL_RESET,
0216                     AD5766_FULL_RESET_CODE);
0217         if (ret < 0)
0218             return ret;
0219     }
0220 
0221     /*
0222      * Minimum time between a reset and the subsequent successful write is
0223      * typically 25 ns
0224      */
0225     ndelay(25);
0226 
0227     return 0;
0228 }
0229 
0230 static int ad5766_read_raw(struct iio_dev *indio_dev,
0231                struct iio_chan_spec const *chan,
0232                int *val,
0233                int *val2,
0234                long m)
0235 {
0236     struct ad5766_state *st = iio_priv(indio_dev);
0237     int ret;
0238 
0239     switch (m) {
0240     case IIO_CHAN_INFO_RAW:
0241         ret = ad5766_read(indio_dev, chan->address, val);
0242         if (ret)
0243             return ret;
0244 
0245         return IIO_VAL_INT;
0246     case IIO_CHAN_INFO_OFFSET:
0247         *val = ad5766_span_tbl[st->crt_range].min;
0248 
0249         return IIO_VAL_INT;
0250     case IIO_CHAN_INFO_SCALE:
0251         *val = ad5766_span_tbl[st->crt_range].max -
0252                ad5766_span_tbl[st->crt_range].min;
0253         *val2 = st->chip_info->channels[0].scan_type.realbits;
0254 
0255         return IIO_VAL_FRACTIONAL_LOG2;
0256     default:
0257         return -EINVAL;
0258     }
0259 }
0260 
0261 static int ad5766_write_raw(struct iio_dev *indio_dev,
0262                 struct iio_chan_spec const *chan,
0263                 int val,
0264                 int val2,
0265                 long info)
0266 {
0267     switch (info) {
0268     case IIO_CHAN_INFO_RAW:
0269     {
0270         const int max_val = GENMASK(chan->scan_type.realbits - 1, 0);
0271 
0272         if (val > max_val || val < 0)
0273             return -EINVAL;
0274         val <<= chan->scan_type.shift;
0275         return ad5766_write(indio_dev, chan->address, val);
0276     }
0277     default:
0278         return -EINVAL;
0279     }
0280 }
0281 
0282 static const struct iio_info ad5766_info = {
0283     .read_raw = ad5766_read_raw,
0284     .write_raw = ad5766_write_raw,
0285 };
0286 
0287 static int ad5766_get_dither_source(struct iio_dev *dev,
0288                     const struct iio_chan_spec *chan)
0289 {
0290     struct ad5766_state *st = iio_priv(dev);
0291     u32 source;
0292 
0293     source = st->dither_source & AD5766_DITHER_SOURCE_MASK(chan->channel);
0294     source = source >> (chan->channel * 2);
0295     source -= 1;
0296 
0297     return source;
0298 }
0299 
0300 static int ad5766_set_dither_source(struct iio_dev *dev,
0301               const struct iio_chan_spec *chan,
0302               unsigned int source)
0303 {
0304     struct ad5766_state *st = iio_priv(dev);
0305     uint16_t val;
0306     int ret;
0307 
0308     st->dither_source &= ~AD5766_DITHER_SOURCE_MASK(chan->channel);
0309     st->dither_source |= AD5766_DITHER_SOURCE(chan->channel, source);
0310 
0311     val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
0312     ret = ad5766_write(dev, AD5766_CMD_DITHER_SIG_1, val);
0313     if (ret)
0314         return ret;
0315 
0316     val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
0317 
0318     return ad5766_write(dev, AD5766_CMD_DITHER_SIG_2, val);
0319 }
0320 
0321 static int ad5766_get_dither_scale(struct iio_dev *dev,
0322                    const struct iio_chan_spec *chan)
0323 {
0324     struct ad5766_state *st = iio_priv(dev);
0325     u32 scale;
0326 
0327     scale = st->dither_scale & AD5766_DITHER_SCALE_MASK(chan->channel);
0328 
0329     return (scale >> (chan->channel * 2));
0330 }
0331 
0332 static int ad5766_set_dither_scale(struct iio_dev *dev,
0333               const struct iio_chan_spec *chan,
0334               unsigned int scale)
0335 {
0336     int ret;
0337     struct ad5766_state *st = iio_priv(dev);
0338     uint16_t val;
0339 
0340     st->dither_scale &= ~AD5766_DITHER_SCALE_MASK(chan->channel);
0341     st->dither_scale |= AD5766_DITHER_SCALE(chan->channel, scale);
0342 
0343     val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
0344     ret = ad5766_write(dev, AD5766_CMD_DITHER_SCALE_1, val);
0345     if (ret)
0346         return ret;
0347     val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
0348 
0349     return ad5766_write(dev, AD5766_CMD_DITHER_SCALE_2, val);
0350 }
0351 
0352 static const struct iio_enum ad5766_dither_scale_enum = {
0353     .items = ad5766_dither_scales,
0354     .num_items = ARRAY_SIZE(ad5766_dither_scales),
0355     .set = ad5766_set_dither_scale,
0356     .get = ad5766_get_dither_scale,
0357 };
0358 
0359 static ssize_t ad5766_read_ext(struct iio_dev *indio_dev,
0360                    uintptr_t private,
0361                    const struct iio_chan_spec *chan,
0362                    char *buf)
0363 {
0364     struct ad5766_state *st = iio_priv(indio_dev);
0365 
0366     switch (private) {
0367     case AD5766_DITHER_ENABLE:
0368         return sprintf(buf, "%u\n",
0369                    !(st->dither_enable & BIT(chan->channel)));
0370         break;
0371     case AD5766_DITHER_INVERT:
0372         return sprintf(buf, "%u\n",
0373                    !!(st->dither_invert & BIT(chan->channel)));
0374         break;
0375     case AD5766_DITHER_SOURCE:
0376         return sprintf(buf, "%d\n",
0377                    ad5766_get_dither_source(indio_dev, chan));
0378     default:
0379         return -EINVAL;
0380     }
0381 }
0382 
0383 static ssize_t ad5766_write_ext(struct iio_dev *indio_dev,
0384                  uintptr_t private,
0385                  const struct iio_chan_spec *chan,
0386                  const char *buf, size_t len)
0387 {
0388     struct ad5766_state *st = iio_priv(indio_dev);
0389     bool readin;
0390     int ret;
0391 
0392     ret = kstrtobool(buf, &readin);
0393     if (ret)
0394         return ret;
0395 
0396     switch (private) {
0397     case AD5766_DITHER_ENABLE:
0398         st->dither_enable &= ~AD5766_DITHER_ENABLE_MASK(chan->channel);
0399         st->dither_enable |= AD5766_DITHER_ENABLE(chan->channel,
0400                               readin);
0401         ret = ad5766_write(indio_dev, AD5766_CMD_WR_PWR_DITHER,
0402                    st->dither_enable);
0403         break;
0404     case AD5766_DITHER_INVERT:
0405         st->dither_invert &= ~AD5766_DITHER_INVERT_MASK(chan->channel);
0406         st->dither_invert |= AD5766_DITHER_INVERT(chan->channel,
0407                               readin);
0408         ret = ad5766_write(indio_dev, AD5766_CMD_INV_DITHER,
0409                    st->dither_invert);
0410         break;
0411     case AD5766_DITHER_SOURCE:
0412         ret = ad5766_set_dither_source(indio_dev, chan, readin);
0413         break;
0414     default:
0415         return -EINVAL;
0416     }
0417 
0418     return ret ? ret : len;
0419 }
0420 
0421 #define _AD5766_CHAN_EXT_INFO(_name, _what, _shared) { \
0422     .name = _name, \
0423     .read = ad5766_read_ext, \
0424     .write = ad5766_write_ext, \
0425     .private = _what, \
0426     .shared = _shared, \
0427 }
0428 
0429 static const struct iio_chan_spec_ext_info ad5766_ext_info[] = {
0430 
0431     _AD5766_CHAN_EXT_INFO("dither_enable", AD5766_DITHER_ENABLE,
0432                   IIO_SEPARATE),
0433     _AD5766_CHAN_EXT_INFO("dither_invert", AD5766_DITHER_INVERT,
0434                   IIO_SEPARATE),
0435     _AD5766_CHAN_EXT_INFO("dither_source", AD5766_DITHER_SOURCE,
0436                   IIO_SEPARATE),
0437     IIO_ENUM("dither_scale", IIO_SEPARATE, &ad5766_dither_scale_enum),
0438     IIO_ENUM_AVAILABLE("dither_scale", IIO_SEPARATE,
0439                &ad5766_dither_scale_enum),
0440     {}
0441 };
0442 
0443 #define AD576x_CHANNEL(_chan, _bits) {                  \
0444     .type = IIO_VOLTAGE,                        \
0445     .indexed = 1,                           \
0446     .output = 1,                            \
0447     .channel = (_chan),                     \
0448     .address = (_chan),                     \
0449     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
0450     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |     \
0451         BIT(IIO_CHAN_INFO_SCALE),               \
0452     .scan_index = (_chan),                      \
0453     .scan_type = {                          \
0454         .sign = 'u',                        \
0455         .realbits = (_bits),                    \
0456         .storagebits = 16,                  \
0457         .shift = 16 - (_bits),                  \
0458     },                              \
0459     .ext_info = ad5766_ext_info,                    \
0460 }
0461 
0462 #define DECLARE_AD576x_CHANNELS(_name, _bits)           \
0463 const struct iio_chan_spec _name[] = {              \
0464     AD576x_CHANNEL(0, (_bits)),             \
0465     AD576x_CHANNEL(1, (_bits)),             \
0466     AD576x_CHANNEL(2, (_bits)),             \
0467     AD576x_CHANNEL(3, (_bits)),             \
0468     AD576x_CHANNEL(4, (_bits)),             \
0469     AD576x_CHANNEL(5, (_bits)),             \
0470     AD576x_CHANNEL(6, (_bits)),             \
0471     AD576x_CHANNEL(7, (_bits)),             \
0472     AD576x_CHANNEL(8, (_bits)),             \
0473     AD576x_CHANNEL(9, (_bits)),             \
0474     AD576x_CHANNEL(10, (_bits)),                \
0475     AD576x_CHANNEL(11, (_bits)),                \
0476     AD576x_CHANNEL(12, (_bits)),                \
0477     AD576x_CHANNEL(13, (_bits)),                \
0478     AD576x_CHANNEL(14, (_bits)),                \
0479     AD576x_CHANNEL(15, (_bits)),                \
0480 }
0481 
0482 static DECLARE_AD576x_CHANNELS(ad5766_channels, 16);
0483 static DECLARE_AD576x_CHANNELS(ad5767_channels, 12);
0484 
0485 static const struct ad5766_chip_info ad5766_chip_infos[] = {
0486     [ID_AD5766] = {
0487         .num_channels = ARRAY_SIZE(ad5766_channels),
0488         .channels = ad5766_channels,
0489     },
0490     [ID_AD5767] = {
0491         .num_channels = ARRAY_SIZE(ad5767_channels),
0492         .channels = ad5767_channels,
0493     },
0494 };
0495 
0496 static int ad5766_get_output_range(struct ad5766_state *st)
0497 {
0498     int i, ret, min, max, tmp[2];
0499 
0500     ret = device_property_read_u32_array(&st->spi->dev,
0501                          "output-range-microvolts",
0502                          tmp, 2);
0503     if (ret)
0504         return ret;
0505 
0506     min = tmp[0] / 1000000;
0507     max = tmp[1] / 1000000;
0508     for (i = 0; i < ARRAY_SIZE(ad5766_span_tbl); i++) {
0509         if (ad5766_span_tbl[i].min != min ||
0510             ad5766_span_tbl[i].max != max)
0511             continue;
0512 
0513         st->crt_range = i;
0514 
0515         return 0;
0516     }
0517 
0518     return -EINVAL;
0519 }
0520 
0521 static int ad5766_default_setup(struct ad5766_state *st)
0522 {
0523     uint16_t val;
0524     int ret, i;
0525 
0526     /* Always issue a reset before writing to the span register. */
0527     ret = ad5766_reset(st);
0528     if (ret)
0529         return ret;
0530 
0531     ret = ad5766_get_output_range(st);
0532     if (ret)
0533         return ret;
0534 
0535     /* Dither power down */
0536     st->dither_enable = GENMASK(15, 0);
0537     ret = __ad5766_spi_write(st, AD5766_CMD_WR_PWR_DITHER,
0538                  st->dither_enable);
0539     if (ret)
0540         return ret;
0541 
0542     st->dither_source = 0;
0543     for (i = 0; i < ARRAY_SIZE(ad5766_channels); i++)
0544         st->dither_source |= AD5766_DITHER_SOURCE(i, 0);
0545     val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
0546     ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_1, val);
0547     if (ret)
0548         return ret;
0549 
0550     val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
0551     ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_2, val);
0552     if (ret)
0553         return ret;
0554 
0555     st->dither_scale = 0;
0556     val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
0557     ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_1, val);
0558     if (ret)
0559         return ret;
0560 
0561     val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
0562     ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_2, val);
0563     if (ret)
0564         return ret;
0565 
0566     st->dither_invert = 0;
0567     ret = __ad5766_spi_write(st, AD5766_CMD_INV_DITHER, st->dither_invert);
0568     if (ret)
0569         return ret;
0570 
0571     return  __ad5766_spi_write(st, AD5766_CMD_SPAN_REG, st->crt_range);
0572 }
0573 
0574 static irqreturn_t ad5766_trigger_handler(int irq, void *p)
0575 {
0576     struct iio_poll_func *pf = p;
0577     struct iio_dev *indio_dev = pf->indio_dev;
0578     struct iio_buffer *buffer = indio_dev->buffer;
0579     struct ad5766_state *st = iio_priv(indio_dev);
0580     int ret, ch, i;
0581     u16 data[ARRAY_SIZE(ad5766_channels)];
0582 
0583     ret = iio_pop_from_buffer(buffer, data);
0584     if (ret)
0585         goto done;
0586 
0587     i = 0;
0588     mutex_lock(&st->lock);
0589     for_each_set_bit(ch, indio_dev->active_scan_mask,
0590              st->chip_info->num_channels - 1)
0591         __ad5766_spi_write(st, AD5766_CMD_WR_IN_REG(ch), data[i++]);
0592 
0593     __ad5766_spi_write(st, AD5766_CMD_SW_LDAC,
0594                *indio_dev->active_scan_mask);
0595     mutex_unlock(&st->lock);
0596 
0597 done:
0598     iio_trigger_notify_done(indio_dev->trig);
0599 
0600     return IRQ_HANDLED;
0601 }
0602 
0603 static int ad5766_probe(struct spi_device *spi)
0604 {
0605     enum ad5766_type type;
0606     struct iio_dev *indio_dev;
0607     struct ad5766_state *st;
0608     int ret;
0609 
0610     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0611     if (!indio_dev)
0612         return -ENOMEM;
0613 
0614     st = iio_priv(indio_dev);
0615     mutex_init(&st->lock);
0616 
0617     st->spi = spi;
0618     type = spi_get_device_id(spi)->driver_data;
0619     st->chip_info = &ad5766_chip_infos[type];
0620 
0621     indio_dev->channels = st->chip_info->channels;
0622     indio_dev->num_channels = st->chip_info->num_channels;
0623     indio_dev->info = &ad5766_info;
0624     indio_dev->name = spi_get_device_id(spi)->name;
0625     indio_dev->modes = INDIO_DIRECT_MODE;
0626 
0627     st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
0628                         GPIOD_OUT_LOW);
0629     if (IS_ERR(st->gpio_reset))
0630         return PTR_ERR(st->gpio_reset);
0631 
0632     ret = ad5766_default_setup(st);
0633     if (ret)
0634         return ret;
0635 
0636     /* Configure trigger buffer */
0637     ret = devm_iio_triggered_buffer_setup_ext(&spi->dev, indio_dev, NULL,
0638                           ad5766_trigger_handler,
0639                           IIO_BUFFER_DIRECTION_OUT,
0640                           NULL,
0641                           NULL);
0642     if (ret)
0643         return ret;
0644 
0645     return devm_iio_device_register(&spi->dev, indio_dev);
0646 }
0647 
0648 static const struct of_device_id ad5766_dt_match[] = {
0649     { .compatible = "adi,ad5766" },
0650     { .compatible = "adi,ad5767" },
0651     {}
0652 };
0653 MODULE_DEVICE_TABLE(of, ad5766_dt_match);
0654 
0655 static const struct spi_device_id ad5766_spi_ids[] = {
0656     { "ad5766", ID_AD5766 },
0657     { "ad5767", ID_AD5767 },
0658     {}
0659 };
0660 MODULE_DEVICE_TABLE(spi, ad5766_spi_ids);
0661 
0662 static struct spi_driver ad5766_driver = {
0663     .driver = {
0664         .name = "ad5766",
0665         .of_match_table = ad5766_dt_match,
0666     },
0667     .probe = ad5766_probe,
0668     .id_table = ad5766_spi_ids,
0669 };
0670 module_spi_driver(ad5766_driver);
0671 
0672 MODULE_AUTHOR("Denis-Gabriel Gheorghescu <denis.gheorghescu@analog.com>");
0673 MODULE_DESCRIPTION("Analog Devices AD5766/AD5767 DACs");
0674 MODULE_LICENSE("GPL v2");
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