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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
0004  * Digital to Analog Converters driver
0005  *
0006  * Copyright 2011 Analog Devices Inc.
0007  */
0008 
0009 #include <linux/device.h>
0010 #include <linux/err.h>
0011 #include <linux/module.h>
0012 #include <linux/kernel.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/slab.h>
0015 #include <linux/sysfs.h>
0016 #include <linux/regulator/consumer.h>
0017 
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 
0021 #define AD5764_REG_SF_NOP           0x0
0022 #define AD5764_REG_SF_CONFIG            0x1
0023 #define AD5764_REG_SF_CLEAR         0x4
0024 #define AD5764_REG_SF_LOAD          0x5
0025 #define AD5764_REG_DATA(x)          ((2 << 3) | (x))
0026 #define AD5764_REG_COARSE_GAIN(x)       ((3 << 3) | (x))
0027 #define AD5764_REG_FINE_GAIN(x)         ((4 << 3) | (x))
0028 #define AD5764_REG_OFFSET(x)            ((5 << 3) | (x))
0029 
0030 #define AD5764_NUM_CHANNELS 4
0031 
0032 /**
0033  * struct ad5764_chip_info - chip specific information
0034  * @int_vref:   Value of the internal reference voltage in uV - 0 if external
0035  *      reference voltage is used
0036  * @channels:   channel specification
0037 */
0038 struct ad5764_chip_info {
0039     unsigned long int_vref;
0040     const struct iio_chan_spec *channels;
0041 };
0042 
0043 /**
0044  * struct ad5764_state - driver instance specific data
0045  * @spi:        spi_device
0046  * @chip_info:      chip info
0047  * @vref_reg:       vref supply regulators
0048  * @lock:       lock to protect the data buffer during SPI ops
0049  * @data:       spi transfer buffers
0050  */
0051 
0052 struct ad5764_state {
0053     struct spi_device       *spi;
0054     const struct ad5764_chip_info   *chip_info;
0055     struct regulator_bulk_data  vref_reg[2];
0056     struct mutex            lock;
0057 
0058     /*
0059      * DMA (thus cache coherency maintenance) may require the
0060      * transfer buffers to live in their own cache lines.
0061      */
0062     union {
0063         __be32 d32;
0064         u8 d8[4];
0065     } data[2] __aligned(IIO_DMA_MINALIGN);
0066 };
0067 
0068 enum ad5764_type {
0069     ID_AD5744,
0070     ID_AD5744R,
0071     ID_AD5764,
0072     ID_AD5764R,
0073 };
0074 
0075 #define AD5764_CHANNEL(_chan, _bits) {              \
0076     .type = IIO_VOLTAGE,                    \
0077     .indexed = 1,                       \
0078     .output = 1,                        \
0079     .channel = (_chan),                 \
0080     .address = (_chan),                 \
0081     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0082         BIT(IIO_CHAN_INFO_SCALE) |          \
0083         BIT(IIO_CHAN_INFO_CALIBSCALE) |         \
0084         BIT(IIO_CHAN_INFO_CALIBBIAS),           \
0085     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET),  \
0086     .scan_type = {                      \
0087         .sign = 'u',                    \
0088         .realbits = (_bits),                \
0089         .storagebits = 16,              \
0090         .shift = 16 - (_bits),              \
0091     },                          \
0092 }
0093 
0094 #define DECLARE_AD5764_CHANNELS(_name, _bits) \
0095 const struct iio_chan_spec _name##_channels[] = { \
0096     AD5764_CHANNEL(0, (_bits)), \
0097     AD5764_CHANNEL(1, (_bits)), \
0098     AD5764_CHANNEL(2, (_bits)), \
0099     AD5764_CHANNEL(3, (_bits)), \
0100 };
0101 
0102 static DECLARE_AD5764_CHANNELS(ad5764, 16);
0103 static DECLARE_AD5764_CHANNELS(ad5744, 14);
0104 
0105 static const struct ad5764_chip_info ad5764_chip_infos[] = {
0106     [ID_AD5744] = {
0107         .int_vref = 0,
0108         .channels = ad5744_channels,
0109     },
0110     [ID_AD5744R] = {
0111         .int_vref = 5000000,
0112         .channels = ad5744_channels,
0113     },
0114     [ID_AD5764] = {
0115         .int_vref = 0,
0116         .channels = ad5764_channels,
0117     },
0118     [ID_AD5764R] = {
0119         .int_vref = 5000000,
0120         .channels = ad5764_channels,
0121     },
0122 };
0123 
0124 static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
0125     unsigned int val)
0126 {
0127     struct ad5764_state *st = iio_priv(indio_dev);
0128     int ret;
0129 
0130     mutex_lock(&st->lock);
0131     st->data[0].d32 = cpu_to_be32((reg << 16) | val);
0132 
0133     ret = spi_write(st->spi, &st->data[0].d8[1], 3);
0134     mutex_unlock(&st->lock);
0135 
0136     return ret;
0137 }
0138 
0139 static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
0140     unsigned int *val)
0141 {
0142     struct ad5764_state *st = iio_priv(indio_dev);
0143     int ret;
0144     struct spi_transfer t[] = {
0145         {
0146             .tx_buf = &st->data[0].d8[1],
0147             .len = 3,
0148             .cs_change = 1,
0149         }, {
0150             .rx_buf = &st->data[1].d8[1],
0151             .len = 3,
0152         },
0153     };
0154 
0155     mutex_lock(&st->lock);
0156 
0157     st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
0158 
0159     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0160     if (ret >= 0)
0161         *val = be32_to_cpu(st->data[1].d32) & 0xffff;
0162 
0163     mutex_unlock(&st->lock);
0164 
0165     return ret;
0166 }
0167 
0168 static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
0169 {
0170     switch (info) {
0171     case IIO_CHAN_INFO_RAW:
0172         return AD5764_REG_DATA(chan->address);
0173     case IIO_CHAN_INFO_CALIBBIAS:
0174         return AD5764_REG_OFFSET(chan->address);
0175     case IIO_CHAN_INFO_CALIBSCALE:
0176         return AD5764_REG_FINE_GAIN(chan->address);
0177     default:
0178         break;
0179     }
0180 
0181     return 0;
0182 }
0183 
0184 static int ad5764_write_raw(struct iio_dev *indio_dev,
0185     struct iio_chan_spec const *chan, int val, int val2, long info)
0186 {
0187     const int max_val = (1 << chan->scan_type.realbits);
0188     unsigned int reg;
0189 
0190     switch (info) {
0191     case IIO_CHAN_INFO_RAW:
0192         if (val >= max_val || val < 0)
0193             return -EINVAL;
0194         val <<= chan->scan_type.shift;
0195         break;
0196     case IIO_CHAN_INFO_CALIBBIAS:
0197         if (val >= 128 || val < -128)
0198             return -EINVAL;
0199         break;
0200     case IIO_CHAN_INFO_CALIBSCALE:
0201         if (val >= 32 || val < -32)
0202             return -EINVAL;
0203         break;
0204     default:
0205         return -EINVAL;
0206     }
0207 
0208     reg = ad5764_chan_info_to_reg(chan, info);
0209     return ad5764_write(indio_dev, reg, (u16)val);
0210 }
0211 
0212 static int ad5764_get_channel_vref(struct ad5764_state *st,
0213     unsigned int channel)
0214 {
0215     if (st->chip_info->int_vref)
0216         return st->chip_info->int_vref;
0217     else
0218         return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
0219 }
0220 
0221 static int ad5764_read_raw(struct iio_dev *indio_dev,
0222     struct iio_chan_spec const *chan, int *val, int *val2, long info)
0223 {
0224     struct ad5764_state *st = iio_priv(indio_dev);
0225     unsigned int reg;
0226     int vref;
0227     int ret;
0228 
0229     switch (info) {
0230     case IIO_CHAN_INFO_RAW:
0231         reg = AD5764_REG_DATA(chan->address);
0232         ret = ad5764_read(indio_dev, reg, val);
0233         if (ret < 0)
0234             return ret;
0235         *val >>= chan->scan_type.shift;
0236         return IIO_VAL_INT;
0237     case IIO_CHAN_INFO_CALIBBIAS:
0238         reg = AD5764_REG_OFFSET(chan->address);
0239         ret = ad5764_read(indio_dev, reg, val);
0240         if (ret < 0)
0241             return ret;
0242         *val = sign_extend32(*val, 7);
0243         return IIO_VAL_INT;
0244     case IIO_CHAN_INFO_CALIBSCALE:
0245         reg = AD5764_REG_FINE_GAIN(chan->address);
0246         ret = ad5764_read(indio_dev, reg, val);
0247         if (ret < 0)
0248             return ret;
0249         *val = sign_extend32(*val, 5);
0250         return IIO_VAL_INT;
0251     case IIO_CHAN_INFO_SCALE:
0252         /* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
0253         vref = ad5764_get_channel_vref(st, chan->channel);
0254         if (vref < 0)
0255             return vref;
0256 
0257         *val = vref * 4 / 1000;
0258         *val2 = chan->scan_type.realbits;
0259         return IIO_VAL_FRACTIONAL_LOG2;
0260     case IIO_CHAN_INFO_OFFSET:
0261         *val = -(1 << chan->scan_type.realbits) / 2;
0262         return IIO_VAL_INT;
0263     }
0264 
0265     return -EINVAL;
0266 }
0267 
0268 static const struct iio_info ad5764_info = {
0269     .read_raw = ad5764_read_raw,
0270     .write_raw = ad5764_write_raw,
0271 };
0272 
0273 static int ad5764_probe(struct spi_device *spi)
0274 {
0275     enum ad5764_type type = spi_get_device_id(spi)->driver_data;
0276     struct iio_dev *indio_dev;
0277     struct ad5764_state *st;
0278     int ret;
0279 
0280     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0281     if (indio_dev == NULL) {
0282         dev_err(&spi->dev, "Failed to allocate iio device\n");
0283         return -ENOMEM;
0284     }
0285 
0286     st = iio_priv(indio_dev);
0287     spi_set_drvdata(spi, indio_dev);
0288 
0289     st->spi = spi;
0290     st->chip_info = &ad5764_chip_infos[type];
0291 
0292     indio_dev->name = spi_get_device_id(spi)->name;
0293     indio_dev->info = &ad5764_info;
0294     indio_dev->modes = INDIO_DIRECT_MODE;
0295     indio_dev->num_channels = AD5764_NUM_CHANNELS;
0296     indio_dev->channels = st->chip_info->channels;
0297 
0298     mutex_init(&st->lock);
0299 
0300     if (st->chip_info->int_vref == 0) {
0301         st->vref_reg[0].supply = "vrefAB";
0302         st->vref_reg[1].supply = "vrefCD";
0303 
0304         ret = devm_regulator_bulk_get(&st->spi->dev,
0305             ARRAY_SIZE(st->vref_reg), st->vref_reg);
0306         if (ret) {
0307             dev_err(&spi->dev, "Failed to request vref regulators: %d\n",
0308                 ret);
0309             return ret;
0310         }
0311 
0312         ret = regulator_bulk_enable(ARRAY_SIZE(st->vref_reg),
0313             st->vref_reg);
0314         if (ret) {
0315             dev_err(&spi->dev, "Failed to enable vref regulators: %d\n",
0316                 ret);
0317             return ret;
0318         }
0319     }
0320 
0321     ret = iio_device_register(indio_dev);
0322     if (ret) {
0323         dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
0324         goto error_disable_reg;
0325     }
0326 
0327     return 0;
0328 
0329 error_disable_reg:
0330     if (st->chip_info->int_vref == 0)
0331         regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
0332     return ret;
0333 }
0334 
0335 static void ad5764_remove(struct spi_device *spi)
0336 {
0337     struct iio_dev *indio_dev = spi_get_drvdata(spi);
0338     struct ad5764_state *st = iio_priv(indio_dev);
0339 
0340     iio_device_unregister(indio_dev);
0341 
0342     if (st->chip_info->int_vref == 0)
0343         regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
0344 }
0345 
0346 static const struct spi_device_id ad5764_ids[] = {
0347     { "ad5744", ID_AD5744 },
0348     { "ad5744r", ID_AD5744R },
0349     { "ad5764", ID_AD5764 },
0350     { "ad5764r", ID_AD5764R },
0351     { }
0352 };
0353 MODULE_DEVICE_TABLE(spi, ad5764_ids);
0354 
0355 static struct spi_driver ad5764_driver = {
0356     .driver = {
0357         .name = "ad5764",
0358     },
0359     .probe = ad5764_probe,
0360     .remove = ad5764_remove,
0361     .id_table = ad5764_ids,
0362 };
0363 module_spi_driver(ad5764_driver);
0364 
0365 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0366 MODULE_DESCRIPTION("Analog Devices AD5744/AD5744R/AD5764/AD5764R DAC");
0367 MODULE_LICENSE("GPL v2");
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