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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
0004  *
0005  * Copyright 2012 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/device.h>
0009 #include <linux/err.h>
0010 #include <linux/module.h>
0011 #include <linux/kernel.h>
0012 #include <linux/spi/spi.h>
0013 #include <linux/slab.h>
0014 #include <linux/sysfs.h>
0015 #include <linux/delay.h>
0016 #include <linux/property.h>
0017 
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 
0021 #define AD5755_NUM_CHANNELS 4
0022 
0023 #define AD5755_ADDR(x)          ((x) << 16)
0024 
0025 #define AD5755_WRITE_REG_DATA(chan) (chan)
0026 #define AD5755_WRITE_REG_GAIN(chan) (0x08 | (chan))
0027 #define AD5755_WRITE_REG_OFFSET(chan)   (0x10 | (chan))
0028 #define AD5755_WRITE_REG_CTRL(chan) (0x1c | (chan))
0029 
0030 #define AD5755_READ_REG_DATA(chan)  (chan)
0031 #define AD5755_READ_REG_CTRL(chan)  (0x4 | (chan))
0032 #define AD5755_READ_REG_GAIN(chan)  (0x8 | (chan))
0033 #define AD5755_READ_REG_OFFSET(chan)    (0xc | (chan))
0034 #define AD5755_READ_REG_CLEAR(chan) (0x10 | (chan))
0035 #define AD5755_READ_REG_SLEW(chan)  (0x14 | (chan))
0036 #define AD5755_READ_REG_STATUS      0x18
0037 #define AD5755_READ_REG_MAIN        0x19
0038 #define AD5755_READ_REG_DC_DC       0x1a
0039 
0040 #define AD5755_CTRL_REG_SLEW    0x0
0041 #define AD5755_CTRL_REG_MAIN    0x1
0042 #define AD5755_CTRL_REG_DAC 0x2
0043 #define AD5755_CTRL_REG_DC_DC   0x3
0044 #define AD5755_CTRL_REG_SW  0x4
0045 
0046 #define AD5755_READ_FLAG 0x800000
0047 
0048 #define AD5755_NOOP 0x1CE000
0049 
0050 #define AD5755_DAC_INT_EN           BIT(8)
0051 #define AD5755_DAC_CLR_EN           BIT(7)
0052 #define AD5755_DAC_OUT_EN           BIT(6)
0053 #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR   BIT(5)
0054 #define AD5755_DAC_DC_DC_EN         BIT(4)
0055 #define AD5755_DAC_VOLTAGE_OVERRANGE_EN     BIT(3)
0056 
0057 #define AD5755_DC_DC_MAXV           0
0058 #define AD5755_DC_DC_FREQ_SHIFT         2
0059 #define AD5755_DC_DC_PHASE_SHIFT        4
0060 #define AD5755_EXT_DC_DC_COMP_RES       BIT(6)
0061 
0062 #define AD5755_SLEW_STEP_SIZE_SHIFT     0
0063 #define AD5755_SLEW_RATE_SHIFT          3
0064 #define AD5755_SLEW_ENABLE          BIT(12)
0065 
0066 enum ad5755_mode {
0067     AD5755_MODE_VOLTAGE_0V_5V       = 0,
0068     AD5755_MODE_VOLTAGE_0V_10V      = 1,
0069     AD5755_MODE_VOLTAGE_PLUSMINUS_5V    = 2,
0070     AD5755_MODE_VOLTAGE_PLUSMINUS_10V   = 3,
0071     AD5755_MODE_CURRENT_4mA_20mA        = 4,
0072     AD5755_MODE_CURRENT_0mA_20mA        = 5,
0073     AD5755_MODE_CURRENT_0mA_24mA        = 6,
0074 };
0075 
0076 enum ad5755_dc_dc_phase {
0077     AD5755_DC_DC_PHASE_ALL_SAME_EDGE        = 0,
0078     AD5755_DC_DC_PHASE_A_B_SAME_EDGE_C_D_OPP_EDGE   = 1,
0079     AD5755_DC_DC_PHASE_A_C_SAME_EDGE_B_D_OPP_EDGE   = 2,
0080     AD5755_DC_DC_PHASE_90_DEGREE            = 3,
0081 };
0082 
0083 enum ad5755_dc_dc_freq {
0084     AD5755_DC_DC_FREQ_250kHZ = 0,
0085     AD5755_DC_DC_FREQ_410kHZ = 1,
0086     AD5755_DC_DC_FREQ_650kHZ = 2,
0087 };
0088 
0089 enum ad5755_dc_dc_maxv {
0090     AD5755_DC_DC_MAXV_23V   = 0,
0091     AD5755_DC_DC_MAXV_24V5  = 1,
0092     AD5755_DC_DC_MAXV_27V   = 2,
0093     AD5755_DC_DC_MAXV_29V5  = 3,
0094 };
0095 
0096 enum ad5755_slew_rate {
0097     AD5755_SLEW_RATE_64k    = 0,
0098     AD5755_SLEW_RATE_32k    = 1,
0099     AD5755_SLEW_RATE_16k    = 2,
0100     AD5755_SLEW_RATE_8k = 3,
0101     AD5755_SLEW_RATE_4k = 4,
0102     AD5755_SLEW_RATE_2k = 5,
0103     AD5755_SLEW_RATE_1k = 6,
0104     AD5755_SLEW_RATE_500    = 7,
0105     AD5755_SLEW_RATE_250    = 8,
0106     AD5755_SLEW_RATE_125    = 9,
0107     AD5755_SLEW_RATE_64 = 10,
0108     AD5755_SLEW_RATE_32 = 11,
0109     AD5755_SLEW_RATE_16 = 12,
0110     AD5755_SLEW_RATE_8  = 13,
0111     AD5755_SLEW_RATE_4  = 14,
0112     AD5755_SLEW_RATE_0_5    = 15,
0113 };
0114 
0115 enum ad5755_slew_step_size {
0116     AD5755_SLEW_STEP_SIZE_1 = 0,
0117     AD5755_SLEW_STEP_SIZE_2 = 1,
0118     AD5755_SLEW_STEP_SIZE_4 = 2,
0119     AD5755_SLEW_STEP_SIZE_8 = 3,
0120     AD5755_SLEW_STEP_SIZE_16 = 4,
0121     AD5755_SLEW_STEP_SIZE_32 = 5,
0122     AD5755_SLEW_STEP_SIZE_64 = 6,
0123     AD5755_SLEW_STEP_SIZE_128 = 7,
0124     AD5755_SLEW_STEP_SIZE_256 = 8,
0125 };
0126 
0127 /**
0128  * struct ad5755_platform_data - AD5755 DAC driver platform data
0129  * @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
0130  * compensation register is used.
0131  * @dc_dc_phase: DC-DC converter phase.
0132  * @dc_dc_freq: DC-DC converter frequency.
0133  * @dc_dc_maxv: DC-DC maximum allowed boost voltage.
0134  * @dac: Per DAC instance parameters.
0135  * @dac.mode: The mode to be used for the DAC output.
0136  * @dac.ext_current_sense_resistor: Whether an external current sense resistor
0137  * is used.
0138  * @dac.enable_voltage_overrange: Whether to enable 20% voltage output overrange.
0139  * @dac.slew.enable: Whether to enable digital slew.
0140  * @dac.slew.rate: Slew rate of the digital slew.
0141  * @dac.slew.step_size: Slew step size of the digital slew.
0142  **/
0143 struct ad5755_platform_data {
0144     bool ext_dc_dc_compenstation_resistor;
0145     enum ad5755_dc_dc_phase dc_dc_phase;
0146     enum ad5755_dc_dc_freq dc_dc_freq;
0147     enum ad5755_dc_dc_maxv dc_dc_maxv;
0148 
0149     struct {
0150         enum ad5755_mode mode;
0151         bool ext_current_sense_resistor;
0152         bool enable_voltage_overrange;
0153         struct {
0154             bool enable;
0155             enum ad5755_slew_rate rate;
0156             enum ad5755_slew_step_size step_size;
0157         } slew;
0158     } dac[4];
0159 };
0160 
0161 /**
0162  * struct ad5755_chip_info - chip specific information
0163  * @channel_template:   channel specification
0164  * @calib_shift:    shift for the calibration data registers
0165  * @has_voltage_out:    whether the chip has voltage outputs
0166  */
0167 struct ad5755_chip_info {
0168     const struct iio_chan_spec channel_template;
0169     unsigned int calib_shift;
0170     bool has_voltage_out;
0171 };
0172 
0173 /**
0174  * struct ad5755_state - driver instance specific data
0175  * @spi:    spi device the driver is attached to
0176  * @chip_info:  chip model specific constants, available modes etc
0177  * @pwr_down:   bitmask which contains  hether a channel is powered down or not
0178  * @ctrl:   software shadow of the channel ctrl registers
0179  * @channels:   iio channel spec for the device
0180  * @lock:   lock to protect the data buffer during SPI ops
0181  * @data:   spi transfer buffers
0182  */
0183 struct ad5755_state {
0184     struct spi_device       *spi;
0185     const struct ad5755_chip_info   *chip_info;
0186     unsigned int            pwr_down;
0187     unsigned int            ctrl[AD5755_NUM_CHANNELS];
0188     struct iio_chan_spec        channels[AD5755_NUM_CHANNELS];
0189     struct mutex            lock;
0190 
0191     /*
0192      * DMA (thus cache coherency maintenance) may require the
0193      * transfer buffers to live in their own cache lines.
0194      */
0195 
0196     union {
0197         __be32 d32;
0198         u8 d8[4];
0199     } data[2] __aligned(IIO_DMA_MINALIGN);
0200 };
0201 
0202 enum ad5755_type {
0203     ID_AD5755,
0204     ID_AD5757,
0205     ID_AD5735,
0206     ID_AD5737,
0207 };
0208 
0209 static const int ad5755_dcdc_freq_table[][2] = {
0210     { 250000, AD5755_DC_DC_FREQ_250kHZ },
0211     { 410000, AD5755_DC_DC_FREQ_410kHZ },
0212     { 650000, AD5755_DC_DC_FREQ_650kHZ }
0213 };
0214 
0215 static const int ad5755_dcdc_maxv_table[][2] = {
0216     { 23000000, AD5755_DC_DC_MAXV_23V },
0217     { 24500000, AD5755_DC_DC_MAXV_24V5 },
0218     { 27000000, AD5755_DC_DC_MAXV_27V },
0219     { 29500000, AD5755_DC_DC_MAXV_29V5 },
0220 };
0221 
0222 static const int ad5755_slew_rate_table[][2] = {
0223     { 64000, AD5755_SLEW_RATE_64k },
0224     { 32000, AD5755_SLEW_RATE_32k },
0225     { 16000, AD5755_SLEW_RATE_16k },
0226     { 8000, AD5755_SLEW_RATE_8k },
0227     { 4000, AD5755_SLEW_RATE_4k },
0228     { 2000, AD5755_SLEW_RATE_2k },
0229     { 1000, AD5755_SLEW_RATE_1k },
0230     { 500, AD5755_SLEW_RATE_500 },
0231     { 250, AD5755_SLEW_RATE_250 },
0232     { 125, AD5755_SLEW_RATE_125 },
0233     { 64, AD5755_SLEW_RATE_64 },
0234     { 32, AD5755_SLEW_RATE_32 },
0235     { 16, AD5755_SLEW_RATE_16 },
0236     { 8, AD5755_SLEW_RATE_8 },
0237     { 4, AD5755_SLEW_RATE_4 },
0238     { 0, AD5755_SLEW_RATE_0_5 },
0239 };
0240 
0241 static const int ad5755_slew_step_table[][2] = {
0242     { 256, AD5755_SLEW_STEP_SIZE_256 },
0243     { 128, AD5755_SLEW_STEP_SIZE_128 },
0244     { 64, AD5755_SLEW_STEP_SIZE_64 },
0245     { 32, AD5755_SLEW_STEP_SIZE_32 },
0246     { 16, AD5755_SLEW_STEP_SIZE_16 },
0247     { 4, AD5755_SLEW_STEP_SIZE_4 },
0248     { 2, AD5755_SLEW_STEP_SIZE_2 },
0249     { 1, AD5755_SLEW_STEP_SIZE_1 },
0250 };
0251 
0252 static int ad5755_write_unlocked(struct iio_dev *indio_dev,
0253     unsigned int reg, unsigned int val)
0254 {
0255     struct ad5755_state *st = iio_priv(indio_dev);
0256 
0257     st->data[0].d32 = cpu_to_be32((reg << 16) | val);
0258 
0259     return spi_write(st->spi, &st->data[0].d8[1], 3);
0260 }
0261 
0262 static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
0263     unsigned int channel, unsigned int reg, unsigned int val)
0264 {
0265     return ad5755_write_unlocked(indio_dev,
0266         AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
0267 }
0268 
0269 static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
0270     unsigned int val)
0271 {
0272     struct ad5755_state *st = iio_priv(indio_dev);
0273     int ret;
0274 
0275     mutex_lock(&st->lock);
0276     ret = ad5755_write_unlocked(indio_dev, reg, val);
0277     mutex_unlock(&st->lock);
0278 
0279     return ret;
0280 }
0281 
0282 static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
0283     unsigned int reg, unsigned int val)
0284 {
0285     struct ad5755_state *st = iio_priv(indio_dev);
0286     int ret;
0287 
0288     mutex_lock(&st->lock);
0289     ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
0290     mutex_unlock(&st->lock);
0291 
0292     return ret;
0293 }
0294 
0295 static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
0296 {
0297     struct ad5755_state *st = iio_priv(indio_dev);
0298     int ret;
0299     struct spi_transfer t[] = {
0300         {
0301             .tx_buf = &st->data[0].d8[1],
0302             .len = 3,
0303             .cs_change = 1,
0304         }, {
0305             .tx_buf = &st->data[1].d8[1],
0306             .rx_buf = &st->data[1].d8[1],
0307             .len = 3,
0308         },
0309     };
0310 
0311     mutex_lock(&st->lock);
0312 
0313     st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
0314     st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
0315 
0316     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0317     if (ret >= 0)
0318         ret = be32_to_cpu(st->data[1].d32) & 0xffff;
0319 
0320     mutex_unlock(&st->lock);
0321 
0322     return ret;
0323 }
0324 
0325 static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
0326     unsigned int channel, unsigned int set, unsigned int clr)
0327 {
0328     struct ad5755_state *st = iio_priv(indio_dev);
0329     int ret;
0330 
0331     st->ctrl[channel] |= set;
0332     st->ctrl[channel] &= ~clr;
0333 
0334     ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
0335         AD5755_CTRL_REG_DAC, st->ctrl[channel]);
0336 
0337     return ret;
0338 }
0339 
0340 static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
0341     unsigned int channel, bool pwr_down)
0342 {
0343     struct ad5755_state *st = iio_priv(indio_dev);
0344     unsigned int mask = BIT(channel);
0345 
0346     mutex_lock(&st->lock);
0347 
0348     if ((bool)(st->pwr_down & mask) == pwr_down)
0349         goto out_unlock;
0350 
0351     if (!pwr_down) {
0352         st->pwr_down &= ~mask;
0353         ad5755_update_dac_ctrl(indio_dev, channel,
0354             AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
0355         udelay(200);
0356         ad5755_update_dac_ctrl(indio_dev, channel,
0357             AD5755_DAC_OUT_EN, 0);
0358     } else {
0359         st->pwr_down |= mask;
0360         ad5755_update_dac_ctrl(indio_dev, channel,
0361             0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
0362                 AD5755_DAC_DC_DC_EN);
0363     }
0364 
0365 out_unlock:
0366     mutex_unlock(&st->lock);
0367 
0368     return 0;
0369 }
0370 
0371 static const int ad5755_min_max_table[][2] = {
0372     [AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
0373     [AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
0374     [AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
0375     [AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
0376     [AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
0377     [AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
0378     [AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
0379 };
0380 
0381 static void ad5755_get_min_max(struct ad5755_state *st,
0382     struct iio_chan_spec const *chan, int *min, int *max)
0383 {
0384     enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
0385     *min = ad5755_min_max_table[mode][0];
0386     *max = ad5755_min_max_table[mode][1];
0387 }
0388 
0389 static inline int ad5755_get_offset(struct ad5755_state *st,
0390     struct iio_chan_spec const *chan)
0391 {
0392     int min, max;
0393 
0394     ad5755_get_min_max(st, chan, &min, &max);
0395     return (min * (1 << chan->scan_type.realbits)) / (max - min);
0396 }
0397 
0398 static int ad5755_chan_reg_info(struct ad5755_state *st,
0399     struct iio_chan_spec const *chan, long info, bool write,
0400     unsigned int *reg, unsigned int *shift, unsigned int *offset)
0401 {
0402     switch (info) {
0403     case IIO_CHAN_INFO_RAW:
0404         if (write)
0405             *reg = AD5755_WRITE_REG_DATA(chan->address);
0406         else
0407             *reg = AD5755_READ_REG_DATA(chan->address);
0408         *shift = chan->scan_type.shift;
0409         *offset = 0;
0410         break;
0411     case IIO_CHAN_INFO_CALIBBIAS:
0412         if (write)
0413             *reg = AD5755_WRITE_REG_OFFSET(chan->address);
0414         else
0415             *reg = AD5755_READ_REG_OFFSET(chan->address);
0416         *shift = st->chip_info->calib_shift;
0417         *offset = 32768;
0418         break;
0419     case IIO_CHAN_INFO_CALIBSCALE:
0420         if (write)
0421             *reg =  AD5755_WRITE_REG_GAIN(chan->address);
0422         else
0423             *reg =  AD5755_READ_REG_GAIN(chan->address);
0424         *shift = st->chip_info->calib_shift;
0425         *offset = 0;
0426         break;
0427     default:
0428         return -EINVAL;
0429     }
0430 
0431     return 0;
0432 }
0433 
0434 static int ad5755_read_raw(struct iio_dev *indio_dev,
0435     const struct iio_chan_spec *chan, int *val, int *val2, long info)
0436 {
0437     struct ad5755_state *st = iio_priv(indio_dev);
0438     unsigned int reg, shift, offset;
0439     int min, max;
0440     int ret;
0441 
0442     switch (info) {
0443     case IIO_CHAN_INFO_SCALE:
0444         ad5755_get_min_max(st, chan, &min, &max);
0445         *val = max - min;
0446         *val2 = chan->scan_type.realbits;
0447         return IIO_VAL_FRACTIONAL_LOG2;
0448     case IIO_CHAN_INFO_OFFSET:
0449         *val = ad5755_get_offset(st, chan);
0450         return IIO_VAL_INT;
0451     default:
0452         ret = ad5755_chan_reg_info(st, chan, info, false,
0453                         &reg, &shift, &offset);
0454         if (ret)
0455             return ret;
0456 
0457         ret = ad5755_read(indio_dev, reg);
0458         if (ret < 0)
0459             return ret;
0460 
0461         *val = (ret - offset) >> shift;
0462 
0463         return IIO_VAL_INT;
0464     }
0465 
0466     return -EINVAL;
0467 }
0468 
0469 static int ad5755_write_raw(struct iio_dev *indio_dev,
0470     const struct iio_chan_spec *chan, int val, int val2, long info)
0471 {
0472     struct ad5755_state *st = iio_priv(indio_dev);
0473     unsigned int shift, reg, offset;
0474     int ret;
0475 
0476     ret = ad5755_chan_reg_info(st, chan, info, true,
0477                     &reg, &shift, &offset);
0478     if (ret)
0479         return ret;
0480 
0481     val <<= shift;
0482     val += offset;
0483 
0484     if (val < 0 || val > 0xffff)
0485         return -EINVAL;
0486 
0487     return ad5755_write(indio_dev, reg, val);
0488 }
0489 
0490 static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
0491     const struct iio_chan_spec *chan, char *buf)
0492 {
0493     struct ad5755_state *st = iio_priv(indio_dev);
0494 
0495     return sysfs_emit(buf, "%d\n",
0496               (bool)(st->pwr_down & (1 << chan->channel)));
0497 }
0498 
0499 static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
0500     struct iio_chan_spec const *chan, const char *buf, size_t len)
0501 {
0502     bool pwr_down;
0503     int ret;
0504 
0505     ret = kstrtobool(buf, &pwr_down);
0506     if (ret)
0507         return ret;
0508 
0509     ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
0510     return ret ? ret : len;
0511 }
0512 
0513 static const struct iio_info ad5755_info = {
0514     .read_raw = ad5755_read_raw,
0515     .write_raw = ad5755_write_raw,
0516 };
0517 
0518 static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
0519     {
0520         .name = "powerdown",
0521         .read = ad5755_read_powerdown,
0522         .write = ad5755_write_powerdown,
0523         .shared = IIO_SEPARATE,
0524     },
0525     { },
0526 };
0527 
0528 #define AD5755_CHANNEL(_bits) {                 \
0529     .indexed = 1,                       \
0530     .output = 1,                        \
0531     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0532         BIT(IIO_CHAN_INFO_SCALE) |          \
0533         BIT(IIO_CHAN_INFO_OFFSET) |         \
0534         BIT(IIO_CHAN_INFO_CALIBSCALE) |         \
0535         BIT(IIO_CHAN_INFO_CALIBBIAS),           \
0536     .scan_type = {                      \
0537         .sign = 'u',                    \
0538         .realbits = (_bits),                \
0539         .storagebits = 16,              \
0540         .shift = 16 - (_bits),              \
0541     },                          \
0542     .ext_info = ad5755_ext_info,                \
0543 }
0544 
0545 static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
0546     [ID_AD5735] = {
0547         .channel_template = AD5755_CHANNEL(14),
0548         .has_voltage_out = true,
0549         .calib_shift = 4,
0550     },
0551     [ID_AD5737] = {
0552         .channel_template = AD5755_CHANNEL(14),
0553         .has_voltage_out = false,
0554         .calib_shift = 4,
0555     },
0556     [ID_AD5755] = {
0557         .channel_template = AD5755_CHANNEL(16),
0558         .has_voltage_out = true,
0559         .calib_shift = 0,
0560     },
0561     [ID_AD5757] = {
0562         .channel_template = AD5755_CHANNEL(16),
0563         .has_voltage_out = false,
0564         .calib_shift = 0,
0565     },
0566 };
0567 
0568 static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
0569 {
0570     switch (mode) {
0571     case AD5755_MODE_VOLTAGE_0V_5V:
0572     case AD5755_MODE_VOLTAGE_0V_10V:
0573     case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
0574     case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
0575         return st->chip_info->has_voltage_out;
0576     case AD5755_MODE_CURRENT_4mA_20mA:
0577     case AD5755_MODE_CURRENT_0mA_20mA:
0578     case AD5755_MODE_CURRENT_0mA_24mA:
0579         return true;
0580     default:
0581         return false;
0582     }
0583 }
0584 
0585 static int ad5755_setup_pdata(struct iio_dev *indio_dev,
0586                   const struct ad5755_platform_data *pdata)
0587 {
0588     struct ad5755_state *st = iio_priv(indio_dev);
0589     unsigned int val;
0590     unsigned int i;
0591     int ret;
0592 
0593     if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
0594         pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
0595         pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
0596         return -EINVAL;
0597 
0598     val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
0599     val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
0600     val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
0601     if (pdata->ext_dc_dc_compenstation_resistor)
0602         val |= AD5755_EXT_DC_DC_COMP_RES;
0603 
0604     ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
0605     if (ret < 0)
0606         return ret;
0607 
0608     for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
0609         val = pdata->dac[i].slew.step_size <<
0610             AD5755_SLEW_STEP_SIZE_SHIFT;
0611         val |= pdata->dac[i].slew.rate <<
0612             AD5755_SLEW_RATE_SHIFT;
0613         if (pdata->dac[i].slew.enable)
0614             val |= AD5755_SLEW_ENABLE;
0615 
0616         ret = ad5755_write_ctrl(indio_dev, i,
0617                     AD5755_CTRL_REG_SLEW, val);
0618         if (ret < 0)
0619             return ret;
0620     }
0621 
0622     for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
0623         if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
0624             return -EINVAL;
0625 
0626         val = 0;
0627         if (!pdata->dac[i].ext_current_sense_resistor)
0628             val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
0629         if (pdata->dac[i].enable_voltage_overrange)
0630             val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
0631         val |= pdata->dac[i].mode;
0632 
0633         ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
0634         if (ret < 0)
0635             return ret;
0636     }
0637 
0638     return 0;
0639 }
0640 
0641 static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
0642 {
0643     switch (mode) {
0644     case AD5755_MODE_VOLTAGE_0V_5V:
0645     case AD5755_MODE_VOLTAGE_0V_10V:
0646     case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
0647     case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
0648         return true;
0649     default:
0650         return false;
0651     }
0652 }
0653 
0654 static int ad5755_init_channels(struct iio_dev *indio_dev,
0655                 const struct ad5755_platform_data *pdata)
0656 {
0657     struct ad5755_state *st = iio_priv(indio_dev);
0658     struct iio_chan_spec *channels = st->channels;
0659     unsigned int i;
0660 
0661     for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
0662         channels[i] = st->chip_info->channel_template;
0663         channels[i].channel = i;
0664         channels[i].address = i;
0665         if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
0666             channels[i].type = IIO_VOLTAGE;
0667         else
0668             channels[i].type = IIO_CURRENT;
0669     }
0670 
0671     indio_dev->channels = channels;
0672 
0673     return 0;
0674 }
0675 
0676 #define AD5755_DEFAULT_DAC_PDATA { \
0677         .mode = AD5755_MODE_CURRENT_4mA_20mA, \
0678         .ext_current_sense_resistor = true, \
0679         .enable_voltage_overrange = false, \
0680         .slew = { \
0681             .enable = false, \
0682             .rate = AD5755_SLEW_RATE_64k, \
0683             .step_size = AD5755_SLEW_STEP_SIZE_1, \
0684         }, \
0685     }
0686 
0687 static const struct ad5755_platform_data ad5755_default_pdata = {
0688     .ext_dc_dc_compenstation_resistor = false,
0689     .dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
0690     .dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
0691     .dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
0692     .dac = {
0693         [0] = AD5755_DEFAULT_DAC_PDATA,
0694         [1] = AD5755_DEFAULT_DAC_PDATA,
0695         [2] = AD5755_DEFAULT_DAC_PDATA,
0696         [3] = AD5755_DEFAULT_DAC_PDATA,
0697     },
0698 };
0699 
0700 static struct ad5755_platform_data *ad5755_parse_fw(struct device *dev)
0701 {
0702     struct fwnode_handle *pp;
0703     struct ad5755_platform_data *pdata;
0704     unsigned int tmp;
0705     unsigned int tmparray[3];
0706     int devnr, i;
0707 
0708     if (!dev_fwnode(dev))
0709         return NULL;
0710 
0711     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
0712     if (!pdata)
0713         return NULL;
0714 
0715     pdata->ext_dc_dc_compenstation_resistor =
0716         device_property_read_bool(dev, "adi,ext-dc-dc-compenstation-resistor");
0717 
0718     pdata->dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE;
0719     device_property_read_u32(dev, "adi,dc-dc-phase", &pdata->dc_dc_phase);
0720 
0721     pdata->dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ;
0722     if (!device_property_read_u32(dev, "adi,dc-dc-freq-hz", &tmp)) {
0723         for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_freq_table); i++) {
0724             if (tmp == ad5755_dcdc_freq_table[i][0]) {
0725                 pdata->dc_dc_freq = ad5755_dcdc_freq_table[i][1];
0726                 break;
0727             }
0728         }
0729 
0730         if (i == ARRAY_SIZE(ad5755_dcdc_freq_table))
0731             dev_err(dev,
0732                 "adi,dc-dc-freq out of range selecting 410kHz\n");
0733     }
0734 
0735     pdata->dc_dc_maxv = AD5755_DC_DC_MAXV_23V;
0736     if (!device_property_read_u32(dev, "adi,dc-dc-max-microvolt", &tmp)) {
0737         for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_maxv_table); i++) {
0738             if (tmp == ad5755_dcdc_maxv_table[i][0]) {
0739                 pdata->dc_dc_maxv = ad5755_dcdc_maxv_table[i][1];
0740                 break;
0741             }
0742         }
0743         if (i == ARRAY_SIZE(ad5755_dcdc_maxv_table))
0744                 dev_err(dev,
0745                     "adi,dc-dc-maxv out of range selecting 23V\n");
0746     }
0747 
0748     devnr = 0;
0749     device_for_each_child_node(dev, pp) {
0750         if (devnr >= AD5755_NUM_CHANNELS) {
0751             dev_err(dev,
0752                 "There are too many channels defined in DT\n");
0753             goto error_out;
0754         }
0755 
0756         pdata->dac[devnr].mode = AD5755_MODE_CURRENT_4mA_20mA;
0757         fwnode_property_read_u32(pp, "adi,mode", &pdata->dac[devnr].mode);
0758 
0759         pdata->dac[devnr].ext_current_sense_resistor =
0760             fwnode_property_read_bool(pp, "adi,ext-current-sense-resistor");
0761 
0762         pdata->dac[devnr].enable_voltage_overrange =
0763             fwnode_property_read_bool(pp, "adi,enable-voltage-overrange");
0764 
0765         if (!fwnode_property_read_u32_array(pp, "adi,slew", tmparray, 3)) {
0766             pdata->dac[devnr].slew.enable = tmparray[0];
0767 
0768             pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
0769             for (i = 0; i < ARRAY_SIZE(ad5755_slew_rate_table); i++) {
0770                 if (tmparray[1] == ad5755_slew_rate_table[i][0]) {
0771                     pdata->dac[devnr].slew.rate =
0772                         ad5755_slew_rate_table[i][1];
0773                     break;
0774                 }
0775             }
0776             if (i == ARRAY_SIZE(ad5755_slew_rate_table))
0777                 dev_err(dev,
0778                     "channel %d slew rate out of range selecting 64kHz\n",
0779                     devnr);
0780 
0781             pdata->dac[devnr].slew.step_size = AD5755_SLEW_STEP_SIZE_1;
0782             for (i = 0; i < ARRAY_SIZE(ad5755_slew_step_table); i++) {
0783                 if (tmparray[2] == ad5755_slew_step_table[i][0]) {
0784                     pdata->dac[devnr].slew.step_size =
0785                         ad5755_slew_step_table[i][1];
0786                     break;
0787                 }
0788             }
0789             if (i == ARRAY_SIZE(ad5755_slew_step_table))
0790                 dev_err(dev,
0791                     "channel %d slew step size out of range selecting 1 LSB\n",
0792                     devnr);
0793         } else {
0794             pdata->dac[devnr].slew.enable = false;
0795             pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
0796             pdata->dac[devnr].slew.step_size =
0797                 AD5755_SLEW_STEP_SIZE_1;
0798         }
0799         devnr++;
0800     }
0801 
0802     return pdata;
0803 
0804  error_out:
0805     devm_kfree(dev, pdata);
0806     return NULL;
0807 }
0808 
0809 static int ad5755_probe(struct spi_device *spi)
0810 {
0811     enum ad5755_type type = spi_get_device_id(spi)->driver_data;
0812     const struct ad5755_platform_data *pdata;
0813     struct iio_dev *indio_dev;
0814     struct ad5755_state *st;
0815     int ret;
0816 
0817     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0818     if (indio_dev == NULL) {
0819         dev_err(&spi->dev, "Failed to allocate iio device\n");
0820         return  -ENOMEM;
0821     }
0822 
0823     st = iio_priv(indio_dev);
0824     spi_set_drvdata(spi, indio_dev);
0825 
0826     st->chip_info = &ad5755_chip_info_tbl[type];
0827     st->spi = spi;
0828     st->pwr_down = 0xf;
0829 
0830     indio_dev->name = spi_get_device_id(spi)->name;
0831     indio_dev->info = &ad5755_info;
0832     indio_dev->modes = INDIO_DIRECT_MODE;
0833     indio_dev->num_channels = AD5755_NUM_CHANNELS;
0834 
0835     mutex_init(&st->lock);
0836 
0837 
0838     pdata = ad5755_parse_fw(&spi->dev);
0839     if (!pdata) {
0840         dev_warn(&spi->dev, "no firmware provided parameters? using default\n");
0841         pdata = &ad5755_default_pdata;
0842     }
0843 
0844     ret = ad5755_init_channels(indio_dev, pdata);
0845     if (ret)
0846         return ret;
0847 
0848     ret = ad5755_setup_pdata(indio_dev, pdata);
0849     if (ret)
0850         return ret;
0851 
0852     return devm_iio_device_register(&spi->dev, indio_dev);
0853 }
0854 
0855 static const struct spi_device_id ad5755_id[] = {
0856     { "ad5755", ID_AD5755 },
0857     { "ad5755-1", ID_AD5755 },
0858     { "ad5757", ID_AD5757 },
0859     { "ad5735", ID_AD5735 },
0860     { "ad5737", ID_AD5737 },
0861     {}
0862 };
0863 MODULE_DEVICE_TABLE(spi, ad5755_id);
0864 
0865 static const struct of_device_id ad5755_of_match[] = {
0866     { .compatible = "adi,ad5755" },
0867     { .compatible = "adi,ad5755-1" },
0868     { .compatible = "adi,ad5757" },
0869     { .compatible = "adi,ad5735" },
0870     { .compatible = "adi,ad5737" },
0871     { }
0872 };
0873 MODULE_DEVICE_TABLE(of, ad5755_of_match);
0874 
0875 static struct spi_driver ad5755_driver = {
0876     .driver = {
0877         .name = "ad5755",
0878     },
0879     .probe = ad5755_probe,
0880     .id_table = ad5755_id,
0881 };
0882 module_spi_driver(ad5755_driver);
0883 
0884 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0885 MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
0886 MODULE_LICENSE("GPL v2");
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