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0007 #ifndef SPI_AD5624R_H_
0008 #define SPI_AD5624R_H_
0009
0010 #define AD5624R_DAC_CHANNELS 4
0011
0012 #define AD5624R_ADDR_DAC0 0x0
0013 #define AD5624R_ADDR_DAC1 0x1
0014 #define AD5624R_ADDR_DAC2 0x2
0015 #define AD5624R_ADDR_DAC3 0x3
0016 #define AD5624R_ADDR_ALL_DAC 0x7
0017
0018 #define AD5624R_CMD_WRITE_INPUT_N 0x0
0019 #define AD5624R_CMD_UPDATE_DAC_N 0x1
0020 #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
0021 #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_N 0x3
0022 #define AD5624R_CMD_POWERDOWN_DAC 0x4
0023 #define AD5624R_CMD_RESET 0x5
0024 #define AD5624R_CMD_LDAC_SETUP 0x6
0025 #define AD5624R_CMD_INTERNAL_REFER_SETUP 0x7
0026
0027 #define AD5624R_LDAC_PWRDN_NONE 0x0
0028 #define AD5624R_LDAC_PWRDN_1K 0x1
0029 #define AD5624R_LDAC_PWRDN_100K 0x2
0030 #define AD5624R_LDAC_PWRDN_3STATE 0x3
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0037
0038 struct ad5624r_chip_info {
0039 const struct iio_chan_spec *channels;
0040 u16 int_vref_mv;
0041 };
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0053
0054 struct ad5624r_state {
0055 struct spi_device *us;
0056 const struct ad5624r_chip_info *chip_info;
0057 struct regulator *reg;
0058 unsigned short vref_mv;
0059 unsigned pwr_down_mask;
0060 unsigned pwr_down_mode;
0061 };
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0068
0069 enum ad5624r_supported_device_ids {
0070 ID_AD5624R3,
0071 ID_AD5644R3,
0072 ID_AD5664R3,
0073 ID_AD5624R5,
0074 ID_AD5644R5,
0075 ID_AD5664R5,
0076 };
0077
0078 #endif