iio/dac/ad5592r-base.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD5592R Digital <-> Analog converters driver
0004  *
0005  * Copyright 2014-2016 Analog Devices Inc.
0006  * Author: Paul Cercueil <paul.cercueil@analog.com>
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/delay.h>
0011 #include <linux/iio/iio.h>
0012 #include <linux/module.h>
0013 #include <linux/mutex.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/gpio/driver.h>
0017 #include <linux/property.h>
0018
0019 #include <dt-bindings/iio/adi,ad5592r.h>
0020
0021 #include "ad5592r-base.h"
0022
0023 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
0024 {
0025     struct ad5592r_state *st = gpiochip_get_data(chip);
0026     int ret = 0;
0027     u8 val;
0028
0029     mutex_lock(&st->gpio_lock);
0030
0031     if (st->gpio_out & BIT(offset))
0032         val = st->gpio_val;
0033     else
0034         ret = st->ops->gpio_read(st, &val);
0035
0036     mutex_unlock(&st->gpio_lock);
0037
0038     if (ret < 0)
0039         return ret;
0040
0041     return !!(val & BIT(offset));
0042 }
0043
0044 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0045 {
0046     struct ad5592r_state *st = gpiochip_get_data(chip);
0047
0048     mutex_lock(&st->gpio_lock);
0049
0050     if (value)
0051         st->gpio_val |= BIT(offset);
0052     else
0053         st->gpio_val &= ~BIT(offset);
0054
0055     st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
0056
0057     mutex_unlock(&st->gpio_lock);
0058 }
0059
0060 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0061 {
0062     struct ad5592r_state *st = gpiochip_get_data(chip);
0063     int ret;
0064
0065     mutex_lock(&st->gpio_lock);
0066
0067     st->gpio_out &= ~BIT(offset);
0068     st->gpio_in |= BIT(offset);
0069
0070     ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
0071     if (ret < 0)
0072         goto err_unlock;
0073
0074     ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
0075
0076 err_unlock:
0077     mutex_unlock(&st->gpio_lock);
0078
0079     return ret;
0080 }
0081
0082 static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
0083                      unsigned offset, int value)
0084 {
0085     struct ad5592r_state *st = gpiochip_get_data(chip);
0086     int ret;
0087
0088     mutex_lock(&st->gpio_lock);
0089
0090     if (value)
0091         st->gpio_val |= BIT(offset);
0092     else
0093         st->gpio_val &= ~BIT(offset);
0094
0095     st->gpio_in &= ~BIT(offset);
0096     st->gpio_out |= BIT(offset);
0097
0098     ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
0099     if (ret < 0)
0100         goto err_unlock;
0101
0102     ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
0103     if (ret < 0)
0104         goto err_unlock;
0105
0106     ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
0107
0108 err_unlock:
0109     mutex_unlock(&st->gpio_lock);
0110
0111     return ret;
0112 }
0113
0114 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
0115 {
0116     struct ad5592r_state *st = gpiochip_get_data(chip);
0117
0118     if (!(st->gpio_map & BIT(offset))) {
0119         dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
0120             offset);
0121         return -ENODEV;
0122     }
0123
0124     return 0;
0125 }
0126
0127 static int ad5592r_gpio_init(struct ad5592r_state *st)
0128 {
0129     if (!st->gpio_map)
0130         return 0;
0131
0132     st->gpiochip.label = dev_name(st->dev);
0133     st->gpiochip.base = -1;
0134     st->gpiochip.ngpio = 8;
0135     st->gpiochip.parent = st->dev;
0136     st->gpiochip.can_sleep = true;
0137     st->gpiochip.direction_input = ad5592r_gpio_direction_input;
0138     st->gpiochip.direction_output = ad5592r_gpio_direction_output;
0139     st->gpiochip.get = ad5592r_gpio_get;
0140     st->gpiochip.set = ad5592r_gpio_set;
0141     st->gpiochip.request = ad5592r_gpio_request;
0142     st->gpiochip.owner = THIS_MODULE;
0143
0144     mutex_init(&st->gpio_lock);
0145
0146     return gpiochip_add_data(&st->gpiochip, st);
0147 }
0148
0149 static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
0150 {
0151     if (st->gpio_map)
0152         gpiochip_remove(&st->gpiochip);
0153 }
0154
0155 static int ad5592r_reset(struct ad5592r_state *st)
0156 {
0157     struct gpio_desc *gpio;
0158
0159     gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
0160     if (IS_ERR(gpio))
0161         return PTR_ERR(gpio);
0162
0163     if (gpio) {
0164         udelay(1);
0165         gpiod_set_value(gpio, 1);
0166     } else {
0167         mutex_lock(&st->lock);
0168         /* Writing this magic value resets the device */
0169         st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
0170         mutex_unlock(&st->lock);
0171     }
0172
0173     udelay(250);
0174
0175     return 0;
0176 }
0177
0178 static int ad5592r_get_vref(struct ad5592r_state *st)
0179 {
0180     int ret;
0181
0182     if (st->reg) {
0183         ret = regulator_get_voltage(st->reg);
0184         if (ret < 0)
0185             return ret;
0186
0187         return ret / 1000;
0188     } else {
0189         return 2500;
0190     }
0191 }
0192
0193 static int ad5592r_set_channel_modes(struct ad5592r_state *st)
0194 {
0195     const struct ad5592r_rw_ops *ops = st->ops;
0196     int ret;
0197     unsigned i;
0198     u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
0199     u16 read_back;
0200
0201     for (i = 0; i < st->num_channels; i++) {
0202         switch (st->channel_modes[i]) {
0203         case CH_MODE_DAC:
0204             dac |= BIT(i);
0205             break;
0206
0207         case CH_MODE_ADC:
0208             adc |= BIT(i);
0209             break;
0210
0211         case CH_MODE_DAC_AND_ADC:
0212             dac |= BIT(i);
0213             adc |= BIT(i);
0214             break;
0215
0216         case CH_MODE_GPIO:
0217             st->gpio_map |= BIT(i);
0218             st->gpio_in |= BIT(i); /* Default to input */
0219             break;
0220
0221         case CH_MODE_UNUSED:
0222         default:
0223             switch (st->channel_offstate[i]) {
0224             case CH_OFFSTATE_OUT_TRISTATE:
0225                 tristate |= BIT(i);
0226                 break;
0227
0228             case CH_OFFSTATE_OUT_LOW:
0229                 st->gpio_out |= BIT(i);
0230                 break;
0231
0232             case CH_OFFSTATE_OUT_HIGH:
0233                 st->gpio_out |= BIT(i);
0234                 st->gpio_val |= BIT(i);
0235                 break;
0236
0237             case CH_OFFSTATE_PULLDOWN:
0238             default:
0239                 pulldown |= BIT(i);
0240                 break;
0241             }
0242         }
0243     }
0244
0245     mutex_lock(&st->lock);
0246
0247     /* Pull down unused pins to GND */
0248     ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
0249     if (ret)
0250         goto err_unlock;
0251
0252     ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
0253     if (ret)
0254         goto err_unlock;
0255
0256     /* Configure pins that we use */
0257     ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
0258     if (ret)
0259         goto err_unlock;
0260
0261     ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
0262     if (ret)
0263         goto err_unlock;
0264
0265     ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
0266     if (ret)
0267         goto err_unlock;
0268
0269     ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
0270     if (ret)
0271         goto err_unlock;
0272
0273     ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
0274     if (ret)
0275         goto err_unlock;
0276
0277     /* Verify that we can read back at least one register */
0278     ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
0279     if (!ret && (read_back & 0xff) != adc)
0280         ret = -EIO;
0281
0282 err_unlock:
0283     mutex_unlock(&st->lock);
0284     return ret;
0285 }
0286
0287 static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
0288 {
0289     int i;
0290
0291     for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
0292         st->channel_modes[i] = CH_MODE_UNUSED;
0293
0294     return ad5592r_set_channel_modes(st);
0295 }
0296
0297 static int ad5592r_write_raw(struct iio_dev *iio_dev,
0298     struct iio_chan_spec const *chan, int val, int val2, long mask)
0299 {
0300     struct ad5592r_state *st = iio_priv(iio_dev);
0301     int ret;
0302
0303     switch (mask) {
0304     case IIO_CHAN_INFO_RAW:
0305
0306         if (val >= (1 << chan->scan_type.realbits) || val < 0)
0307             return -EINVAL;
0308
0309         if (!chan->output)
0310             return -EINVAL;
0311
0312         mutex_lock(&st->lock);
0313         ret = st->ops->write_dac(st, chan->channel, val);
0314         if (!ret)
0315             st->cached_dac[chan->channel] = val;
0316         mutex_unlock(&st->lock);
0317         return ret;
0318     case IIO_CHAN_INFO_SCALE:
0319         if (chan->type == IIO_VOLTAGE) {
0320             bool gain;
0321
0322             if (val == st->scale_avail[0][0] &&
0323                 val2 == st->scale_avail[0][1])
0324                 gain = false;
0325             else if (val == st->scale_avail[1][0] &&
0326                  val2 == st->scale_avail[1][1])
0327                 gain = true;
0328             else
0329                 return -EINVAL;
0330
0331             mutex_lock(&st->lock);
0332
0333             ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
0334                         &st->cached_gp_ctrl);
0335             if (ret < 0) {
0336                 mutex_unlock(&st->lock);
0337                 return ret;
0338             }
0339
0340             if (chan->output) {
0341                 if (gain)
0342                     st->cached_gp_ctrl |=
0343                         AD5592R_REG_CTRL_DAC_RANGE;
0344                 else
0345                     st->cached_gp_ctrl &=
0346                         ~AD5592R_REG_CTRL_DAC_RANGE;
0347             } else {
0348                 if (gain)
0349                     st->cached_gp_ctrl |=
0350                         AD5592R_REG_CTRL_ADC_RANGE;
0351                 else
0352                     st->cached_gp_ctrl &=
0353                         ~AD5592R_REG_CTRL_ADC_RANGE;
0354             }
0355
0356             ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
0357                          st->cached_gp_ctrl);
0358             mutex_unlock(&st->lock);
0359
0360             return ret;
0361         }
0362         break;
0363     default:
0364         return -EINVAL;
0365     }
0366
0367     return 0;
0368 }
0369
0370 static int ad5592r_read_raw(struct iio_dev *iio_dev,
0371                struct iio_chan_spec const *chan,
0372                int *val, int *val2, long m)
0373 {
0374     struct ad5592r_state *st = iio_priv(iio_dev);
0375     u16 read_val;
0376     int ret, mult;
0377
0378     switch (m) {
0379     case IIO_CHAN_INFO_RAW:
0380         if (!chan->output) {
0381             mutex_lock(&st->lock);
0382             ret = st->ops->read_adc(st, chan->channel, &read_val);
0383             mutex_unlock(&st->lock);
0384             if (ret)
0385                 return ret;
0386
0387             if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
0388                 dev_err(st->dev, "Error while reading channel %u\n",
0389                         chan->channel);
0390                 return -EIO;
0391             }
0392
0393             read_val &= GENMASK(11, 0);
0394
0395         } else {
0396             mutex_lock(&st->lock);
0397             read_val = st->cached_dac[chan->channel];
0398             mutex_unlock(&st->lock);
0399         }
0400
0401         dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
0402                 chan->channel, read_val);
0403
0404         *val = (int) read_val;
0405         return IIO_VAL_INT;
0406     case IIO_CHAN_INFO_SCALE:
0407         *val = ad5592r_get_vref(st);
0408
0409         if (chan->type == IIO_TEMP) {
0410             s64 tmp = *val * (3767897513LL / 25LL);
0411             *val = div_s64_rem(tmp, 1000000000LL, val2);
0412
0413             return IIO_VAL_INT_PLUS_MICRO;
0414         }
0415
0416         mutex_lock(&st->lock);
0417
0418         if (chan->output)
0419             mult = !!(st->cached_gp_ctrl &
0420                 AD5592R_REG_CTRL_DAC_RANGE);
0421         else
0422             mult = !!(st->cached_gp_ctrl &
0423                 AD5592R_REG_CTRL_ADC_RANGE);
0424
0425         mutex_unlock(&st->lock);
0426
0427         *val *= ++mult;
0428
0429         *val2 = chan->scan_type.realbits;
0430
0431         return IIO_VAL_FRACTIONAL_LOG2;
0432     case IIO_CHAN_INFO_OFFSET:
0433         ret = ad5592r_get_vref(st);
0434
0435         mutex_lock(&st->lock);
0436
0437         if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
0438             *val = (-34365 * 25) / ret;
0439         else
0440             *val = (-75365 * 25) / ret;
0441
0442         mutex_unlock(&st->lock);
0443
0444         return IIO_VAL_INT;
0445     default:
0446         return -EINVAL;
0447     }
0448 }
0449
0450 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
0451                  struct iio_chan_spec const *chan, long mask)
0452 {
0453     switch (mask) {
0454     case IIO_CHAN_INFO_SCALE:
0455         return IIO_VAL_INT_PLUS_NANO;
0456
0457     default:
0458         return IIO_VAL_INT_PLUS_MICRO;
0459     }
0460
0461     return -EINVAL;
0462 }
0463
0464 static const struct iio_info ad5592r_info = {
0465     .read_raw = ad5592r_read_raw,
0466     .write_raw = ad5592r_write_raw,
0467     .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
0468 };
0469
0470 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
0471                        uintptr_t private,
0472                        const struct iio_chan_spec *chan,
0473                        char *buf)
0474 {
0475     struct ad5592r_state *st = iio_priv(iio_dev);
0476
0477     return sprintf(buf, "%d.%09u %d.%09u\n",
0478         st->scale_avail[0][0], st->scale_avail[0][1],
0479         st->scale_avail[1][0], st->scale_avail[1][1]);
0480 }
0481
0482 static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
0483     {
0484      .name = "scale_available",
0485      .read = ad5592r_show_scale_available,
0486      .shared = IIO_SHARED_BY_TYPE,
0487      },
0488     {},
0489 };
0490
0491 static void ad5592r_setup_channel(struct iio_dev *iio_dev,
0492         struct iio_chan_spec *chan, bool output, unsigned id)
0493 {
0494     chan->type = IIO_VOLTAGE;
0495     chan->indexed = 1;
0496     chan->output = output;
0497     chan->channel = id;
0498     chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0499     chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0500     chan->scan_type.sign = 'u';
0501     chan->scan_type.realbits = 12;
0502     chan->scan_type.storagebits = 16;
0503     chan->ext_info = ad5592r_ext_info;
0504 }
0505
0506 static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
0507 {
0508     struct ad5592r_state *st = iio_priv(iio_dev);
0509     unsigned i, curr_channel = 0,
0510          num_channels = st->num_channels;
0511     struct iio_chan_spec *channels;
0512     struct fwnode_handle *child;
0513     u32 reg, tmp;
0514     int ret;
0515
0516     device_for_each_child_node(st->dev, child) {
0517         ret = fwnode_property_read_u32(child, "reg", &reg);
0518         if (ret || reg >= ARRAY_SIZE(st->channel_modes))
0519             continue;
0520
0521         ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
0522         if (!ret)
0523             st->channel_modes[reg] = tmp;
0524
0525         ret = fwnode_property_read_u32(child, "adi,off-state", &tmp);
0526         if (!ret)
0527             st->channel_offstate[reg] = tmp;
0528     }
0529
0530     channels = devm_kcalloc(st->dev,
0531             1 + 2 * num_channels, sizeof(*channels),
0532             GFP_KERNEL);
0533     if (!channels)
0534         return -ENOMEM;
0535
0536     for (i = 0; i < num_channels; i++) {
0537         switch (st->channel_modes[i]) {
0538         case CH_MODE_DAC:
0539             ad5592r_setup_channel(iio_dev, &channels[curr_channel],
0540                     true, i);
0541             curr_channel++;
0542             break;
0543
0544         case CH_MODE_ADC:
0545             ad5592r_setup_channel(iio_dev, &channels[curr_channel],
0546                     false, i);
0547             curr_channel++;
0548             break;
0549
0550         case CH_MODE_DAC_AND_ADC:
0551             ad5592r_setup_channel(iio_dev, &channels[curr_channel],
0552                     true, i);
0553             curr_channel++;
0554             ad5592r_setup_channel(iio_dev, &channels[curr_channel],
0555                     false, i);
0556             curr_channel++;
0557             break;
0558
0559         default:
0560             continue;
0561         }
0562     }
0563
0564     channels[curr_channel].type = IIO_TEMP;
0565     channels[curr_channel].channel = 8;
0566     channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0567                    BIT(IIO_CHAN_INFO_SCALE) |
0568                    BIT(IIO_CHAN_INFO_OFFSET);
0569     curr_channel++;
0570
0571     iio_dev->num_channels = curr_channel;
0572     iio_dev->channels = channels;
0573
0574     return 0;
0575 }
0576
0577 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
0578 {
0579     s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
0580
0581     st->scale_avail[0][0] =
0582         div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
0583     st->scale_avail[1][0] =
0584         div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
0585 }
0586
0587 int ad5592r_probe(struct device *dev, const char *name,
0588         const struct ad5592r_rw_ops *ops)
0589 {
0590     struct iio_dev *iio_dev;
0591     struct ad5592r_state *st;
0592     int ret;
0593
0594     iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
0595     if (!iio_dev)
0596         return -ENOMEM;
0597
0598     st = iio_priv(iio_dev);
0599     st->dev = dev;
0600     st->ops = ops;
0601     st->num_channels = 8;
0602     dev_set_drvdata(dev, iio_dev);
0603
0604     st->reg = devm_regulator_get_optional(dev, "vref");
0605     if (IS_ERR(st->reg)) {
0606         if ((PTR_ERR(st->reg) != -ENODEV) && dev_fwnode(dev))
0607             return PTR_ERR(st->reg);
0608
0609         st->reg = NULL;
0610     } else {
0611         ret = regulator_enable(st->reg);
0612         if (ret)
0613             return ret;
0614     }
0615
0616     iio_dev->name = name;
0617     iio_dev->info = &ad5592r_info;
0618     iio_dev->modes = INDIO_DIRECT_MODE;
0619
0620     mutex_init(&st->lock);
0621
0622     ad5592r_init_scales(st, ad5592r_get_vref(st));
0623
0624     ret = ad5592r_reset(st);
0625     if (ret)
0626         goto error_disable_reg;
0627
0628     ret = ops->reg_write(st, AD5592R_REG_PD,
0629              (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
0630     if (ret)
0631         goto error_disable_reg;
0632
0633     ret = ad5592r_alloc_channels(iio_dev);
0634     if (ret)
0635         goto error_disable_reg;
0636
0637     ret = ad5592r_set_channel_modes(st);
0638     if (ret)
0639         goto error_reset_ch_modes;
0640
0641     ret = iio_device_register(iio_dev);
0642     if (ret)
0643         goto error_reset_ch_modes;
0644
0645     ret = ad5592r_gpio_init(st);
0646     if (ret)
0647         goto error_dev_unregister;
0648
0649     return 0;
0650
0651 error_dev_unregister:
0652     iio_device_unregister(iio_dev);
0653
0654 error_reset_ch_modes:
0655     ad5592r_reset_channel_modes(st);
0656
0657 error_disable_reg:
0658     if (st->reg)
0659         regulator_disable(st->reg);
0660
0661     return ret;
0662 }
0663 EXPORT_SYMBOL_NS_GPL(ad5592r_probe, IIO_AD5592R);
0664
0665 void ad5592r_remove(struct device *dev)
0666 {
0667     struct iio_dev *iio_dev = dev_get_drvdata(dev);
0668     struct ad5592r_state *st = iio_priv(iio_dev);
0669
0670     iio_device_unregister(iio_dev);
0671     ad5592r_reset_channel_modes(st);
0672     ad5592r_gpio_cleanup(st);
0673
0674     if (st->reg)
0675         regulator_disable(st->reg);
0676 }
0677 EXPORT_SYMBOL_NS_GPL(ad5592r_remove, IIO_AD5592R);
0678
0679 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
0680 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
0681 MODULE_LICENSE("GPL v2");