iio/dac/ad5421.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD5421 Digital to analog converters  driver
0004  *
0005  * Copyright 2011 Analog Devices Inc.
0006  */
0007
0008 #include <linux/device.h>
0009 #include <linux/delay.h>
0010 #include <linux/err.h>
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/kernel.h>
0014 #include <linux/spi/spi.h>
0015 #include <linux/slab.h>
0016 #include <linux/sysfs.h>
0017
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 #include <linux/iio/events.h>
0021 #include <linux/iio/dac/ad5421.h>
0022
0023
0024 #define AD5421_REG_DAC_DATA     0x1
0025 #define AD5421_REG_CTRL         0x2
0026 #define AD5421_REG_OFFSET       0x3
0027 #define AD5421_REG_GAIN         0x4
0028 /* load dac and fault shared the same register number. Writing to it will cause
0029  * a dac load command, reading from it will return the fault status register */
0030 #define AD5421_REG_LOAD_DAC     0x5
0031 #define AD5421_REG_FAULT        0x5
0032 #define AD5421_REG_FORCE_ALARM_CURRENT  0x6
0033 #define AD5421_REG_RESET        0x7
0034 #define AD5421_REG_START_CONVERSION 0x8
0035 #define AD5421_REG_NOOP         0x9
0036
0037 #define AD5421_CTRL_WATCHDOG_DISABLE    BIT(12)
0038 #define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11)
0039 #define AD5421_CTRL_MIN_CURRENT     BIT(9)
0040 #define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8)
0041 #define AD5421_CTRL_ADC_ENABLE      BIT(7)
0042 #define AD5421_CTRL_PWR_DOWN_INT_VREF   BIT(6)
0043
0044 #define AD5421_FAULT_SPI            BIT(15)
0045 #define AD5421_FAULT_PEC            BIT(14)
0046 #define AD5421_FAULT_OVER_CURRENT       BIT(13)
0047 #define AD5421_FAULT_UNDER_CURRENT      BIT(12)
0048 #define AD5421_FAULT_TEMP_OVER_140      BIT(11)
0049 #define AD5421_FAULT_TEMP_OVER_100      BIT(10)
0050 #define AD5421_FAULT_UNDER_VOLTAGE_6V       BIT(9)
0051 #define AD5421_FAULT_UNDER_VOLTAGE_12V      BIT(8)
0052
0053 /* These bits will cause the fault pin to go high */
0054 #define AD5421_FAULT_TRIGGER_IRQ \
0055     (AD5421_FAULT_SPI | AD5421_FAULT_PEC | AD5421_FAULT_OVER_CURRENT | \
0056     AD5421_FAULT_UNDER_CURRENT | AD5421_FAULT_TEMP_OVER_140)
0057
0058 /**
0059  * struct ad5421_state - driver instance specific data
0060  * @spi:        spi_device
0061  * @ctrl:       control register cache
0062  * @current_range:  current range which the device is configured for
0063  * @data:       spi transfer buffers
0064  * @fault_mask:     software masking of events
0065  * @lock:       lock to protect the data buffer during SPI ops
0066  */
0067 struct ad5421_state {
0068     struct spi_device       *spi;
0069     unsigned int            ctrl;
0070     enum ad5421_current_range   current_range;
0071     unsigned int            fault_mask;
0072     struct mutex            lock;
0073
0074     /*
0075      * DMA (thus cache coherency maintenance) may require the
0076      * transfer buffers to live in their own cache lines.
0077      */
0078     union {
0079         __be32 d32;
0080         u8 d8[4];
0081     } data[2] __aligned(IIO_DMA_MINALIGN);
0082 };
0083
0084 static const struct iio_event_spec ad5421_current_event[] = {
0085     {
0086         .type = IIO_EV_TYPE_THRESH,
0087         .dir = IIO_EV_DIR_RISING,
0088         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0089             BIT(IIO_EV_INFO_ENABLE),
0090     }, {
0091         .type = IIO_EV_TYPE_THRESH,
0092         .dir = IIO_EV_DIR_FALLING,
0093         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0094             BIT(IIO_EV_INFO_ENABLE),
0095     },
0096 };
0097
0098 static const struct iio_event_spec ad5421_temp_event[] = {
0099     {
0100         .type = IIO_EV_TYPE_THRESH,
0101         .dir = IIO_EV_DIR_RISING,
0102         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0103             BIT(IIO_EV_INFO_ENABLE),
0104     },
0105 };
0106
0107 static const struct iio_chan_spec ad5421_channels[] = {
0108     {
0109         .type = IIO_CURRENT,
0110         .indexed = 1,
0111         .output = 1,
0112         .channel = 0,
0113         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0114             BIT(IIO_CHAN_INFO_CALIBSCALE) |
0115             BIT(IIO_CHAN_INFO_CALIBBIAS),
0116         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
0117             BIT(IIO_CHAN_INFO_OFFSET),
0118         .scan_type = {
0119             .sign = 'u',
0120             .realbits = 16,
0121             .storagebits = 16,
0122         },
0123         .event_spec = ad5421_current_event,
0124         .num_event_specs = ARRAY_SIZE(ad5421_current_event),
0125     },
0126     {
0127         .type = IIO_TEMP,
0128         .channel = -1,
0129         .event_spec = ad5421_temp_event,
0130         .num_event_specs = ARRAY_SIZE(ad5421_temp_event),
0131     },
0132 };
0133
0134 static int ad5421_write_unlocked(struct iio_dev *indio_dev,
0135     unsigned int reg, unsigned int val)
0136 {
0137     struct ad5421_state *st = iio_priv(indio_dev);
0138
0139     st->data[0].d32 = cpu_to_be32((reg << 16) | val);
0140
0141     return spi_write(st->spi, &st->data[0].d8[1], 3);
0142 }
0143
0144 static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg,
0145     unsigned int val)
0146 {
0147     struct ad5421_state *st = iio_priv(indio_dev);
0148     int ret;
0149
0150     mutex_lock(&st->lock);
0151     ret = ad5421_write_unlocked(indio_dev, reg, val);
0152     mutex_unlock(&st->lock);
0153
0154     return ret;
0155 }
0156
0157 static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg)
0158 {
0159     struct ad5421_state *st = iio_priv(indio_dev);
0160     int ret;
0161     struct spi_transfer t[] = {
0162         {
0163             .tx_buf = &st->data[0].d8[1],
0164             .len = 3,
0165             .cs_change = 1,
0166         }, {
0167             .rx_buf = &st->data[1].d8[1],
0168             .len = 3,
0169         },
0170     };
0171
0172     mutex_lock(&st->lock);
0173
0174     st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
0175
0176     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0177     if (ret >= 0)
0178         ret = be32_to_cpu(st->data[1].d32) & 0xffff;
0179
0180     mutex_unlock(&st->lock);
0181
0182     return ret;
0183 }
0184
0185 static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
0186     unsigned int clr)
0187 {
0188     struct ad5421_state *st = iio_priv(indio_dev);
0189     unsigned int ret;
0190
0191     mutex_lock(&st->lock);
0192
0193     st->ctrl &= ~clr;
0194     st->ctrl |= set;
0195
0196     ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl);
0197
0198     mutex_unlock(&st->lock);
0199
0200     return ret;
0201 }
0202
0203 static irqreturn_t ad5421_fault_handler(int irq, void *data)
0204 {
0205     struct iio_dev *indio_dev = data;
0206     struct ad5421_state *st = iio_priv(indio_dev);
0207     unsigned int fault;
0208     unsigned int old_fault = 0;
0209     unsigned int events;
0210
0211     fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
0212     if (!fault)
0213         return IRQ_NONE;
0214
0215     /* If we had a fault, this might mean that the DAC has lost its state
0216      * and has been reset. Make sure that the control register actually
0217      * contains what we expect it to contain. Otherwise the watchdog might
0218      * be enabled and we get watchdog timeout faults, which will render the
0219      * DAC unusable. */
0220     ad5421_update_ctrl(indio_dev, 0, 0);
0221
0222
0223     /* The fault pin stays high as long as a fault condition is present and
0224      * it is not possible to mask fault conditions. For certain fault
0225      * conditions for example like over-temperature it takes some time
0226      * until the fault condition disappears. If we would exit the interrupt
0227      * handler immediately after handling the event it would be entered
0228      * again instantly. Thus we fall back to polling in case we detect that
0229      * a interrupt condition is still present.
0230      */
0231     do {
0232         /* 0xffff is a invalid value for the register and will only be
0233          * read if there has been a communication error */
0234         if (fault == 0xffff)
0235             fault = 0;
0236
0237         /* we are only interested in new events */
0238         events = (old_fault ^ fault) & fault;
0239         events &= st->fault_mask;
0240
0241         if (events & AD5421_FAULT_OVER_CURRENT) {
0242             iio_push_event(indio_dev,
0243                 IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
0244                     0,
0245                     IIO_EV_TYPE_THRESH,
0246                     IIO_EV_DIR_RISING),
0247             iio_get_time_ns(indio_dev));
0248         }
0249
0250         if (events & AD5421_FAULT_UNDER_CURRENT) {
0251             iio_push_event(indio_dev,
0252                 IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
0253                     0,
0254                     IIO_EV_TYPE_THRESH,
0255                     IIO_EV_DIR_FALLING),
0256                 iio_get_time_ns(indio_dev));
0257         }
0258
0259         if (events & AD5421_FAULT_TEMP_OVER_140) {
0260             iio_push_event(indio_dev,
0261                 IIO_UNMOD_EVENT_CODE(IIO_TEMP,
0262                     0,
0263                     IIO_EV_TYPE_MAG,
0264                     IIO_EV_DIR_RISING),
0265                 iio_get_time_ns(indio_dev));
0266         }
0267
0268         old_fault = fault;
0269         fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
0270
0271         /* still active? go to sleep for some time */
0272         if (fault & AD5421_FAULT_TRIGGER_IRQ)
0273             msleep(1000);
0274
0275     } while (fault & AD5421_FAULT_TRIGGER_IRQ);
0276
0277
0278     return IRQ_HANDLED;
0279 }
0280
0281 static void ad5421_get_current_min_max(struct ad5421_state *st,
0282     unsigned int *min, unsigned int *max)
0283 {
0284     /* The current range is configured using external pins, which are
0285      * usually hard-wired and not run-time switchable. */
0286     switch (st->current_range) {
0287     case AD5421_CURRENT_RANGE_4mA_20mA:
0288         *min = 4000;
0289         *max = 20000;
0290         break;
0291     case AD5421_CURRENT_RANGE_3mA8_21mA:
0292         *min = 3800;
0293         *max = 21000;
0294         break;
0295     case AD5421_CURRENT_RANGE_3mA2_24mA:
0296         *min = 3200;
0297         *max = 24000;
0298         break;
0299     default:
0300         *min = 0;
0301         *max = 1;
0302         break;
0303     }
0304 }
0305
0306 static inline unsigned int ad5421_get_offset(struct ad5421_state *st)
0307 {
0308     unsigned int min, max;
0309
0310     ad5421_get_current_min_max(st, &min, &max);
0311     return (min * (1 << 16)) / (max - min);
0312 }
0313
0314 static int ad5421_read_raw(struct iio_dev *indio_dev,
0315     struct iio_chan_spec const *chan, int *val, int *val2, long m)
0316 {
0317     struct ad5421_state *st = iio_priv(indio_dev);
0318     unsigned int min, max;
0319     int ret;
0320
0321     if (chan->type != IIO_CURRENT)
0322         return -EINVAL;
0323
0324     switch (m) {
0325     case IIO_CHAN_INFO_RAW:
0326         ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
0327         if (ret < 0)
0328             return ret;
0329         *val = ret;
0330         return IIO_VAL_INT;
0331     case IIO_CHAN_INFO_SCALE:
0332         ad5421_get_current_min_max(st, &min, &max);
0333         *val = max - min;
0334         *val2 = (1 << 16) * 1000;
0335         return IIO_VAL_FRACTIONAL;
0336     case IIO_CHAN_INFO_OFFSET:
0337         *val = ad5421_get_offset(st);
0338         return IIO_VAL_INT;
0339     case IIO_CHAN_INFO_CALIBBIAS:
0340         ret = ad5421_read(indio_dev, AD5421_REG_OFFSET);
0341         if (ret < 0)
0342             return ret;
0343         *val = ret - 32768;
0344         return IIO_VAL_INT;
0345     case IIO_CHAN_INFO_CALIBSCALE:
0346         ret = ad5421_read(indio_dev, AD5421_REG_GAIN);
0347         if (ret < 0)
0348             return ret;
0349         *val = ret;
0350         return IIO_VAL_INT;
0351     }
0352
0353     return -EINVAL;
0354 }
0355
0356 static int ad5421_write_raw(struct iio_dev *indio_dev,
0357     struct iio_chan_spec const *chan, int val, int val2, long mask)
0358 {
0359     const unsigned int max_val = 1 << 16;
0360
0361     switch (mask) {
0362     case IIO_CHAN_INFO_RAW:
0363         if (val >= max_val || val < 0)
0364             return -EINVAL;
0365
0366         return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val);
0367     case IIO_CHAN_INFO_CALIBBIAS:
0368         val += 32768;
0369         if (val >= max_val || val < 0)
0370             return -EINVAL;
0371
0372         return ad5421_write(indio_dev, AD5421_REG_OFFSET, val);
0373     case IIO_CHAN_INFO_CALIBSCALE:
0374         if (val >= max_val || val < 0)
0375             return -EINVAL;
0376
0377         return ad5421_write(indio_dev, AD5421_REG_GAIN, val);
0378     default:
0379         break;
0380     }
0381
0382     return -EINVAL;
0383 }
0384
0385 static int ad5421_write_event_config(struct iio_dev *indio_dev,
0386     const struct iio_chan_spec *chan, enum iio_event_type type,
0387     enum iio_event_direction dir, int state)
0388 {
0389     struct ad5421_state *st = iio_priv(indio_dev);
0390     unsigned int mask;
0391
0392     switch (chan->type) {
0393     case IIO_CURRENT:
0394         if (dir == IIO_EV_DIR_RISING)
0395             mask = AD5421_FAULT_OVER_CURRENT;
0396         else
0397             mask = AD5421_FAULT_UNDER_CURRENT;
0398         break;
0399     case IIO_TEMP:
0400         mask = AD5421_FAULT_TEMP_OVER_140;
0401         break;
0402     default:
0403         return -EINVAL;
0404     }
0405
0406     mutex_lock(&st->lock);
0407     if (state)
0408         st->fault_mask |= mask;
0409     else
0410         st->fault_mask &= ~mask;
0411     mutex_unlock(&st->lock);
0412
0413     return 0;
0414 }
0415
0416 static int ad5421_read_event_config(struct iio_dev *indio_dev,
0417     const struct iio_chan_spec *chan, enum iio_event_type type,
0418     enum iio_event_direction dir)
0419 {
0420     struct ad5421_state *st = iio_priv(indio_dev);
0421     unsigned int mask;
0422
0423     switch (chan->type) {
0424     case IIO_CURRENT:
0425         if (dir == IIO_EV_DIR_RISING)
0426             mask = AD5421_FAULT_OVER_CURRENT;
0427         else
0428             mask = AD5421_FAULT_UNDER_CURRENT;
0429         break;
0430     case IIO_TEMP:
0431         mask = AD5421_FAULT_TEMP_OVER_140;
0432         break;
0433     default:
0434         return -EINVAL;
0435     }
0436
0437     return (bool)(st->fault_mask & mask);
0438 }
0439
0440 static int ad5421_read_event_value(struct iio_dev *indio_dev,
0441     const struct iio_chan_spec *chan, enum iio_event_type type,
0442     enum iio_event_direction dir, enum iio_event_info info, int *val,
0443     int *val2)
0444 {
0445     int ret;
0446
0447     switch (chan->type) {
0448     case IIO_CURRENT:
0449         ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
0450         if (ret < 0)
0451             return ret;
0452         *val = ret;
0453         break;
0454     case IIO_TEMP:
0455         *val = 140000;
0456         break;
0457     default:
0458         return -EINVAL;
0459     }
0460
0461     return IIO_VAL_INT;
0462 }
0463
0464 static const struct iio_info ad5421_info = {
0465     .read_raw =     ad5421_read_raw,
0466     .write_raw =        ad5421_write_raw,
0467     .read_event_config =    ad5421_read_event_config,
0468     .write_event_config =   ad5421_write_event_config,
0469     .read_event_value = ad5421_read_event_value,
0470 };
0471
0472 static int ad5421_probe(struct spi_device *spi)
0473 {
0474     struct ad5421_platform_data *pdata = dev_get_platdata(&spi->dev);
0475     struct iio_dev *indio_dev;
0476     struct ad5421_state *st;
0477     int ret;
0478
0479     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0480     if (indio_dev == NULL) {
0481         dev_err(&spi->dev, "Failed to allocate iio device\n");
0482         return  -ENOMEM;
0483     }
0484
0485     st = iio_priv(indio_dev);
0486     spi_set_drvdata(spi, indio_dev);
0487
0488     st->spi = spi;
0489
0490     indio_dev->name = "ad5421";
0491     indio_dev->info = &ad5421_info;
0492     indio_dev->modes = INDIO_DIRECT_MODE;
0493     indio_dev->channels = ad5421_channels;
0494     indio_dev->num_channels = ARRAY_SIZE(ad5421_channels);
0495
0496     mutex_init(&st->lock);
0497
0498     st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE |
0499             AD5421_CTRL_AUTO_FAULT_READBACK;
0500
0501     if (pdata) {
0502         st->current_range = pdata->current_range;
0503         if (pdata->external_vref)
0504             st->ctrl |= AD5421_CTRL_PWR_DOWN_INT_VREF;
0505     } else {
0506         st->current_range = AD5421_CURRENT_RANGE_4mA_20mA;
0507     }
0508
0509     /* write initial ctrl register value */
0510     ad5421_update_ctrl(indio_dev, 0, 0);
0511
0512     if (spi->irq) {
0513         ret = devm_request_threaded_irq(&spi->dev, spi->irq,
0514                        NULL,
0515                        ad5421_fault_handler,
0516                        IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
0517                        "ad5421 fault",
0518                        indio_dev);
0519         if (ret)
0520             return ret;
0521     }
0522
0523     return devm_iio_device_register(&spi->dev, indio_dev);
0524 }
0525
0526 static struct spi_driver ad5421_driver = {
0527     .driver = {
0528            .name = "ad5421",
0529     },
0530     .probe = ad5421_probe,
0531 };
0532 module_spi_driver(ad5421_driver);
0533
0534 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0535 MODULE_DESCRIPTION("Analog Devices AD5421 DAC");
0536 MODULE_LICENSE("GPL v2");
0537 MODULE_ALIAS("spi:ad5421");