0001
0002
0003
0004
0005
0006
0007
0008
0009 #include <linux/device.h>
0010 #include <linux/err.h>
0011 #include <linux/module.h>
0012 #include <linux/kernel.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/slab.h>
0015 #include <linux/sysfs.h>
0016 #include <linux/regulator/consumer.h>
0017
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020
0021 #define AD5360_CMD(x) ((x) << 22)
0022 #define AD5360_ADDR(x) ((x) << 16)
0023
0024 #define AD5360_READBACK_TYPE(x) ((x) << 13)
0025 #define AD5360_READBACK_ADDR(x) ((x) << 7)
0026
0027 #define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
0028
0029 #define AD5360_CMD_WRITE_DATA 0x3
0030 #define AD5360_CMD_WRITE_OFFSET 0x2
0031 #define AD5360_CMD_WRITE_GAIN 0x1
0032 #define AD5360_CMD_SPECIAL_FUNCTION 0x0
0033
0034
0035 #define AD5360_REG_SF_NOP 0x0
0036 #define AD5360_REG_SF_CTRL 0x1
0037 #define AD5360_REG_SF_OFS(x) (0x2 + (x))
0038 #define AD5360_REG_SF_READBACK 0x5
0039
0040 #define AD5360_SF_CTRL_PWR_DOWN BIT(0)
0041
0042 #define AD5360_READBACK_X1A 0x0
0043 #define AD5360_READBACK_X1B 0x1
0044 #define AD5360_READBACK_OFFSET 0x2
0045 #define AD5360_READBACK_GAIN 0x3
0046 #define AD5360_READBACK_SF 0x4
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057 struct ad5360_chip_info {
0058 struct iio_chan_spec channel_template;
0059 unsigned int num_channels;
0060 unsigned int channels_per_group;
0061 unsigned int num_vrefs;
0062 };
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074 struct ad5360_state {
0075 struct spi_device *spi;
0076 const struct ad5360_chip_info *chip_info;
0077 struct regulator_bulk_data vref_reg[3];
0078 unsigned int ctrl;
0079 struct mutex lock;
0080
0081
0082
0083
0084
0085 union {
0086 __be32 d32;
0087 u8 d8[4];
0088 } data[2] __aligned(IIO_DMA_MINALIGN);
0089 };
0090
0091 enum ad5360_type {
0092 ID_AD5360,
0093 ID_AD5361,
0094 ID_AD5362,
0095 ID_AD5363,
0096 ID_AD5370,
0097 ID_AD5371,
0098 ID_AD5372,
0099 ID_AD5373,
0100 };
0101
0102 #define AD5360_CHANNEL(bits) { \
0103 .type = IIO_VOLTAGE, \
0104 .indexed = 1, \
0105 .output = 1, \
0106 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0107 BIT(IIO_CHAN_INFO_SCALE) | \
0108 BIT(IIO_CHAN_INFO_OFFSET) | \
0109 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
0110 BIT(IIO_CHAN_INFO_CALIBBIAS), \
0111 .scan_type = { \
0112 .sign = 'u', \
0113 .realbits = (bits), \
0114 .storagebits = 16, \
0115 .shift = 16 - (bits), \
0116 }, \
0117 }
0118
0119 static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
0120 [ID_AD5360] = {
0121 .channel_template = AD5360_CHANNEL(16),
0122 .num_channels = 16,
0123 .channels_per_group = 8,
0124 .num_vrefs = 2,
0125 },
0126 [ID_AD5361] = {
0127 .channel_template = AD5360_CHANNEL(14),
0128 .num_channels = 16,
0129 .channels_per_group = 8,
0130 .num_vrefs = 2,
0131 },
0132 [ID_AD5362] = {
0133 .channel_template = AD5360_CHANNEL(16),
0134 .num_channels = 8,
0135 .channels_per_group = 4,
0136 .num_vrefs = 2,
0137 },
0138 [ID_AD5363] = {
0139 .channel_template = AD5360_CHANNEL(14),
0140 .num_channels = 8,
0141 .channels_per_group = 4,
0142 .num_vrefs = 2,
0143 },
0144 [ID_AD5370] = {
0145 .channel_template = AD5360_CHANNEL(16),
0146 .num_channels = 40,
0147 .channels_per_group = 8,
0148 .num_vrefs = 2,
0149 },
0150 [ID_AD5371] = {
0151 .channel_template = AD5360_CHANNEL(14),
0152 .num_channels = 40,
0153 .channels_per_group = 8,
0154 .num_vrefs = 3,
0155 },
0156 [ID_AD5372] = {
0157 .channel_template = AD5360_CHANNEL(16),
0158 .num_channels = 32,
0159 .channels_per_group = 8,
0160 .num_vrefs = 2,
0161 },
0162 [ID_AD5373] = {
0163 .channel_template = AD5360_CHANNEL(14),
0164 .num_channels = 32,
0165 .channels_per_group = 8,
0166 .num_vrefs = 2,
0167 },
0168 };
0169
0170 static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
0171 unsigned int channel)
0172 {
0173 unsigned int i;
0174
0175
0176
0177 i = channel / st->chip_info->channels_per_group;
0178 if (i >= st->chip_info->num_vrefs)
0179 i = st->chip_info->num_vrefs - 1;
0180
0181 return i;
0182 }
0183
0184 static int ad5360_get_channel_vref(struct ad5360_state *st,
0185 unsigned int channel)
0186 {
0187 unsigned int i = ad5360_get_channel_vref_index(st, channel);
0188
0189 return regulator_get_voltage(st->vref_reg[i].consumer);
0190 }
0191
0192
0193 static int ad5360_write_unlocked(struct iio_dev *indio_dev,
0194 unsigned int cmd, unsigned int addr, unsigned int val,
0195 unsigned int shift)
0196 {
0197 struct ad5360_state *st = iio_priv(indio_dev);
0198
0199 val <<= shift;
0200 val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
0201 st->data[0].d32 = cpu_to_be32(val);
0202
0203 return spi_write(st->spi, &st->data[0].d8[1], 3);
0204 }
0205
0206 static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
0207 unsigned int addr, unsigned int val, unsigned int shift)
0208 {
0209 int ret;
0210 struct ad5360_state *st = iio_priv(indio_dev);
0211
0212 mutex_lock(&st->lock);
0213 ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
0214 mutex_unlock(&st->lock);
0215
0216 return ret;
0217 }
0218
0219 static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
0220 unsigned int addr)
0221 {
0222 struct ad5360_state *st = iio_priv(indio_dev);
0223 int ret;
0224 struct spi_transfer t[] = {
0225 {
0226 .tx_buf = &st->data[0].d8[1],
0227 .len = 3,
0228 .cs_change = 1,
0229 }, {
0230 .rx_buf = &st->data[1].d8[1],
0231 .len = 3,
0232 },
0233 };
0234
0235 mutex_lock(&st->lock);
0236
0237 st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
0238 AD5360_ADDR(AD5360_REG_SF_READBACK) |
0239 AD5360_READBACK_TYPE(type) |
0240 AD5360_READBACK_ADDR(addr));
0241
0242 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0243 if (ret >= 0)
0244 ret = be32_to_cpu(st->data[1].d32) & 0xffff;
0245
0246 mutex_unlock(&st->lock);
0247
0248 return ret;
0249 }
0250
0251 static ssize_t ad5360_read_dac_powerdown(struct device *dev,
0252 struct device_attribute *attr,
0253 char *buf)
0254 {
0255 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0256 struct ad5360_state *st = iio_priv(indio_dev);
0257
0258 return sysfs_emit(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
0259 }
0260
0261 static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
0262 unsigned int clr)
0263 {
0264 struct ad5360_state *st = iio_priv(indio_dev);
0265 unsigned int ret;
0266
0267 mutex_lock(&st->lock);
0268
0269 st->ctrl |= set;
0270 st->ctrl &= ~clr;
0271
0272 ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
0273 AD5360_REG_SF_CTRL, st->ctrl, 0);
0274
0275 mutex_unlock(&st->lock);
0276
0277 return ret;
0278 }
0279
0280 static ssize_t ad5360_write_dac_powerdown(struct device *dev,
0281 struct device_attribute *attr, const char *buf, size_t len)
0282 {
0283 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0284 bool pwr_down;
0285 int ret;
0286
0287 ret = kstrtobool(buf, &pwr_down);
0288 if (ret)
0289 return ret;
0290
0291 if (pwr_down)
0292 ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
0293 else
0294 ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
0295
0296 return ret ? ret : len;
0297 }
0298
0299 static IIO_DEVICE_ATTR(out_voltage_powerdown,
0300 S_IRUGO | S_IWUSR,
0301 ad5360_read_dac_powerdown,
0302 ad5360_write_dac_powerdown, 0);
0303
0304 static struct attribute *ad5360_attributes[] = {
0305 &iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
0306 NULL,
0307 };
0308
0309 static const struct attribute_group ad5360_attribute_group = {
0310 .attrs = ad5360_attributes,
0311 };
0312
0313 static int ad5360_write_raw(struct iio_dev *indio_dev,
0314 struct iio_chan_spec const *chan,
0315 int val,
0316 int val2,
0317 long mask)
0318 {
0319 struct ad5360_state *st = iio_priv(indio_dev);
0320 int max_val = (1 << chan->scan_type.realbits);
0321 unsigned int ofs_index;
0322
0323 switch (mask) {
0324 case IIO_CHAN_INFO_RAW:
0325 if (val >= max_val || val < 0)
0326 return -EINVAL;
0327
0328 return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
0329 chan->address, val, chan->scan_type.shift);
0330
0331 case IIO_CHAN_INFO_CALIBBIAS:
0332 if (val >= max_val || val < 0)
0333 return -EINVAL;
0334
0335 return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
0336 chan->address, val, chan->scan_type.shift);
0337
0338 case IIO_CHAN_INFO_CALIBSCALE:
0339 if (val >= max_val || val < 0)
0340 return -EINVAL;
0341
0342 return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
0343 chan->address, val, chan->scan_type.shift);
0344
0345 case IIO_CHAN_INFO_OFFSET:
0346 if (val <= -max_val || val > 0)
0347 return -EINVAL;
0348
0349 val = -val;
0350
0351
0352
0353
0354 val >>= (chan->scan_type.realbits - 14);
0355
0356
0357
0358
0359 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
0360 return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
0361 AD5360_REG_SF_OFS(ofs_index), val, 0);
0362 default:
0363 break;
0364 }
0365
0366 return -EINVAL;
0367 }
0368
0369 static int ad5360_read_raw(struct iio_dev *indio_dev,
0370 struct iio_chan_spec const *chan,
0371 int *val,
0372 int *val2,
0373 long m)
0374 {
0375 struct ad5360_state *st = iio_priv(indio_dev);
0376 unsigned int ofs_index;
0377 int scale_uv;
0378 int ret;
0379
0380 switch (m) {
0381 case IIO_CHAN_INFO_RAW:
0382 ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
0383 chan->address);
0384 if (ret < 0)
0385 return ret;
0386 *val = ret >> chan->scan_type.shift;
0387 return IIO_VAL_INT;
0388 case IIO_CHAN_INFO_SCALE:
0389 scale_uv = ad5360_get_channel_vref(st, chan->channel);
0390 if (scale_uv < 0)
0391 return scale_uv;
0392
0393
0394 *val = scale_uv * 4 / 1000;
0395 *val2 = chan->scan_type.realbits;
0396 return IIO_VAL_FRACTIONAL_LOG2;
0397 case IIO_CHAN_INFO_CALIBBIAS:
0398 ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
0399 chan->address);
0400 if (ret < 0)
0401 return ret;
0402 *val = ret;
0403 return IIO_VAL_INT;
0404 case IIO_CHAN_INFO_CALIBSCALE:
0405 ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
0406 chan->address);
0407 if (ret < 0)
0408 return ret;
0409 *val = ret;
0410 return IIO_VAL_INT;
0411 case IIO_CHAN_INFO_OFFSET:
0412 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
0413 ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
0414 AD5360_REG_SF_OFS(ofs_index));
0415 if (ret < 0)
0416 return ret;
0417
0418 ret <<= (chan->scan_type.realbits - 14);
0419 *val = -ret;
0420 return IIO_VAL_INT;
0421 }
0422
0423 return -EINVAL;
0424 }
0425
0426 static const struct iio_info ad5360_info = {
0427 .read_raw = ad5360_read_raw,
0428 .write_raw = ad5360_write_raw,
0429 .attrs = &ad5360_attribute_group,
0430 };
0431
0432 static const char * const ad5360_vref_name[] = {
0433 "vref0", "vref1", "vref2"
0434 };
0435
0436 static int ad5360_alloc_channels(struct iio_dev *indio_dev)
0437 {
0438 struct ad5360_state *st = iio_priv(indio_dev);
0439 struct iio_chan_spec *channels;
0440 unsigned int i;
0441
0442 channels = kcalloc(st->chip_info->num_channels,
0443 sizeof(struct iio_chan_spec), GFP_KERNEL);
0444
0445 if (!channels)
0446 return -ENOMEM;
0447
0448 for (i = 0; i < st->chip_info->num_channels; ++i) {
0449 channels[i] = st->chip_info->channel_template;
0450 channels[i].channel = i;
0451 channels[i].address = AD5360_CHAN_ADDR(i);
0452 }
0453
0454 indio_dev->channels = channels;
0455
0456 return 0;
0457 }
0458
0459 static int ad5360_probe(struct spi_device *spi)
0460 {
0461 enum ad5360_type type = spi_get_device_id(spi)->driver_data;
0462 struct iio_dev *indio_dev;
0463 struct ad5360_state *st;
0464 unsigned int i;
0465 int ret;
0466
0467 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0468 if (indio_dev == NULL) {
0469 dev_err(&spi->dev, "Failed to allocate iio device\n");
0470 return -ENOMEM;
0471 }
0472
0473 st = iio_priv(indio_dev);
0474 spi_set_drvdata(spi, indio_dev);
0475
0476 st->chip_info = &ad5360_chip_info_tbl[type];
0477 st->spi = spi;
0478
0479 indio_dev->name = spi_get_device_id(spi)->name;
0480 indio_dev->info = &ad5360_info;
0481 indio_dev->modes = INDIO_DIRECT_MODE;
0482 indio_dev->num_channels = st->chip_info->num_channels;
0483
0484 mutex_init(&st->lock);
0485
0486 ret = ad5360_alloc_channels(indio_dev);
0487 if (ret) {
0488 dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
0489 return ret;
0490 }
0491
0492 for (i = 0; i < st->chip_info->num_vrefs; ++i)
0493 st->vref_reg[i].supply = ad5360_vref_name[i];
0494
0495 ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
0496 st->vref_reg);
0497 if (ret) {
0498 dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
0499 goto error_free_channels;
0500 }
0501
0502 ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
0503 if (ret) {
0504 dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
0505 goto error_free_channels;
0506 }
0507
0508 ret = iio_device_register(indio_dev);
0509 if (ret) {
0510 dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
0511 goto error_disable_reg;
0512 }
0513
0514 return 0;
0515
0516 error_disable_reg:
0517 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
0518 error_free_channels:
0519 kfree(indio_dev->channels);
0520
0521 return ret;
0522 }
0523
0524 static void ad5360_remove(struct spi_device *spi)
0525 {
0526 struct iio_dev *indio_dev = spi_get_drvdata(spi);
0527 struct ad5360_state *st = iio_priv(indio_dev);
0528
0529 iio_device_unregister(indio_dev);
0530
0531 kfree(indio_dev->channels);
0532
0533 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
0534 }
0535
0536 static const struct spi_device_id ad5360_ids[] = {
0537 { "ad5360", ID_AD5360 },
0538 { "ad5361", ID_AD5361 },
0539 { "ad5362", ID_AD5362 },
0540 { "ad5363", ID_AD5363 },
0541 { "ad5370", ID_AD5370 },
0542 { "ad5371", ID_AD5371 },
0543 { "ad5372", ID_AD5372 },
0544 { "ad5373", ID_AD5373 },
0545 {}
0546 };
0547 MODULE_DEVICE_TABLE(spi, ad5360_ids);
0548
0549 static struct spi_driver ad5360_driver = {
0550 .driver = {
0551 .name = "ad5360",
0552 },
0553 .probe = ad5360_probe,
0554 .remove = ad5360_remove,
0555 .id_table = ad5360_ids,
0556 };
0557 module_spi_driver(ad5360_driver);
0558
0559 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0560 MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
0561 MODULE_LICENSE("GPL v2");