Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog Devices AD3552R
0004  * Digital to Analog converter driver
0005  *
0006  * Copyright 2021 Analog Devices Inc.
0007  */
0008 #include <asm/unaligned.h>
0009 #include <linux/device.h>
0010 #include <linux/iio/triggered_buffer.h>
0011 #include <linux/iio/trigger_consumer.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/kernel.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/spi/spi.h>
0016 
0017 /* Register addresses */
0018 /* Primary address space */
0019 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_A     0x00
0020 #define   AD3552R_MASK_SOFTWARE_RESET           (BIT(7) | BIT(0))
0021 #define   AD3552R_MASK_ADDR_ASCENSION           BIT(5)
0022 #define   AD3552R_MASK_SDO_ACTIVE           BIT(4)
0023 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_B     0x01
0024 #define   AD3552R_MASK_SINGLE_INST          BIT(7)
0025 #define   AD3552R_MASK_SHORT_INSTRUCTION        BIT(3)
0026 #define AD3552R_REG_ADDR_DEVICE_CONFIG          0x02
0027 #define   AD3552R_MASK_DEVICE_STATUS(n)         BIT(4 + (n))
0028 #define   AD3552R_MASK_CUSTOM_MODES         GENMASK(3, 2)
0029 #define   AD3552R_MASK_OPERATING_MODES          GENMASK(1, 0)
0030 #define AD3552R_REG_ADDR_CHIP_TYPE          0x03
0031 #define   AD3552R_MASK_CLASS                GENMASK(7, 0)
0032 #define AD3552R_REG_ADDR_PRODUCT_ID_L           0x04
0033 #define AD3552R_REG_ADDR_PRODUCT_ID_H           0x05
0034 #define AD3552R_REG_ADDR_CHIP_GRADE         0x06
0035 #define   AD3552R_MASK_GRADE                GENMASK(7, 4)
0036 #define   AD3552R_MASK_DEVICE_REVISION          GENMASK(3, 0)
0037 #define AD3552R_REG_ADDR_SCRATCH_PAD            0x0A
0038 #define AD3552R_REG_ADDR_SPI_REVISION           0x0B
0039 #define AD3552R_REG_ADDR_VENDOR_L           0x0C
0040 #define AD3552R_REG_ADDR_VENDOR_H           0x0D
0041 #define AD3552R_REG_ADDR_STREAM_MODE            0x0E
0042 #define   AD3552R_MASK_LENGTH               GENMASK(7, 0)
0043 #define AD3552R_REG_ADDR_TRANSFER_REGISTER      0x0F
0044 #define   AD3552R_MASK_MULTI_IO_MODE            GENMASK(7, 6)
0045 #define   AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE     BIT(2)
0046 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_C     0x10
0047 #define   AD3552R_MASK_CRC_ENABLE           (GENMASK(7, 6) |\
0048                              GENMASK(1, 0))
0049 #define   AD3552R_MASK_STRICT_REGISTER_ACCESS       BIT(5)
0050 #define AD3552R_REG_ADDR_INTERFACE_STATUS_A     0x11
0051 #define   AD3552R_MASK_INTERFACE_NOT_READY      BIT(7)
0052 #define   AD3552R_MASK_CLOCK_COUNTING_ERROR     BIT(5)
0053 #define   AD3552R_MASK_INVALID_OR_NO_CRC        BIT(3)
0054 #define   AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER  BIT(2)
0055 #define   AD3552R_MASK_PARTIAL_REGISTER_ACCESS      BIT(1)
0056 #define   AD3552R_MASK_REGISTER_ADDRESS_INVALID     BIT(0)
0057 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_D     0x14
0058 #define   AD3552R_MASK_ALERT_ENABLE_PULLUP      BIT(6)
0059 #define   AD3552R_MASK_MEM_CRC_EN           BIT(4)
0060 #define   AD3552R_MASK_SDO_DRIVE_STRENGTH       GENMASK(3, 2)
0061 #define   AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN     BIT(1)
0062 #define   AD3552R_MASK_SPI_CONFIG_DDR           BIT(0)
0063 #define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG        0x15
0064 #define   AD3552R_MASK_IDUMP_FAST_MODE          BIT(6)
0065 #define   AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN BIT(5)
0066 #define   AD3552R_MASK_SAMPLE_HOLD_USER_TRIM        GENMASK(4, 3)
0067 #define   AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE      BIT(2)
0068 #define   AD3552R_MASK_REFERENCE_VOLTAGE_SEL        GENMASK(1, 0)
0069 #define AD3552R_REG_ADDR_ERR_ALARM_MASK         0x16
0070 #define   AD3552R_MASK_REF_RANGE_ALARM          BIT(6)
0071 #define   AD3552R_MASK_CLOCK_COUNT_ERR_ALARM        BIT(5)
0072 #define   AD3552R_MASK_MEM_CRC_ERR_ALARM        BIT(4)
0073 #define   AD3552R_MASK_SPI_CRC_ERR_ALARM        BIT(3)
0074 #define   AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM     BIT(2)
0075 #define   AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM    BIT(1)
0076 #define   AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM   BIT(0)
0077 #define AD3552R_REG_ADDR_ERR_STATUS         0x17
0078 #define   AD3552R_MASK_REF_RANGE_ERR_STATUS         BIT(6)
0079 #define   AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS   BIT(5)
0080 #define   AD3552R_MASK_MEM_CRC_ERR_STATUS           BIT(4)
0081 #define   AD3552R_MASK_RESET_STATUS             BIT(0)
0082 #define AD3552R_REG_ADDR_POWERDOWN_CONFIG       0x18
0083 #define   AD3552R_MASK_CH_DAC_POWERDOWN(ch)     BIT(4 + (ch))
0084 #define   AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch)   BIT(ch)
0085 #define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE       0x19
0086 #define   AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch)      ((ch) ? GENMASK(7, 4) :\
0087                              GENMASK(3, 0))
0088 #define AD3552R_REG_ADDR_CH_OFFSET(ch)          (0x1B + (ch) * 2)
0089 #define   AD3552R_MASK_CH_OFFSET_BITS_0_7       GENMASK(7, 0)
0090 #define AD3552R_REG_ADDR_CH_GAIN(ch)            (0x1C + (ch) * 2)
0091 #define   AD3552R_MASK_CH_RANGE_OVERRIDE        BIT(7)
0092 #define   AD3552R_MASK_CH_GAIN_SCALING_N        GENMASK(6, 5)
0093 #define   AD3552R_MASK_CH_GAIN_SCALING_P        GENMASK(4, 3)
0094 #define   AD3552R_MASK_CH_OFFSET_POLARITY       BIT(2)
0095 #define   AD3552R_MASK_CH_OFFSET_BIT_8          BIT(0)
0096 /*
0097  * Secondary region
0098  * For multibyte registers specify the highest address because the access is
0099  * done in descending order
0100  */
0101 #define AD3552R_SECONDARY_REGION_START          0x28
0102 #define AD3552R_REG_ADDR_HW_LDAC_16B            0x28
0103 #define AD3552R_REG_ADDR_CH_DAC_16B(ch)         (0x2C - (1 - ch) * 2)
0104 #define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B      0x2E
0105 #define AD3552R_REG_ADDR_CH_SELECT_16B          0x2F
0106 #define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B        0x31
0107 #define AD3552R_REG_ADDR_SW_LDAC_16B            0x32
0108 #define AD3552R_REG_ADDR_CH_INPUT_16B(ch)       (0x36 - (1 - ch) * 2)
0109 /* 3 bytes registers */
0110 #define AD3552R_REG_START_24B               0x37
0111 #define AD3552R_REG_ADDR_HW_LDAC_24B            0x37
0112 #define AD3552R_REG_ADDR_CH_DAC_24B(ch)         (0x3D - (1 - ch) * 3)
0113 #define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B      0x40
0114 #define AD3552R_REG_ADDR_CH_SELECT_24B          0x41
0115 #define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B        0x44
0116 #define AD3552R_REG_ADDR_SW_LDAC_24B            0x45
0117 #define AD3552R_REG_ADDR_CH_INPUT_24B(ch)       (0x4B - (1 - ch) * 3)
0118 
0119 /* Useful defines */
0120 #define AD3552R_NUM_CH                  2
0121 #define AD3552R_MASK_CH(ch)             BIT(ch)
0122 #define AD3552R_MASK_ALL_CH             GENMASK(1, 0)
0123 #define AD3552R_MAX_REG_SIZE                3
0124 #define AD3552R_READ_BIT                BIT(7)
0125 #define AD3552R_ADDR_MASK               GENMASK(6, 0)
0126 #define AD3552R_MASK_DAC_12B                0xFFF0
0127 #define AD3552R_DEFAULT_CONFIG_B_VALUE          0x8
0128 #define AD3552R_SCRATCH_PAD_TEST_VAL1           0x34
0129 #define AD3552R_SCRATCH_PAD_TEST_VAL2           0xB2
0130 #define AD3552R_GAIN_SCALE              1000
0131 #define AD3552R_LDAC_PULSE_US               100
0132 
0133 enum ad3552r_ch_vref_select {
0134     /* Internal source with Vref I/O floating */
0135     AD3552R_INTERNAL_VREF_PIN_FLOATING,
0136     /* Internal source with Vref I/O at 2.5V */
0137     AD3552R_INTERNAL_VREF_PIN_2P5V,
0138     /* External source with Vref I/O as input */
0139     AD3552R_EXTERNAL_VREF_PIN_INPUT
0140 };
0141 
0142 enum ad3542r_id {
0143     AD3542R_ID = 0x4008,
0144     AD3552R_ID = 0x4009,
0145 };
0146 
0147 enum ad3552r_ch_output_range {
0148     /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
0149     AD3552R_CH_OUTPUT_RANGE_0__2P5V,
0150     /* Range from 0 V to 5 V. Requires Rfb1x connection  */
0151     AD3552R_CH_OUTPUT_RANGE_0__5V,
0152     /* Range from 0 V to 10 V. Requires Rfb2x connection  */
0153     AD3552R_CH_OUTPUT_RANGE_0__10V,
0154     /* Range from -5 V to 5 V. Requires Rfb2x connection  */
0155     AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,
0156     /* Range from -10 V to 10 V. Requires Rfb4x connection  */
0157     AD3552R_CH_OUTPUT_RANGE_NEG_10__10V,
0158 };
0159 
0160 static const s32 ad3552r_ch_ranges[][2] = {
0161     [AD3552R_CH_OUTPUT_RANGE_0__2P5V]   = {0, 2500},
0162     [AD3552R_CH_OUTPUT_RANGE_0__5V]     = {0, 5000},
0163     [AD3552R_CH_OUTPUT_RANGE_0__10V]    = {0, 10000},
0164     [AD3552R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000},
0165     [AD3552R_CH_OUTPUT_RANGE_NEG_10__10V]   = {-10000, 10000}
0166 };
0167 
0168 enum ad3542r_ch_output_range {
0169     /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
0170     AD3542R_CH_OUTPUT_RANGE_0__2P5V,
0171     /* Range from 0 V to 3 V. Requires Rfb1x connection  */
0172     AD3542R_CH_OUTPUT_RANGE_0__3V,
0173     /* Range from 0 V to 5 V. Requires Rfb1x connection  */
0174     AD3542R_CH_OUTPUT_RANGE_0__5V,
0175     /* Range from 0 V to 10 V. Requires Rfb2x connection  */
0176     AD3542R_CH_OUTPUT_RANGE_0__10V,
0177     /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection  */
0178     AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V,
0179     /* Range from -5 V to 5 V. Requires Rfb2x connection  */
0180     AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,
0181 };
0182 
0183 static const s32 ad3542r_ch_ranges[][2] = {
0184     [AD3542R_CH_OUTPUT_RANGE_0__2P5V]   = {0, 2500},
0185     [AD3542R_CH_OUTPUT_RANGE_0__3V]     = {0, 3000},
0186     [AD3542R_CH_OUTPUT_RANGE_0__5V]     = {0, 5000},
0187     [AD3542R_CH_OUTPUT_RANGE_0__10V]    = {0, 10000},
0188     [AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V] = {-2500, 7500},
0189     [AD3542R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000}
0190 };
0191 
0192 enum ad3552r_ch_gain_scaling {
0193     /* Gain scaling of 1 */
0194     AD3552R_CH_GAIN_SCALING_1,
0195     /* Gain scaling of 0.5 */
0196     AD3552R_CH_GAIN_SCALING_0_5,
0197     /* Gain scaling of 0.25 */
0198     AD3552R_CH_GAIN_SCALING_0_25,
0199     /* Gain scaling of 0.125 */
0200     AD3552R_CH_GAIN_SCALING_0_125,
0201 };
0202 
0203 /* Gain * AD3552R_GAIN_SCALE */
0204 static const s32 gains_scaling_table[] = {
0205     [AD3552R_CH_GAIN_SCALING_1]     = 1000,
0206     [AD3552R_CH_GAIN_SCALING_0_5]       = 500,
0207     [AD3552R_CH_GAIN_SCALING_0_25]      = 250,
0208     [AD3552R_CH_GAIN_SCALING_0_125]     = 125
0209 };
0210 
0211 enum ad3552r_dev_attributes {
0212     /* - Direct register values */
0213     /* From 0-3 */
0214     AD3552R_SDO_DRIVE_STRENGTH,
0215     /*
0216      * 0 -> Internal Vref, vref_io pin floating (default)
0217      * 1 -> Internal Vref, vref_io driven by internal vref
0218      * 2 or 3 -> External Vref
0219      */
0220     AD3552R_VREF_SELECT,
0221     /* Read registers in ascending order if set. Else descending */
0222     AD3552R_ADDR_ASCENSION,
0223 };
0224 
0225 enum ad3552r_ch_attributes {
0226     /* DAC powerdown */
0227     AD3552R_CH_DAC_POWERDOWN,
0228     /* DAC amplifier powerdown */
0229     AD3552R_CH_AMPLIFIER_POWERDOWN,
0230     /* Select the output range. Select from enum ad3552r_ch_output_range */
0231     AD3552R_CH_OUTPUT_RANGE_SEL,
0232     /*
0233      * Over-rider the range selector in order to manually set the output
0234      * voltage range
0235      */
0236     AD3552R_CH_RANGE_OVERRIDE,
0237     /* Manually set the offset voltage */
0238     AD3552R_CH_GAIN_OFFSET,
0239     /* Sets the polarity of the offset. */
0240     AD3552R_CH_GAIN_OFFSET_POLARITY,
0241     /* PDAC gain scaling */
0242     AD3552R_CH_GAIN_SCALING_P,
0243     /* NDAC gain scaling */
0244     AD3552R_CH_GAIN_SCALING_N,
0245     /* Rfb value */
0246     AD3552R_CH_RFB,
0247     /* Channel select. When set allow Input -> DAC and Mask -> DAC */
0248     AD3552R_CH_SELECT,
0249 };
0250 
0251 struct ad3552r_ch_data {
0252     s32 scale_int;
0253     s32 scale_dec;
0254     s32 offset_int;
0255     s32 offset_dec;
0256     s16 gain_offset;
0257     u16 rfb;
0258     u8  n;
0259     u8  p;
0260     u8  range;
0261     bool    range_override;
0262 };
0263 
0264 struct ad3552r_desc {
0265     /* Used to look the spi bus for atomic operations where needed */
0266     struct mutex        lock;
0267     struct gpio_desc    *gpio_reset;
0268     struct gpio_desc    *gpio_ldac;
0269     struct spi_device   *spi;
0270     struct ad3552r_ch_data  ch_data[AD3552R_NUM_CH];
0271     struct iio_chan_spec    channels[AD3552R_NUM_CH + 1];
0272     unsigned long       enabled_ch;
0273     unsigned int        num_ch;
0274     enum ad3542r_id     chip_id;
0275 };
0276 
0277 static const u16 addr_mask_map[][2] = {
0278     [AD3552R_ADDR_ASCENSION] = {
0279             AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
0280             AD3552R_MASK_ADDR_ASCENSION
0281     },
0282     [AD3552R_SDO_DRIVE_STRENGTH] = {
0283             AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
0284             AD3552R_MASK_SDO_DRIVE_STRENGTH
0285     },
0286     [AD3552R_VREF_SELECT] = {
0287             AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
0288             AD3552R_MASK_REFERENCE_VOLTAGE_SEL
0289     },
0290 };
0291 
0292 /* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */
0293 static const u16 addr_mask_map_ch[][3] = {
0294     [AD3552R_CH_DAC_POWERDOWN] = {
0295             AD3552R_REG_ADDR_POWERDOWN_CONFIG,
0296             AD3552R_MASK_CH_DAC_POWERDOWN(0),
0297             AD3552R_MASK_CH_DAC_POWERDOWN(1)
0298     },
0299     [AD3552R_CH_AMPLIFIER_POWERDOWN] = {
0300             AD3552R_REG_ADDR_POWERDOWN_CONFIG,
0301             AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0),
0302             AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1)
0303     },
0304     [AD3552R_CH_OUTPUT_RANGE_SEL] = {
0305             AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
0306             AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0),
0307             AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1)
0308     },
0309     [AD3552R_CH_SELECT] = {
0310             AD3552R_REG_ADDR_CH_SELECT_16B,
0311             AD3552R_MASK_CH(0),
0312             AD3552R_MASK_CH(1)
0313     }
0314 };
0315 
0316 static u8 _ad3552r_reg_len(u8 addr)
0317 {
0318     switch (addr) {
0319     case AD3552R_REG_ADDR_HW_LDAC_16B:
0320     case AD3552R_REG_ADDR_CH_SELECT_16B:
0321     case AD3552R_REG_ADDR_SW_LDAC_16B:
0322     case AD3552R_REG_ADDR_HW_LDAC_24B:
0323     case AD3552R_REG_ADDR_CH_SELECT_24B:
0324     case AD3552R_REG_ADDR_SW_LDAC_24B:
0325         return 1;
0326     default:
0327         break;
0328     }
0329 
0330     if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)
0331         return 3;
0332     if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)
0333         return 2;
0334 
0335     return 1;
0336 }
0337 
0338 /* SPI transfer to device */
0339 static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
0340                 u8 *data, bool is_read)
0341 {
0342     /* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */
0343     u8 buf[8];
0344 
0345     buf[0] = addr & AD3552R_ADDR_MASK;
0346     buf[0] |= is_read ? AD3552R_READ_BIT : 0;
0347     if (is_read)
0348         return spi_write_then_read(dac->spi, buf, 1, data, len);
0349 
0350     memcpy(buf + 1, data, len);
0351     return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0);
0352 }
0353 
0354 static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
0355 {
0356     u8 reg_len;
0357     u8 buf[AD3552R_MAX_REG_SIZE] = { 0 };
0358 
0359     reg_len = _ad3552r_reg_len(addr);
0360     if (reg_len == 2)
0361         /* Only DAC register are 2 bytes wide */
0362         val &= AD3552R_MASK_DAC_12B;
0363     if (reg_len == 1)
0364         buf[0] = val & 0xFF;
0365     else
0366         /* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */
0367         put_unaligned_be16(val, buf);
0368 
0369     return ad3552r_transfer(dac, addr, reg_len, buf, false);
0370 }
0371 
0372 static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
0373 {
0374     int err;
0375     u8  reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 };
0376 
0377     reg_len = _ad3552r_reg_len(addr);
0378     err = ad3552r_transfer(dac, addr, reg_len, buf, true);
0379     if (err)
0380         return err;
0381 
0382     if (reg_len == 1)
0383         *val = buf[0];
0384     else
0385         /* reg_len can be 2 or 3, but only first 2 bytes are relevant */
0386         *val = get_unaligned_be16(buf);
0387 
0388     return 0;
0389 }
0390 
0391 static u16 ad3552r_field_prep(u16 val, u16 mask)
0392 {
0393     return (val << __ffs(mask)) & mask;
0394 }
0395 
0396 /* Update field of a register, shift val if needed */
0397 static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
0398                     u16 val)
0399 {
0400     int ret;
0401     u16 reg;
0402 
0403     ret = ad3552r_read_reg(dac, addr, &reg);
0404     if (ret < 0)
0405         return ret;
0406 
0407     reg &= ~mask;
0408     reg |= ad3552r_field_prep(val, mask);
0409 
0410     return ad3552r_write_reg(dac, addr, reg);
0411 }
0412 
0413 static int ad3552r_set_ch_value(struct ad3552r_desc *dac,
0414                 enum ad3552r_ch_attributes attr,
0415                 u8 ch,
0416                 u16 val)
0417 {
0418     /* Update register related to attributes in chip */
0419     return ad3552r_update_reg_field(dac, addr_mask_map_ch[attr][0],
0420                        addr_mask_map_ch[attr][ch + 1], val);
0421 }
0422 
0423 #define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) {      \
0424     .type = IIO_VOLTAGE,                    \
0425     .output = true,                     \
0426     .indexed = true,                    \
0427     .channel = _idx,                    \
0428     .scan_index = _idx,                 \
0429     .scan_type = {                      \
0430         .sign = 'u',                    \
0431         .realbits = 16,                 \
0432         .storagebits = 16,              \
0433         .endianness = IIO_BE,               \
0434     },                          \
0435     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0436                 BIT(IIO_CHAN_INFO_SCALE) |  \
0437                 BIT(IIO_CHAN_INFO_ENABLE) | \
0438                 BIT(IIO_CHAN_INFO_OFFSET),  \
0439 })
0440 
0441 static int ad3552r_read_raw(struct iio_dev *indio_dev,
0442                 struct iio_chan_spec const *chan,
0443                 int *val,
0444                 int *val2,
0445                 long mask)
0446 {
0447     struct ad3552r_desc *dac = iio_priv(indio_dev);
0448     u16 tmp_val;
0449     int err;
0450     u8 ch = chan->channel;
0451 
0452     switch (mask) {
0453     case IIO_CHAN_INFO_RAW:
0454         mutex_lock(&dac->lock);
0455         err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),
0456                        &tmp_val);
0457         mutex_unlock(&dac->lock);
0458         if (err < 0)
0459             return err;
0460         *val = tmp_val;
0461         return IIO_VAL_INT;
0462     case IIO_CHAN_INFO_ENABLE:
0463         mutex_lock(&dac->lock);
0464         err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
0465                        &tmp_val);
0466         mutex_unlock(&dac->lock);
0467         if (err < 0)
0468             return err;
0469         *val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>
0470               __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));
0471         return IIO_VAL_INT;
0472     case IIO_CHAN_INFO_SCALE:
0473         *val = dac->ch_data[ch].scale_int;
0474         *val2 = dac->ch_data[ch].scale_dec;
0475         return IIO_VAL_INT_PLUS_MICRO;
0476     case IIO_CHAN_INFO_OFFSET:
0477         *val = dac->ch_data[ch].offset_int;
0478         *val2 = dac->ch_data[ch].offset_dec;
0479         return IIO_VAL_INT_PLUS_MICRO;
0480     default:
0481         return -EINVAL;
0482     }
0483 }
0484 
0485 static int ad3552r_write_raw(struct iio_dev *indio_dev,
0486                  struct iio_chan_spec const *chan,
0487                  int val,
0488                  int val2,
0489                  long mask)
0490 {
0491     struct ad3552r_desc *dac = iio_priv(indio_dev);
0492     int err;
0493 
0494     mutex_lock(&dac->lock);
0495     switch (mask) {
0496     case IIO_CHAN_INFO_RAW:
0497         err = ad3552r_write_reg(dac,
0498                     AD3552R_REG_ADDR_CH_DAC_24B(chan->channel),
0499                     val);
0500         break;
0501     case IIO_CHAN_INFO_ENABLE:
0502         err = ad3552r_set_ch_value(dac, AD3552R_CH_DAC_POWERDOWN,
0503                        chan->channel, !val);
0504         break;
0505     default:
0506         err = -EINVAL;
0507         break;
0508     }
0509     mutex_unlock(&dac->lock);
0510 
0511     return err;
0512 }
0513 
0514 static const struct iio_info ad3552r_iio_info = {
0515     .read_raw = ad3552r_read_raw,
0516     .write_raw = ad3552r_write_raw
0517 };
0518 
0519 static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac)
0520 {
0521     gpiod_set_value_cansleep(ldac, 0);
0522     usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);
0523     gpiod_set_value_cansleep(ldac, 1);
0524 
0525     return 0;
0526 }
0527 
0528 static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data)
0529 {
0530     int err, len;
0531     u8 addr, buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE + 1];
0532 
0533     addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
0534     /* CH1 */
0535     memcpy(buff, data + 2, 2);
0536     buff[2] = 0;
0537     /* CH0 */
0538     memcpy(buff + 3, data, 2);
0539     buff[5] = 0;
0540     len = 6;
0541     if (!dac->gpio_ldac) {
0542         /* Software LDAC */
0543         buff[6] = AD3552R_MASK_ALL_CH;
0544         ++len;
0545     }
0546     err = ad3552r_transfer(dac, addr, len, buff, false);
0547     if (err)
0548         return err;
0549 
0550     if (dac->gpio_ldac)
0551         return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
0552 
0553     return 0;
0554 }
0555 
0556 static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
0557 {
0558     int err;
0559     u8 addr, buff[AD3552R_MAX_REG_SIZE];
0560 
0561     if (mask == AD3552R_MASK_ALL_CH) {
0562         if (memcmp(data, data + 2, 2) != 0)
0563             return ad3552r_write_all_channels(dac, data);
0564 
0565         addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B;
0566     } else {
0567         addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask));
0568     }
0569 
0570     memcpy(buff, data, 2);
0571     buff[2] = 0;
0572     err = ad3552r_transfer(dac, addr, 3, data, false);
0573     if (err)
0574         return err;
0575 
0576     if (dac->gpio_ldac)
0577         return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
0578 
0579     return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask);
0580 }
0581 
0582 static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
0583 {
0584     struct iio_poll_func *pf = p;
0585     struct iio_dev *indio_dev = pf->indio_dev;
0586     struct iio_buffer *buf = indio_dev->buffer;
0587     struct ad3552r_desc *dac = iio_priv(indio_dev);
0588     /* Maximum size of a scan */
0589     u8 buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE];
0590     int err;
0591 
0592     memset(buff, 0, sizeof(buff));
0593     err = iio_pop_from_buffer(buf, buff);
0594     if (err)
0595         goto end;
0596 
0597     mutex_lock(&dac->lock);
0598     ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);
0599     mutex_unlock(&dac->lock);
0600 end:
0601     iio_trigger_notify_done(indio_dev->trig);
0602 
0603     return IRQ_HANDLED;
0604 }
0605 
0606 static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)
0607 {
0608     const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1;
0609     const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2;
0610     u16 val;
0611     int err;
0612 
0613     err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1);
0614     if (err < 0)
0615         return err;
0616 
0617     err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
0618     if (err < 0)
0619         return err;
0620 
0621     if (val1 != val)
0622         return -ENODEV;
0623 
0624     err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2);
0625     if (err < 0)
0626         return err;
0627 
0628     err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
0629     if (err < 0)
0630         return err;
0631 
0632     if (val2 != val)
0633         return -ENODEV;
0634 
0635     return 0;
0636 }
0637 
0638 struct reg_addr_pool {
0639     struct ad3552r_desc *dac;
0640     u8          addr;
0641 };
0642 
0643 static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
0644 {
0645     int err;
0646     u16 val;
0647 
0648     err = ad3552r_read_reg(addr->dac, addr->addr, &val);
0649     if (err)
0650         return err;
0651 
0652     return val;
0653 }
0654 
0655 static int ad3552r_reset(struct ad3552r_desc *dac)
0656 {
0657     struct reg_addr_pool addr;
0658     int ret;
0659     int val;
0660 
0661     dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
0662                           GPIOD_OUT_LOW);
0663     if (IS_ERR(dac->gpio_reset))
0664         return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),
0665                      "Error while getting gpio reset");
0666 
0667     if (dac->gpio_reset) {
0668         /* Perform hardware reset */
0669         usleep_range(10, 20);
0670         gpiod_set_value_cansleep(dac->gpio_reset, 1);
0671     } else {
0672         /* Perform software reset if no GPIO provided */
0673         ret = ad3552r_update_reg_field(dac,
0674                            AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
0675                            AD3552R_MASK_SOFTWARE_RESET,
0676                            AD3552R_MASK_SOFTWARE_RESET);
0677         if (ret < 0)
0678             return ret;
0679 
0680     }
0681 
0682     addr.dac = dac;
0683     addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
0684     ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
0685                  val == AD3552R_DEFAULT_CONFIG_B_VALUE ||
0686                  val < 0,
0687                  5000, 50000);
0688     if (val < 0)
0689         ret = val;
0690     if (ret) {
0691         dev_err(&dac->spi->dev, "Error while resetting");
0692         return ret;
0693     }
0694 
0695     ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
0696                  !(val & AD3552R_MASK_INTERFACE_NOT_READY) ||
0697                  val < 0,
0698                  5000, 50000);
0699     if (val < 0)
0700         ret = val;
0701     if (ret) {
0702         dev_err(&dac->spi->dev, "Error while resetting");
0703         return ret;
0704     }
0705 
0706     return ad3552r_update_reg_field(dac,
0707                     addr_mask_map[AD3552R_ADDR_ASCENSION][0],
0708                     addr_mask_map[AD3552R_ADDR_ASCENSION][1],
0709                     val);
0710 }
0711 
0712 static void ad3552r_get_custom_range(struct ad3552r_desc *dac, s32 i, s32 *v_min,
0713                      s32 *v_max)
0714 {
0715     s64 vref, tmp, common, offset, gn, gp;
0716     /*
0717      * From datasheet formula (In Volts):
0718      *  Vmin = 2.5 + [(GainN + Offset / 1024) * 2.5 * Rfb * 1.03]
0719      *  Vmax = 2.5 - [(GainP + Offset / 1024) * 2.5 * Rfb * 1.03]
0720      * Calculus are converted to milivolts
0721      */
0722     vref = 2500;
0723     /* 2.5 * 1.03 * 1000 (To mV) */
0724     common = 2575 * dac->ch_data[i].rfb;
0725     offset = dac->ch_data[i].gain_offset;
0726 
0727     gn = gains_scaling_table[dac->ch_data[i].n];
0728     tmp = (1024 * gn + AD3552R_GAIN_SCALE * offset) * common;
0729     tmp = div_s64(tmp, 1024  * AD3552R_GAIN_SCALE);
0730     *v_max = vref + tmp;
0731 
0732     gp = gains_scaling_table[dac->ch_data[i].p];
0733     tmp = (1024 * gp - AD3552R_GAIN_SCALE * offset) * common;
0734     tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);
0735     *v_min = vref - tmp;
0736 }
0737 
0738 static void ad3552r_calc_gain_and_offset(struct ad3552r_desc *dac, s32 ch)
0739 {
0740     s32 idx, v_max, v_min, span, rem;
0741     s64 tmp;
0742 
0743     if (dac->ch_data[ch].range_override) {
0744         ad3552r_get_custom_range(dac, ch, &v_min, &v_max);
0745     } else {
0746         /* Normal range */
0747         idx = dac->ch_data[ch].range;
0748         if (dac->chip_id == AD3542R_ID) {
0749             v_min = ad3542r_ch_ranges[idx][0];
0750             v_max = ad3542r_ch_ranges[idx][1];
0751         } else {
0752             v_min = ad3552r_ch_ranges[idx][0];
0753             v_max = ad3552r_ch_ranges[idx][1];
0754         }
0755     }
0756 
0757     /*
0758      * From datasheet formula:
0759      *  Vout = Span * (D / 65536) + Vmin
0760      * Converted to scale and offset:
0761      *  Scale = Span / 65536
0762      *  Offset = 65536 * Vmin / Span
0763      *
0764      * Reminders are in micros in order to be printed as
0765      * IIO_VAL_INT_PLUS_MICRO
0766      */
0767     span = v_max - v_min;
0768     dac->ch_data[ch].scale_int = div_s64_rem(span, 65536, &rem);
0769     /* Do operations in microvolts */
0770     dac->ch_data[ch].scale_dec = DIV_ROUND_CLOSEST((s64)rem * 1000000,
0771                             65536);
0772 
0773     dac->ch_data[ch].offset_int = div_s64_rem(v_min * 65536, span, &rem);
0774     tmp = (s64)rem * 1000000;
0775     dac->ch_data[ch].offset_dec = div_s64(tmp, span);
0776 }
0777 
0778 static int ad3552r_find_range(u16 id, s32 *vals)
0779 {
0780     int i, len;
0781     const s32 (*ranges)[2];
0782 
0783     if (id == AD3542R_ID) {
0784         len = ARRAY_SIZE(ad3542r_ch_ranges);
0785         ranges = ad3542r_ch_ranges;
0786     } else {
0787         len = ARRAY_SIZE(ad3552r_ch_ranges);
0788         ranges = ad3552r_ch_ranges;
0789     }
0790 
0791     for (i = 0; i < len; i++)
0792         if (vals[0] == ranges[i][0] * 1000 &&
0793             vals[1] == ranges[i][1] * 1000)
0794             return i;
0795 
0796     return -EINVAL;
0797 }
0798 
0799 static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
0800                      struct fwnode_handle *child,
0801                      u32 ch)
0802 {
0803     struct device *dev = &dac->spi->dev;
0804     struct fwnode_handle *gain_child;
0805     u32 val;
0806     int err;
0807     u8 addr;
0808     u16 reg = 0, offset;
0809 
0810     gain_child = fwnode_get_named_child_node(child,
0811                          "custom-output-range-config");
0812     if (!gain_child) {
0813         dev_err(dev,
0814             "mandatory custom-output-range-config property missing\n");
0815         return -EINVAL;
0816     }
0817 
0818     dac->ch_data[ch].range_override = 1;
0819     reg |= ad3552r_field_prep(1, AD3552R_MASK_CH_RANGE_OVERRIDE);
0820 
0821     err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-p", &val);
0822     if (err) {
0823         dev_err(dev, "mandatory adi,gain-scaling-p property missing\n");
0824         goto put_child;
0825     }
0826     reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_P);
0827     dac->ch_data[ch].p = val;
0828 
0829     err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-n", &val);
0830     if (err) {
0831         dev_err(dev, "mandatory adi,gain-scaling-n property missing\n");
0832         goto put_child;
0833     }
0834     reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_N);
0835     dac->ch_data[ch].n = val;
0836 
0837     err = fwnode_property_read_u32(gain_child, "adi,rfb-ohms", &val);
0838     if (err) {
0839         dev_err(dev, "mandatory adi,rfb-ohms property missing\n");
0840         goto put_child;
0841     }
0842     dac->ch_data[ch].rfb = val;
0843 
0844     err = fwnode_property_read_u32(gain_child, "adi,gain-offset", &val);
0845     if (err) {
0846         dev_err(dev, "mandatory adi,gain-offset property missing\n");
0847         goto put_child;
0848     }
0849     dac->ch_data[ch].gain_offset = val;
0850 
0851     offset = abs((s32)val);
0852     reg |= ad3552r_field_prep((offset >> 8), AD3552R_MASK_CH_OFFSET_BIT_8);
0853 
0854     reg |= ad3552r_field_prep((s32)val < 0, AD3552R_MASK_CH_OFFSET_POLARITY);
0855     addr = AD3552R_REG_ADDR_CH_GAIN(ch);
0856     err = ad3552r_write_reg(dac, addr,
0857                 offset & AD3552R_MASK_CH_OFFSET_BITS_0_7);
0858     if (err) {
0859         dev_err(dev, "Error writing register\n");
0860         goto put_child;
0861     }
0862 
0863     err = ad3552r_write_reg(dac, addr, reg);
0864     if (err) {
0865         dev_err(dev, "Error writing register\n");
0866         goto put_child;
0867     }
0868 
0869 put_child:
0870     fwnode_handle_put(gain_child);
0871 
0872     return err;
0873 }
0874 
0875 static void ad3552r_reg_disable(void *reg)
0876 {
0877     regulator_disable(reg);
0878 }
0879 
0880 static int ad3552r_configure_device(struct ad3552r_desc *dac)
0881 {
0882     struct device *dev = &dac->spi->dev;
0883     struct fwnode_handle *child;
0884     struct regulator *vref;
0885     int err, cnt = 0, voltage, delta = 100000;
0886     u32 vals[2], val, ch;
0887 
0888     dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
0889     if (IS_ERR(dac->gpio_ldac))
0890         return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
0891                      "Error getting gpio ldac");
0892 
0893     vref = devm_regulator_get_optional(dev, "vref");
0894     if (IS_ERR(vref)) {
0895         if (PTR_ERR(vref) != -ENODEV)
0896             return dev_err_probe(dev, PTR_ERR(vref),
0897                          "Error getting vref");
0898 
0899         if (device_property_read_bool(dev, "adi,vref-out-en"))
0900             val = AD3552R_INTERNAL_VREF_PIN_2P5V;
0901         else
0902             val = AD3552R_INTERNAL_VREF_PIN_FLOATING;
0903     } else {
0904         err = regulator_enable(vref);
0905         if (err) {
0906             dev_err(dev, "Failed to enable external vref supply\n");
0907             return err;
0908         }
0909 
0910         err = devm_add_action_or_reset(dev, ad3552r_reg_disable, vref);
0911         if (err) {
0912             regulator_disable(vref);
0913             return err;
0914         }
0915 
0916         voltage = regulator_get_voltage(vref);
0917         if (voltage > 2500000 + delta || voltage < 2500000 - delta) {
0918             dev_warn(dev, "vref-supply must be 2.5V");
0919             return -EINVAL;
0920         }
0921         val = AD3552R_EXTERNAL_VREF_PIN_INPUT;
0922     }
0923 
0924     err = ad3552r_update_reg_field(dac,
0925                        addr_mask_map[AD3552R_VREF_SELECT][0],
0926                        addr_mask_map[AD3552R_VREF_SELECT][1],
0927                        val);
0928     if (err)
0929         return err;
0930 
0931     err = device_property_read_u32(dev, "adi,sdo-drive-strength", &val);
0932     if (!err) {
0933         if (val > 3) {
0934             dev_err(dev, "adi,sdo-drive-strength must be less than 4\n");
0935             return -EINVAL;
0936         }
0937 
0938         err = ad3552r_update_reg_field(dac,
0939                            addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0],
0940                            addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1],
0941                            val);
0942         if (err)
0943             return err;
0944     }
0945 
0946     dac->num_ch = device_get_child_node_count(dev);
0947     if (!dac->num_ch) {
0948         dev_err(dev, "No channels defined\n");
0949         return -ENODEV;
0950     }
0951 
0952     device_for_each_child_node(dev, child) {
0953         err = fwnode_property_read_u32(child, "reg", &ch);
0954         if (err) {
0955             dev_err(dev, "mandatory reg property missing\n");
0956             goto put_child;
0957         }
0958         if (ch >= AD3552R_NUM_CH) {
0959             dev_err(dev, "reg must be less than %d\n",
0960                 AD3552R_NUM_CH);
0961             err = -EINVAL;
0962             goto put_child;
0963         }
0964 
0965         if (fwnode_property_present(child, "adi,output-range-microvolt")) {
0966             err = fwnode_property_read_u32_array(child,
0967                                  "adi,output-range-microvolt",
0968                                  vals,
0969                                  2);
0970             if (err) {
0971                 dev_err(dev,
0972                     "adi,output-range-microvolt property could not be parsed\n");
0973                 goto put_child;
0974             }
0975 
0976             err = ad3552r_find_range(dac->chip_id, vals);
0977             if (err < 0) {
0978                 dev_err(dev,
0979                     "Invalid adi,output-range-microvolt value\n");
0980                 goto put_child;
0981             }
0982             val = err;
0983             err = ad3552r_set_ch_value(dac,
0984                            AD3552R_CH_OUTPUT_RANGE_SEL,
0985                            ch, val);
0986             if (err)
0987                 goto put_child;
0988 
0989             dac->ch_data[ch].range = val;
0990         } else if (dac->chip_id == AD3542R_ID) {
0991             dev_err(dev,
0992                 "adi,output-range-microvolt is required for ad3542r\n");
0993             err = -EINVAL;
0994             goto put_child;
0995         } else {
0996             err = ad3552r_configure_custom_gain(dac, child, ch);
0997             if (err)
0998                 goto put_child;
0999         }
1000 
1001         ad3552r_calc_gain_and_offset(dac, ch);
1002         dac->enabled_ch |= BIT(ch);
1003 
1004         err = ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1);
1005         if (err < 0)
1006             goto put_child;
1007 
1008         dac->channels[cnt] = AD3552R_CH_DAC(ch);
1009         ++cnt;
1010 
1011     }
1012 
1013     /* Disable unused channels */
1014     for_each_clear_bit(ch, &dac->enabled_ch, AD3552R_NUM_CH) {
1015         err = ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN,
1016                        ch, 1);
1017         if (err)
1018             return err;
1019     }
1020 
1021     dac->num_ch = cnt;
1022 
1023     return 0;
1024 put_child:
1025     fwnode_handle_put(child);
1026 
1027     return err;
1028 }
1029 
1030 static int ad3552r_init(struct ad3552r_desc *dac)
1031 {
1032     int err;
1033     u16 val, id;
1034 
1035     err = ad3552r_reset(dac);
1036     if (err) {
1037         dev_err(&dac->spi->dev, "Reset failed\n");
1038         return err;
1039     }
1040 
1041     err = ad3552r_check_scratch_pad(dac);
1042     if (err) {
1043         dev_err(&dac->spi->dev, "Scratch pad test failed\n");
1044         return err;
1045     }
1046 
1047     err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);
1048     if (err) {
1049         dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n");
1050         return err;
1051     }
1052 
1053     id = val;
1054     err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);
1055     if (err) {
1056         dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n");
1057         return err;
1058     }
1059 
1060     id |= val << 8;
1061     if (id != dac->chip_id) {
1062         dev_err(&dac->spi->dev, "Product id not matching\n");
1063         return -ENODEV;
1064     }
1065 
1066     return ad3552r_configure_device(dac);
1067 }
1068 
1069 static int ad3552r_probe(struct spi_device *spi)
1070 {
1071     const struct spi_device_id *id = spi_get_device_id(spi);
1072     struct ad3552r_desc *dac;
1073     struct iio_dev *indio_dev;
1074     int err;
1075 
1076     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac));
1077     if (!indio_dev)
1078         return -ENOMEM;
1079 
1080     dac = iio_priv(indio_dev);
1081     dac->spi = spi;
1082     dac->chip_id = id->driver_data;
1083 
1084     mutex_init(&dac->lock);
1085 
1086     err = ad3552r_init(dac);
1087     if (err)
1088         return err;
1089 
1090     /* Config triggered buffer device */
1091     if (dac->chip_id == AD3552R_ID)
1092         indio_dev->name = "ad3552r";
1093     else
1094         indio_dev->name = "ad3542r";
1095     indio_dev->dev.parent = &spi->dev;
1096     indio_dev->info = &ad3552r_iio_info;
1097     indio_dev->num_channels = dac->num_ch;
1098     indio_dev->channels = dac->channels;
1099     indio_dev->modes = INDIO_DIRECT_MODE;
1100 
1101     err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL,
1102                           &ad3552r_trigger_handler,
1103                           IIO_BUFFER_DIRECTION_OUT,
1104                           NULL,
1105                           NULL);
1106     if (err)
1107         return err;
1108 
1109     return devm_iio_device_register(&spi->dev, indio_dev);
1110 }
1111 
1112 static const struct spi_device_id ad3552r_id[] = {
1113     { "ad3542r", AD3542R_ID },
1114     { "ad3552r", AD3552R_ID },
1115     { }
1116 };
1117 MODULE_DEVICE_TABLE(spi, ad3552r_id);
1118 
1119 static const struct of_device_id ad3552r_of_match[] = {
1120     { .compatible = "adi,ad3542r"},
1121     { .compatible = "adi,ad3552r"},
1122     { }
1123 };
1124 MODULE_DEVICE_TABLE(of, ad3552r_of_match);
1125 
1126 static struct spi_driver ad3552r_driver = {
1127     .driver = {
1128         .name = "ad3552r",
1129         .of_match_table = ad3552r_of_match,
1130     },
1131     .probe = ad3552r_probe,
1132     .id_table = ad3552r_id
1133 };
1134 module_spi_driver(ad3552r_driver);
1135 
1136 MODULE_AUTHOR("Mihail Chindris <mihail.chindris@analog.com>");
1137 MODULE_DESCRIPTION("Analog Device AD3552R DAC");
1138 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!