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0007 #include <linux/bits.h>
0008 #include <linux/completion.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/errno.h>
0012 #include <linux/export.h>
0013 #include <linux/iio/buffer.h>
0014 #include <linux/iio/iio.h>
0015 #include <linux/iio/sysfs.h>
0016 #include <linux/iio/trigger.h>
0017 #include <linux/iio/trigger_consumer.h>
0018 #include <linux/iio/triggered_buffer.h>
0019 #include <linux/iio/types.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/irqreturn.h>
0022 #include <linux/jiffies.h>
0023 #include <linux/kernel.h>
0024 #include <linux/module.h>
0025 #include <linux/mutex.h>
0026 #include <linux/regulator/consumer.h>
0027 #include <linux/string.h>
0028 #include <linux/sysfs.h>
0029 #include <linux/types.h>
0030 #include <asm/byteorder.h>
0031
0032 #include "scd30.h"
0033
0034 #define SCD30_PRESSURE_COMP_MIN_MBAR 700
0035 #define SCD30_PRESSURE_COMP_MAX_MBAR 1400
0036 #define SCD30_PRESSURE_COMP_DEFAULT 1013
0037 #define SCD30_MEAS_INTERVAL_MIN_S 2
0038 #define SCD30_MEAS_INTERVAL_MAX_S 1800
0039 #define SCD30_MEAS_INTERVAL_DEFAULT SCD30_MEAS_INTERVAL_MIN_S
0040 #define SCD30_FRC_MIN_PPM 400
0041 #define SCD30_FRC_MAX_PPM 2000
0042 #define SCD30_TEMP_OFFSET_MAX 655360
0043 #define SCD30_EXTRA_TIMEOUT_PER_S 250
0044
0045 enum {
0046 SCD30_CONC,
0047 SCD30_TEMP,
0048 SCD30_HR,
0049 };
0050
0051 static int scd30_command_write(struct scd30_state *state, enum scd30_cmd cmd, u16 arg)
0052 {
0053 return state->command(state, cmd, arg, NULL, 0);
0054 }
0055
0056 static int scd30_command_read(struct scd30_state *state, enum scd30_cmd cmd, u16 *val)
0057 {
0058 __be16 tmp;
0059 int ret;
0060
0061 ret = state->command(state, cmd, 0, &tmp, sizeof(tmp));
0062 *val = be16_to_cpup(&tmp);
0063
0064 return ret;
0065 }
0066
0067 static int scd30_reset(struct scd30_state *state)
0068 {
0069 int ret;
0070 u16 val;
0071
0072 ret = scd30_command_write(state, CMD_RESET, 0);
0073 if (ret)
0074 return ret;
0075
0076
0077 msleep(2000);
0078
0079
0080
0081
0082
0083 scd30_command_read(state, CMD_MEAS_READY, &val);
0084
0085 return 0;
0086 }
0087
0088
0089 static int scd30_float_to_fp(int float32)
0090 {
0091 int fraction, shift,
0092 mantissa = float32 & GENMASK(22, 0),
0093 sign = (float32 & BIT(31)) ? -1 : 1,
0094 exp = (float32 & ~BIT(31)) >> 23;
0095
0096
0097 if (!exp && !mantissa)
0098 return 0;
0099
0100 exp -= 127;
0101 if (exp < 0) {
0102 exp = -exp;
0103
0104 return sign * ((((BIT(23) + mantissa) * 100) >> 23) >> exp);
0105 }
0106
0107
0108 shift = 23 - exp;
0109 float32 = BIT(exp) + (mantissa >> shift);
0110 fraction = mantissa & GENMASK(shift - 1, 0);
0111
0112 return sign * (float32 * 100 + ((fraction * 100) >> shift));
0113 }
0114
0115 static int scd30_read_meas(struct scd30_state *state)
0116 {
0117 int i, ret;
0118
0119 ret = state->command(state, CMD_READ_MEAS, 0, state->meas, sizeof(state->meas));
0120 if (ret)
0121 return ret;
0122
0123 be32_to_cpu_array(state->meas, (__be32 *)state->meas, ARRAY_SIZE(state->meas));
0124
0125 for (i = 0; i < ARRAY_SIZE(state->meas); i++)
0126 state->meas[i] = scd30_float_to_fp(state->meas[i]);
0127
0128
0129
0130
0131
0132 state->meas[SCD30_TEMP] *= 10;
0133 state->meas[SCD30_HR] *= 10;
0134
0135 return 0;
0136 }
0137
0138 static int scd30_wait_meas_irq(struct scd30_state *state)
0139 {
0140 int ret, timeout;
0141
0142 reinit_completion(&state->meas_ready);
0143 enable_irq(state->irq);
0144 timeout = msecs_to_jiffies(state->meas_interval * (1000 + SCD30_EXTRA_TIMEOUT_PER_S));
0145 ret = wait_for_completion_interruptible_timeout(&state->meas_ready, timeout);
0146 if (ret > 0)
0147 ret = 0;
0148 else if (!ret)
0149 ret = -ETIMEDOUT;
0150
0151 disable_irq(state->irq);
0152
0153 return ret;
0154 }
0155
0156 static int scd30_wait_meas_poll(struct scd30_state *state)
0157 {
0158 int timeout = state->meas_interval * SCD30_EXTRA_TIMEOUT_PER_S, tries = 5;
0159
0160 do {
0161 int ret;
0162 u16 val;
0163
0164 ret = scd30_command_read(state, CMD_MEAS_READY, &val);
0165 if (ret)
0166 return -EIO;
0167
0168
0169 if (val)
0170 break;
0171
0172 msleep_interruptible(timeout);
0173 } while (--tries);
0174
0175 return tries ? 0 : -ETIMEDOUT;
0176 }
0177
0178 static int scd30_read_poll(struct scd30_state *state)
0179 {
0180 int ret;
0181
0182 ret = scd30_wait_meas_poll(state);
0183 if (ret)
0184 return ret;
0185
0186 return scd30_read_meas(state);
0187 }
0188
0189 static int scd30_read(struct scd30_state *state)
0190 {
0191 if (state->irq > 0)
0192 return scd30_wait_meas_irq(state);
0193
0194 return scd30_read_poll(state);
0195 }
0196
0197 static int scd30_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
0198 int *val, int *val2, long mask)
0199 {
0200 struct scd30_state *state = iio_priv(indio_dev);
0201 int ret = -EINVAL;
0202 u16 tmp;
0203
0204 mutex_lock(&state->lock);
0205 switch (mask) {
0206 case IIO_CHAN_INFO_RAW:
0207 case IIO_CHAN_INFO_PROCESSED:
0208 if (chan->output) {
0209 *val = state->pressure_comp;
0210 ret = IIO_VAL_INT;
0211 break;
0212 }
0213
0214 ret = iio_device_claim_direct_mode(indio_dev);
0215 if (ret)
0216 break;
0217
0218 ret = scd30_read(state);
0219 if (ret) {
0220 iio_device_release_direct_mode(indio_dev);
0221 break;
0222 }
0223
0224 *val = state->meas[chan->address];
0225 iio_device_release_direct_mode(indio_dev);
0226 ret = IIO_VAL_INT;
0227 break;
0228 case IIO_CHAN_INFO_SCALE:
0229 *val = 0;
0230 *val2 = 1;
0231 ret = IIO_VAL_INT_PLUS_MICRO;
0232 break;
0233 case IIO_CHAN_INFO_SAMP_FREQ:
0234 ret = scd30_command_read(state, CMD_MEAS_INTERVAL, &tmp);
0235 if (ret)
0236 break;
0237
0238 *val = 0;
0239 *val2 = 1000000000 / tmp;
0240 ret = IIO_VAL_INT_PLUS_NANO;
0241 break;
0242 case IIO_CHAN_INFO_CALIBBIAS:
0243 ret = scd30_command_read(state, CMD_TEMP_OFFSET, &tmp);
0244 if (ret)
0245 break;
0246
0247 *val = tmp;
0248 ret = IIO_VAL_INT;
0249 break;
0250 }
0251 mutex_unlock(&state->lock);
0252
0253 return ret;
0254 }
0255
0256 static int scd30_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
0257 int val, int val2, long mask)
0258 {
0259 struct scd30_state *state = iio_priv(indio_dev);
0260 int ret = -EINVAL;
0261
0262 mutex_lock(&state->lock);
0263 switch (mask) {
0264 case IIO_CHAN_INFO_SAMP_FREQ:
0265 if (val)
0266 break;
0267
0268 val = 1000000000 / val2;
0269 if (val < SCD30_MEAS_INTERVAL_MIN_S || val > SCD30_MEAS_INTERVAL_MAX_S)
0270 break;
0271
0272 ret = scd30_command_write(state, CMD_MEAS_INTERVAL, val);
0273 if (ret)
0274 break;
0275
0276 state->meas_interval = val;
0277 break;
0278 case IIO_CHAN_INFO_RAW:
0279 switch (chan->type) {
0280 case IIO_PRESSURE:
0281 if (val < SCD30_PRESSURE_COMP_MIN_MBAR ||
0282 val > SCD30_PRESSURE_COMP_MAX_MBAR)
0283 break;
0284
0285 ret = scd30_command_write(state, CMD_START_MEAS, val);
0286 if (ret)
0287 break;
0288
0289 state->pressure_comp = val;
0290 break;
0291 default:
0292 break;
0293 }
0294 break;
0295 case IIO_CHAN_INFO_CALIBBIAS:
0296 if (val < 0 || val > SCD30_TEMP_OFFSET_MAX)
0297 break;
0298
0299
0300
0301
0302 ret = scd30_command_write(state, CMD_TEMP_OFFSET / 10, val);
0303 }
0304 mutex_unlock(&state->lock);
0305
0306 return ret;
0307 }
0308
0309 static int scd30_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
0310 long mask)
0311 {
0312 switch (mask) {
0313 case IIO_CHAN_INFO_SAMP_FREQ:
0314 return IIO_VAL_INT_PLUS_NANO;
0315 case IIO_CHAN_INFO_RAW:
0316 case IIO_CHAN_INFO_CALIBBIAS:
0317 return IIO_VAL_INT;
0318 }
0319
0320 return -EINVAL;
0321 }
0322
0323 static const int scd30_pressure_raw_available[] = {
0324 SCD30_PRESSURE_COMP_MIN_MBAR, 1, SCD30_PRESSURE_COMP_MAX_MBAR,
0325 };
0326
0327 static const int scd30_temp_calibbias_available[] = {
0328 0, 10, SCD30_TEMP_OFFSET_MAX,
0329 };
0330
0331 static int scd30_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
0332 const int **vals, int *type, int *length, long mask)
0333 {
0334 switch (mask) {
0335 case IIO_CHAN_INFO_RAW:
0336 *vals = scd30_pressure_raw_available;
0337 *type = IIO_VAL_INT;
0338
0339 return IIO_AVAIL_RANGE;
0340 case IIO_CHAN_INFO_CALIBBIAS:
0341 *vals = scd30_temp_calibbias_available;
0342 *type = IIO_VAL_INT;
0343
0344 return IIO_AVAIL_RANGE;
0345 }
0346
0347 return -EINVAL;
0348 }
0349
0350 static ssize_t sampling_frequency_available_show(struct device *dev, struct device_attribute *attr,
0351 char *buf)
0352 {
0353 int i = SCD30_MEAS_INTERVAL_MIN_S;
0354 ssize_t len = 0;
0355
0356 do {
0357 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09u ", 1000000000 / i);
0358
0359
0360
0361
0362
0363 i += 6;
0364 } while (i <= SCD30_MEAS_INTERVAL_MAX_S);
0365
0366 buf[len - 1] = '\n';
0367
0368 return len;
0369 }
0370
0371 static ssize_t calibration_auto_enable_show(struct device *dev, struct device_attribute *attr,
0372 char *buf)
0373 {
0374 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0375 struct scd30_state *state = iio_priv(indio_dev);
0376 int ret;
0377 u16 val;
0378
0379 mutex_lock(&state->lock);
0380 ret = scd30_command_read(state, CMD_ASC, &val);
0381 mutex_unlock(&state->lock);
0382
0383 return ret ?: sprintf(buf, "%d\n", val);
0384 }
0385
0386 static ssize_t calibration_auto_enable_store(struct device *dev, struct device_attribute *attr,
0387 const char *buf, size_t len)
0388 {
0389 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0390 struct scd30_state *state = iio_priv(indio_dev);
0391 bool val;
0392 int ret;
0393
0394 ret = kstrtobool(buf, &val);
0395 if (ret)
0396 return ret;
0397
0398 mutex_lock(&state->lock);
0399 ret = scd30_command_write(state, CMD_ASC, val);
0400 mutex_unlock(&state->lock);
0401
0402 return ret ?: len;
0403 }
0404
0405 static ssize_t calibration_forced_value_show(struct device *dev, struct device_attribute *attr,
0406 char *buf)
0407 {
0408 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0409 struct scd30_state *state = iio_priv(indio_dev);
0410 int ret;
0411 u16 val;
0412
0413 mutex_lock(&state->lock);
0414 ret = scd30_command_read(state, CMD_FRC, &val);
0415 mutex_unlock(&state->lock);
0416
0417 return ret ?: sprintf(buf, "%d\n", val);
0418 }
0419
0420 static ssize_t calibration_forced_value_store(struct device *dev, struct device_attribute *attr,
0421 const char *buf, size_t len)
0422 {
0423 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0424 struct scd30_state *state = iio_priv(indio_dev);
0425 int ret;
0426 u16 val;
0427
0428 ret = kstrtou16(buf, 0, &val);
0429 if (ret)
0430 return ret;
0431
0432 if (val < SCD30_FRC_MIN_PPM || val > SCD30_FRC_MAX_PPM)
0433 return -EINVAL;
0434
0435 mutex_lock(&state->lock);
0436 ret = scd30_command_write(state, CMD_FRC, val);
0437 mutex_unlock(&state->lock);
0438
0439 return ret ?: len;
0440 }
0441
0442 static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0);
0443 static IIO_DEVICE_ATTR_RW(calibration_auto_enable, 0);
0444 static IIO_DEVICE_ATTR_RW(calibration_forced_value, 0);
0445
0446 static struct attribute *scd30_attrs[] = {
0447 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
0448 &iio_dev_attr_calibration_auto_enable.dev_attr.attr,
0449 &iio_dev_attr_calibration_forced_value.dev_attr.attr,
0450 NULL
0451 };
0452
0453 static const struct attribute_group scd30_attr_group = {
0454 .attrs = scd30_attrs,
0455 };
0456
0457 static const struct iio_info scd30_info = {
0458 .attrs = &scd30_attr_group,
0459 .read_raw = scd30_read_raw,
0460 .write_raw = scd30_write_raw,
0461 .write_raw_get_fmt = scd30_write_raw_get_fmt,
0462 .read_avail = scd30_read_avail,
0463 };
0464
0465 #define SCD30_CHAN_SCAN_TYPE(_sign, _realbits) .scan_type = { \
0466 .sign = _sign, \
0467 .realbits = _realbits, \
0468 .storagebits = 32, \
0469 .endianness = IIO_CPU, \
0470 }
0471
0472 static const struct iio_chan_spec scd30_channels[] = {
0473 {
0474
0475
0476
0477
0478
0479 .type = IIO_PRESSURE,
0480 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0481 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW),
0482 .output = 1,
0483 .scan_index = -1,
0484 },
0485 {
0486 .type = IIO_CONCENTRATION,
0487 .channel2 = IIO_MOD_CO2,
0488 .address = SCD30_CONC,
0489 .scan_index = SCD30_CONC,
0490 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0491 BIT(IIO_CHAN_INFO_SCALE),
0492 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0493 .modified = 1,
0494
0495 SCD30_CHAN_SCAN_TYPE('u', 20),
0496 },
0497 {
0498 .type = IIO_TEMP,
0499 .address = SCD30_TEMP,
0500 .scan_index = SCD30_TEMP,
0501 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
0502 BIT(IIO_CHAN_INFO_CALIBBIAS),
0503 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS),
0504 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0505
0506 SCD30_CHAN_SCAN_TYPE('s', 18),
0507 },
0508 {
0509 .type = IIO_HUMIDITYRELATIVE,
0510 .address = SCD30_HR,
0511 .scan_index = SCD30_HR,
0512 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
0513 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0514
0515 SCD30_CHAN_SCAN_TYPE('u', 17),
0516 },
0517 IIO_CHAN_SOFT_TIMESTAMP(3),
0518 };
0519
0520 static int scd30_suspend(struct device *dev)
0521 {
0522 struct iio_dev *indio_dev = dev_get_drvdata(dev);
0523 struct scd30_state *state = iio_priv(indio_dev);
0524 int ret;
0525
0526 ret = scd30_command_write(state, CMD_STOP_MEAS, 0);
0527 if (ret)
0528 return ret;
0529
0530 return regulator_disable(state->vdd);
0531 }
0532
0533 static int scd30_resume(struct device *dev)
0534 {
0535 struct iio_dev *indio_dev = dev_get_drvdata(dev);
0536 struct scd30_state *state = iio_priv(indio_dev);
0537 int ret;
0538
0539 ret = regulator_enable(state->vdd);
0540 if (ret)
0541 return ret;
0542
0543 return scd30_command_write(state, CMD_START_MEAS, state->pressure_comp);
0544 }
0545
0546 EXPORT_NS_SIMPLE_DEV_PM_OPS(scd30_pm_ops, scd30_suspend, scd30_resume, IIO_SCD30);
0547
0548 static void scd30_stop_meas(void *data)
0549 {
0550 struct scd30_state *state = data;
0551
0552 scd30_command_write(state, CMD_STOP_MEAS, 0);
0553 }
0554
0555 static void scd30_disable_regulator(void *data)
0556 {
0557 struct scd30_state *state = data;
0558
0559 regulator_disable(state->vdd);
0560 }
0561
0562 static irqreturn_t scd30_irq_handler(int irq, void *priv)
0563 {
0564 struct iio_dev *indio_dev = priv;
0565
0566 if (iio_buffer_enabled(indio_dev)) {
0567 iio_trigger_poll(indio_dev->trig);
0568
0569 return IRQ_HANDLED;
0570 }
0571
0572 return IRQ_WAKE_THREAD;
0573 }
0574
0575 static irqreturn_t scd30_irq_thread_handler(int irq, void *priv)
0576 {
0577 struct iio_dev *indio_dev = priv;
0578 struct scd30_state *state = iio_priv(indio_dev);
0579 int ret;
0580
0581 ret = scd30_read_meas(state);
0582 if (ret)
0583 goto out;
0584
0585 complete_all(&state->meas_ready);
0586 out:
0587 return IRQ_HANDLED;
0588 }
0589
0590 static irqreturn_t scd30_trigger_handler(int irq, void *p)
0591 {
0592 struct iio_poll_func *pf = p;
0593 struct iio_dev *indio_dev = pf->indio_dev;
0594 struct scd30_state *state = iio_priv(indio_dev);
0595 struct {
0596 int data[SCD30_MEAS_COUNT];
0597 s64 ts __aligned(8);
0598 } scan;
0599 int ret;
0600
0601 mutex_lock(&state->lock);
0602 if (!iio_trigger_using_own(indio_dev))
0603 ret = scd30_read_poll(state);
0604 else
0605 ret = scd30_read_meas(state);
0606 memset(&scan, 0, sizeof(scan));
0607 memcpy(scan.data, state->meas, sizeof(state->meas));
0608 mutex_unlock(&state->lock);
0609 if (ret)
0610 goto out;
0611
0612 iio_push_to_buffers_with_timestamp(indio_dev, &scan, iio_get_time_ns(indio_dev));
0613 out:
0614 iio_trigger_notify_done(indio_dev->trig);
0615 return IRQ_HANDLED;
0616 }
0617
0618 static int scd30_set_trigger_state(struct iio_trigger *trig, bool state)
0619 {
0620 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0621 struct scd30_state *st = iio_priv(indio_dev);
0622
0623 if (state)
0624 enable_irq(st->irq);
0625 else
0626 disable_irq(st->irq);
0627
0628 return 0;
0629 }
0630
0631 static const struct iio_trigger_ops scd30_trigger_ops = {
0632 .set_trigger_state = scd30_set_trigger_state,
0633 .validate_device = iio_trigger_validate_own_device,
0634 };
0635
0636 static int scd30_setup_trigger(struct iio_dev *indio_dev)
0637 {
0638 struct scd30_state *state = iio_priv(indio_dev);
0639 struct device *dev = indio_dev->dev.parent;
0640 struct iio_trigger *trig;
0641 int ret;
0642
0643 trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
0644 iio_device_id(indio_dev));
0645 if (!trig) {
0646 dev_err(dev, "failed to allocate trigger\n");
0647 return -ENOMEM;
0648 }
0649
0650 trig->ops = &scd30_trigger_ops;
0651 iio_trigger_set_drvdata(trig, indio_dev);
0652
0653 ret = devm_iio_trigger_register(dev, trig);
0654 if (ret)
0655 return ret;
0656
0657 indio_dev->trig = iio_trigger_get(trig);
0658
0659
0660
0661
0662
0663
0664 ret = devm_request_threaded_irq(dev, state->irq, scd30_irq_handler,
0665 scd30_irq_thread_handler,
0666 IRQF_TRIGGER_HIGH | IRQF_ONESHOT |
0667 IRQF_NO_AUTOEN,
0668 indio_dev->name, indio_dev);
0669 if (ret)
0670 dev_err(dev, "failed to request irq\n");
0671
0672 return ret;
0673 }
0674
0675 int scd30_probe(struct device *dev, int irq, const char *name, void *priv,
0676 scd30_command_t command)
0677 {
0678 static const unsigned long scd30_scan_masks[] = { 0x07, 0x00 };
0679 struct scd30_state *state;
0680 struct iio_dev *indio_dev;
0681 int ret;
0682 u16 val;
0683
0684 indio_dev = devm_iio_device_alloc(dev, sizeof(*state));
0685 if (!indio_dev)
0686 return -ENOMEM;
0687
0688 state = iio_priv(indio_dev);
0689 state->dev = dev;
0690 state->priv = priv;
0691 state->irq = irq;
0692 state->pressure_comp = SCD30_PRESSURE_COMP_DEFAULT;
0693 state->meas_interval = SCD30_MEAS_INTERVAL_DEFAULT;
0694 state->command = command;
0695 mutex_init(&state->lock);
0696 init_completion(&state->meas_ready);
0697
0698 dev_set_drvdata(dev, indio_dev);
0699
0700 indio_dev->info = &scd30_info;
0701 indio_dev->name = name;
0702 indio_dev->channels = scd30_channels;
0703 indio_dev->num_channels = ARRAY_SIZE(scd30_channels);
0704 indio_dev->modes = INDIO_DIRECT_MODE;
0705 indio_dev->available_scan_masks = scd30_scan_masks;
0706
0707 state->vdd = devm_regulator_get(dev, "vdd");
0708 if (IS_ERR(state->vdd))
0709 return dev_err_probe(dev, PTR_ERR(state->vdd), "failed to get regulator\n");
0710
0711 ret = regulator_enable(state->vdd);
0712 if (ret)
0713 return ret;
0714
0715 ret = devm_add_action_or_reset(dev, scd30_disable_regulator, state);
0716 if (ret)
0717 return ret;
0718
0719 ret = scd30_reset(state);
0720 if (ret) {
0721 dev_err(dev, "failed to reset device: %d\n", ret);
0722 return ret;
0723 }
0724
0725 if (state->irq > 0) {
0726 ret = scd30_setup_trigger(indio_dev);
0727 if (ret) {
0728 dev_err(dev, "failed to setup trigger: %d\n", ret);
0729 return ret;
0730 }
0731 }
0732
0733 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, scd30_trigger_handler, NULL);
0734 if (ret)
0735 return ret;
0736
0737 ret = scd30_command_read(state, CMD_FW_VERSION, &val);
0738 if (ret) {
0739 dev_err(dev, "failed to read firmware version: %d\n", ret);
0740 return ret;
0741 }
0742 dev_info(dev, "firmware version: %d.%d\n", val >> 8, (char)val);
0743
0744 ret = scd30_command_write(state, CMD_MEAS_INTERVAL, state->meas_interval);
0745 if (ret) {
0746 dev_err(dev, "failed to set measurement interval: %d\n", ret);
0747 return ret;
0748 }
0749
0750 ret = scd30_command_write(state, CMD_START_MEAS, state->pressure_comp);
0751 if (ret) {
0752 dev_err(dev, "failed to start measurement: %d\n", ret);
0753 return ret;
0754 }
0755
0756 ret = devm_add_action_or_reset(dev, scd30_stop_meas, state);
0757 if (ret)
0758 return ret;
0759
0760 return devm_iio_device_register(dev, indio_dev);
0761 }
0762 EXPORT_SYMBOL_NS(scd30_probe, IIO_SCD30);
0763
0764 MODULE_AUTHOR("Tomasz Duszynski <tomasz.duszynski@octakon.com>");
0765 MODULE_DESCRIPTION("Sensirion SCD30 carbon dioxide sensor core driver");
0766 MODULE_LICENSE("GPL v2");