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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * AD7150 capacitive sensor driver supporting AD7150/1/6
0004  *
0005  * Copyright 2010-2011 Analog Devices Inc.
0006  * Copyright 2021 Jonathan Cameron <Jonathan.Cameron@huawei.com>
0007  */
0008 
0009 #include <linux/bitfield.h>
0010 #include <linux/device.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/irq.h>
0013 #include <linux/i2c.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/mod_devicetable.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/slab.h>
0019 
0020 #include <linux/iio/iio.h>
0021 #include <linux/iio/sysfs.h>
0022 #include <linux/iio/events.h>
0023 
0024 #define AD7150_STATUS_REG       0
0025 #define   AD7150_STATUS_OUT1        BIT(3)
0026 #define   AD7150_STATUS_OUT2        BIT(5)
0027 #define AD7150_CH1_DATA_HIGH_REG    1
0028 #define AD7150_CH2_DATA_HIGH_REG    3
0029 #define AD7150_CH1_AVG_HIGH_REG     5
0030 #define AD7150_CH2_AVG_HIGH_REG     7
0031 #define AD7150_CH1_SENSITIVITY_REG  9
0032 #define AD7150_CH1_THR_HOLD_H_REG   9
0033 #define AD7150_CH1_TIMEOUT_REG      10
0034 #define   AD7150_CH_TIMEOUT_RECEDING    GENMASK(3, 0)
0035 #define   AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)
0036 #define AD7150_CH1_SETUP_REG        11
0037 #define AD7150_CH2_SENSITIVITY_REG  12
0038 #define AD7150_CH2_THR_HOLD_H_REG   12
0039 #define AD7150_CH2_TIMEOUT_REG      13
0040 #define AD7150_CH2_SETUP_REG        14
0041 #define AD7150_CFG_REG          15
0042 #define   AD7150_CFG_FIX        BIT(7)
0043 #define   AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5)
0044 #define   AD7150_CFG_TT_NEG     0x0
0045 #define   AD7150_CFG_TT_POS     0x1
0046 #define   AD7150_CFG_TT_IN_WINDOW   0x2
0047 #define   AD7150_CFG_TT_OUT_WINDOW  0x3
0048 #define AD7150_PD_TIMER_REG     16
0049 #define AD7150_CH1_CAPDAC_REG       17
0050 #define AD7150_CH2_CAPDAC_REG       18
0051 #define AD7150_SN3_REG          19
0052 #define AD7150_SN2_REG          20
0053 #define AD7150_SN1_REG          21
0054 #define AD7150_SN0_REG          22
0055 #define AD7150_ID_REG           23
0056 
0057 enum {
0058     AD7150,
0059     AD7151,
0060 };
0061 
0062 /**
0063  * struct ad7150_chip_info - instance specific chip data
0064  * @client: i2c client for this device
0065  * @threshold: thresholds for simple capacitance value events
0066  * @thresh_sensitivity: threshold for simple capacitance offset
0067  *  from 'average' value.
0068  * @thresh_timeout: a timeout, in samples from the moment an
0069  *  adaptive threshold event occurs to when the average
0070  *  value jumps to current value.  Note made up of two fields,
0071  *      3:0 are for timeout receding - applies if below lower threshold
0072  *      7:4 are for timeout approaching - applies if above upper threshold
0073  * @state_lock: ensure consistent state of this structure wrt the
0074  *  hardware.
0075  * @interrupts: one or two interrupt numbers depending on device type.
0076  * @int_enabled: is a given interrupt currently enabled.
0077  * @type: threshold type
0078  * @dir: threshold direction
0079  */
0080 struct ad7150_chip_info {
0081     struct i2c_client *client;
0082     u16 threshold[2][2];
0083     u8 thresh_sensitivity[2][2];
0084     u8 thresh_timeout[2][2];
0085     struct mutex state_lock;
0086     int interrupts[2];
0087     bool int_enabled[2];
0088     enum iio_event_type type;
0089     enum iio_event_direction dir;
0090 };
0091 
0092 static const u8 ad7150_addresses[][6] = {
0093     { AD7150_CH1_DATA_HIGH_REG, AD7150_CH1_AVG_HIGH_REG,
0094       AD7150_CH1_SETUP_REG, AD7150_CH1_THR_HOLD_H_REG,
0095       AD7150_CH1_SENSITIVITY_REG, AD7150_CH1_TIMEOUT_REG },
0096     { AD7150_CH2_DATA_HIGH_REG, AD7150_CH2_AVG_HIGH_REG,
0097       AD7150_CH2_SETUP_REG, AD7150_CH2_THR_HOLD_H_REG,
0098       AD7150_CH2_SENSITIVITY_REG, AD7150_CH2_TIMEOUT_REG },
0099 };
0100 
0101 static int ad7150_read_raw(struct iio_dev *indio_dev,
0102                struct iio_chan_spec const *chan,
0103                int *val,
0104                int *val2,
0105                long mask)
0106 {
0107     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0108     int channel = chan->channel;
0109     int ret;
0110 
0111     switch (mask) {
0112     case IIO_CHAN_INFO_RAW:
0113         ret = i2c_smbus_read_word_swapped(chip->client,
0114                           ad7150_addresses[channel][0]);
0115         if (ret < 0)
0116             return ret;
0117         *val = ret >> 4;
0118 
0119         return IIO_VAL_INT;
0120     case IIO_CHAN_INFO_AVERAGE_RAW:
0121         ret = i2c_smbus_read_word_swapped(chip->client,
0122                           ad7150_addresses[channel][1]);
0123         if (ret < 0)
0124             return ret;
0125         *val = ret;
0126 
0127         return IIO_VAL_INT;
0128     case IIO_CHAN_INFO_SCALE:
0129         /*
0130          * Base units for capacitance are nano farads and the value
0131          * calculated from the datasheet formula is in picofarad
0132          * so multiply by 1000
0133          */
0134         *val = 1000;
0135         *val2 = 40944 >> 4; /* To match shift in _RAW */
0136         return IIO_VAL_FRACTIONAL;
0137     case IIO_CHAN_INFO_OFFSET:
0138         *val = -(12288 >> 4); /* To match shift in _RAW */
0139         return IIO_VAL_INT;
0140     case IIO_CHAN_INFO_SAMP_FREQ:
0141         /* Strangely same for both 1 and 2 chan parts */
0142         *val = 100;
0143         return IIO_VAL_INT;
0144     default:
0145         return -EINVAL;
0146     }
0147 }
0148 
0149 static int ad7150_read_event_config(struct iio_dev *indio_dev,
0150                     const struct iio_chan_spec *chan,
0151                     enum iio_event_type type,
0152                     enum iio_event_direction dir)
0153 {
0154     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0155     u8 threshtype;
0156     bool thrfixed;
0157     int ret;
0158 
0159     ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
0160     if (ret < 0)
0161         return ret;
0162 
0163     threshtype = FIELD_GET(AD7150_CFG_THRESHTYPE_MSK, ret);
0164 
0165     /*check if threshold mode is fixed or adaptive*/
0166     thrfixed = FIELD_GET(AD7150_CFG_FIX, ret);
0167 
0168     switch (type) {
0169     case IIO_EV_TYPE_THRESH_ADAPTIVE:
0170         if (dir == IIO_EV_DIR_RISING)
0171             return !thrfixed && (threshtype == AD7150_CFG_TT_POS);
0172         return !thrfixed && (threshtype == AD7150_CFG_TT_NEG);
0173     case IIO_EV_TYPE_THRESH:
0174         if (dir == IIO_EV_DIR_RISING)
0175             return thrfixed && (threshtype == AD7150_CFG_TT_POS);
0176         return thrfixed && (threshtype == AD7150_CFG_TT_NEG);
0177     default:
0178         break;
0179     }
0180     return -EINVAL;
0181 }
0182 
0183 /* state_lock should be held to ensure consistent state */
0184 static int ad7150_write_event_params(struct iio_dev *indio_dev,
0185                      unsigned int chan,
0186                      enum iio_event_type type,
0187                      enum iio_event_direction dir)
0188 {
0189     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0190     int rising = (dir == IIO_EV_DIR_RISING);
0191 
0192     /* Only update value live, if parameter is in use */
0193     if ((type != chip->type) || (dir != chip->dir))
0194         return 0;
0195 
0196     switch (type) {
0197         /* Note completely different from the adaptive versions */
0198     case IIO_EV_TYPE_THRESH: {
0199         u16 value = chip->threshold[rising][chan];
0200         return i2c_smbus_write_word_swapped(chip->client,
0201                             ad7150_addresses[chan][3],
0202                             value);
0203     }
0204     case IIO_EV_TYPE_THRESH_ADAPTIVE: {
0205         int ret;
0206         u8 sens, timeout;
0207 
0208         sens = chip->thresh_sensitivity[rising][chan];
0209         ret = i2c_smbus_write_byte_data(chip->client,
0210                         ad7150_addresses[chan][4],
0211                         sens);
0212         if (ret)
0213             return ret;
0214 
0215         /*
0216          * Single timeout register contains timeouts for both
0217          * directions.
0218          */
0219         timeout = FIELD_PREP(AD7150_CH_TIMEOUT_APPROACHING,
0220                      chip->thresh_timeout[1][chan]);
0221         timeout |= FIELD_PREP(AD7150_CH_TIMEOUT_RECEDING,
0222                       chip->thresh_timeout[0][chan]);
0223         return i2c_smbus_write_byte_data(chip->client,
0224                          ad7150_addresses[chan][5],
0225                          timeout);
0226     }
0227     default:
0228         return -EINVAL;
0229     }
0230 }
0231 
0232 static int ad7150_write_event_config(struct iio_dev *indio_dev,
0233                      const struct iio_chan_spec *chan,
0234                      enum iio_event_type type,
0235                      enum iio_event_direction dir, int state)
0236 {
0237     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0238     int ret = 0;
0239 
0240     /*
0241      * There is only a single shared control and no on chip
0242      * interrupt disables for the two interrupt lines.
0243      * So, enabling will switch the events configured to enable
0244      * whatever was most recently requested and if necessary enable_irq()
0245      * the interrupt and any disable will disable_irq() for that
0246      * channels interrupt.
0247      */
0248     if (!state) {
0249         if ((chip->int_enabled[chan->channel]) &&
0250             (type == chip->type) && (dir == chip->dir)) {
0251             disable_irq(chip->interrupts[chan->channel]);
0252             chip->int_enabled[chan->channel] = false;
0253         }
0254         return 0;
0255     }
0256 
0257     mutex_lock(&chip->state_lock);
0258     if ((type != chip->type) || (dir != chip->dir)) {
0259         int rising = (dir == IIO_EV_DIR_RISING);
0260         u8 thresh_type, cfg, fixed;
0261 
0262         /*
0263          * Need to temporarily disable both interrupts if
0264          * enabled - this is to avoid races around changing
0265          * config and thresholds.
0266          * Note enable/disable_irq() are reference counted so
0267          * no need to check if already enabled.
0268          */
0269         disable_irq(chip->interrupts[0]);
0270         disable_irq(chip->interrupts[1]);
0271 
0272         ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
0273         if (ret < 0)
0274             goto error_ret;
0275 
0276         cfg = ret & ~(AD7150_CFG_THRESHTYPE_MSK | AD7150_CFG_FIX);
0277 
0278         if (type == IIO_EV_TYPE_THRESH_ADAPTIVE)
0279             fixed = 0;
0280         else
0281             fixed = 1;
0282 
0283         if (rising)
0284             thresh_type = AD7150_CFG_TT_POS;
0285         else
0286             thresh_type = AD7150_CFG_TT_NEG;
0287 
0288         cfg |= FIELD_PREP(AD7150_CFG_FIX, fixed) |
0289             FIELD_PREP(AD7150_CFG_THRESHTYPE_MSK, thresh_type);
0290 
0291         ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG_REG,
0292                         cfg);
0293         if (ret < 0)
0294             goto error_ret;
0295 
0296         /*
0297          * There is a potential race condition here, but not easy
0298          * to close given we can't disable the interrupt at the
0299          * chip side of things. Rely on the status bit.
0300          */
0301         chip->type = type;
0302         chip->dir = dir;
0303 
0304         /* update control attributes */
0305         ret = ad7150_write_event_params(indio_dev, chan->channel, type,
0306                         dir);
0307         if (ret)
0308             goto error_ret;
0309         /* reenable any irq's we disabled whilst changing mode */
0310         enable_irq(chip->interrupts[0]);
0311         enable_irq(chip->interrupts[1]);
0312     }
0313     if (!chip->int_enabled[chan->channel]) {
0314         enable_irq(chip->interrupts[chan->channel]);
0315         chip->int_enabled[chan->channel] = true;
0316     }
0317 
0318 error_ret:
0319     mutex_unlock(&chip->state_lock);
0320 
0321     return ret;
0322 }
0323 
0324 static int ad7150_read_event_value(struct iio_dev *indio_dev,
0325                    const struct iio_chan_spec *chan,
0326                    enum iio_event_type type,
0327                    enum iio_event_direction dir,
0328                    enum iio_event_info info,
0329                    int *val, int *val2)
0330 {
0331     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0332     int rising = (dir == IIO_EV_DIR_RISING);
0333 
0334     /* Complex register sharing going on here */
0335     switch (info) {
0336     case IIO_EV_INFO_VALUE:
0337         switch (type) {
0338         case IIO_EV_TYPE_THRESH_ADAPTIVE:
0339             *val = chip->thresh_sensitivity[rising][chan->channel];
0340             return IIO_VAL_INT;
0341         case IIO_EV_TYPE_THRESH:
0342             *val = chip->threshold[rising][chan->channel];
0343             return IIO_VAL_INT;
0344         default:
0345             return -EINVAL;
0346         }
0347     case IIO_EV_INFO_TIMEOUT:
0348         *val = 0;
0349         *val2 = chip->thresh_timeout[rising][chan->channel] * 10000;
0350         return IIO_VAL_INT_PLUS_MICRO;
0351     default:
0352         return -EINVAL;
0353     }
0354 }
0355 
0356 static int ad7150_write_event_value(struct iio_dev *indio_dev,
0357                     const struct iio_chan_spec *chan,
0358                     enum iio_event_type type,
0359                     enum iio_event_direction dir,
0360                     enum iio_event_info info,
0361                     int val, int val2)
0362 {
0363     int ret;
0364     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0365     int rising = (dir == IIO_EV_DIR_RISING);
0366 
0367     mutex_lock(&chip->state_lock);
0368     switch (info) {
0369     case IIO_EV_INFO_VALUE:
0370         switch (type) {
0371         case IIO_EV_TYPE_THRESH_ADAPTIVE:
0372             chip->thresh_sensitivity[rising][chan->channel] = val;
0373             break;
0374         case IIO_EV_TYPE_THRESH:
0375             chip->threshold[rising][chan->channel] = val;
0376             break;
0377         default:
0378             ret = -EINVAL;
0379             goto error_ret;
0380         }
0381         break;
0382     case IIO_EV_INFO_TIMEOUT: {
0383         /*
0384          * Raw timeout is in cycles of 10 msecs as long as both
0385          * channels are enabled.
0386          * In terms of INT_PLUS_MICRO, that is in units of 10,000
0387          */
0388         int timeout = val2 / 10000;
0389 
0390         if (val != 0 || timeout < 0 || timeout > 15 || val2 % 10000) {
0391             ret = -EINVAL;
0392             goto error_ret;
0393         }
0394 
0395         chip->thresh_timeout[rising][chan->channel] = timeout;
0396         break;
0397     }
0398     default:
0399         ret = -EINVAL;
0400         goto error_ret;
0401     }
0402 
0403     /* write back if active */
0404     ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir);
0405 
0406 error_ret:
0407     mutex_unlock(&chip->state_lock);
0408     return ret;
0409 }
0410 
0411 static const struct iio_event_spec ad7150_events[] = {
0412     {
0413         .type = IIO_EV_TYPE_THRESH,
0414         .dir = IIO_EV_DIR_RISING,
0415         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0416             BIT(IIO_EV_INFO_ENABLE),
0417     }, {
0418         .type = IIO_EV_TYPE_THRESH,
0419         .dir = IIO_EV_DIR_FALLING,
0420         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0421             BIT(IIO_EV_INFO_ENABLE),
0422     }, {
0423         .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
0424         .dir = IIO_EV_DIR_RISING,
0425         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0426             BIT(IIO_EV_INFO_ENABLE) |
0427             BIT(IIO_EV_INFO_TIMEOUT),
0428     }, {
0429         .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
0430         .dir = IIO_EV_DIR_FALLING,
0431         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0432             BIT(IIO_EV_INFO_ENABLE) |
0433             BIT(IIO_EV_INFO_TIMEOUT),
0434     },
0435 };
0436 
0437 #define AD7150_CAPACITANCE_CHAN(_chan)  {           \
0438         .type = IIO_CAPACITANCE,            \
0439         .indexed = 1,                   \
0440         .channel = _chan,               \
0441         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
0442         BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
0443         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
0444             BIT(IIO_CHAN_INFO_OFFSET),      \
0445         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
0446         .event_spec = ad7150_events,            \
0447         .num_event_specs = ARRAY_SIZE(ad7150_events),   \
0448     }
0449 
0450 #define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan)   {       \
0451         .type = IIO_CAPACITANCE,            \
0452         .indexed = 1,                   \
0453         .channel = _chan,               \
0454         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
0455         BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
0456         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
0457             BIT(IIO_CHAN_INFO_OFFSET),      \
0458         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
0459     }
0460 
0461 static const struct iio_chan_spec ad7150_channels[] = {
0462     AD7150_CAPACITANCE_CHAN(0),
0463     AD7150_CAPACITANCE_CHAN(1),
0464 };
0465 
0466 static const struct iio_chan_spec ad7150_channels_no_irq[] = {
0467     AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
0468     AD7150_CAPACITANCE_CHAN_NO_IRQ(1),
0469 };
0470 
0471 static const struct iio_chan_spec ad7151_channels[] = {
0472     AD7150_CAPACITANCE_CHAN(0),
0473 };
0474 
0475 static const struct iio_chan_spec ad7151_channels_no_irq[] = {
0476     AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
0477 };
0478 
0479 static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask,
0480                       int channel)
0481 {
0482     struct iio_dev *indio_dev = private;
0483     struct ad7150_chip_info *chip = iio_priv(indio_dev);
0484     s64 timestamp = iio_get_time_ns(indio_dev);
0485     int int_status;
0486 
0487     int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS_REG);
0488     if (int_status < 0)
0489         return IRQ_HANDLED;
0490 
0491     if (!(int_status & status_mask))
0492         return IRQ_HANDLED;
0493 
0494     iio_push_event(indio_dev,
0495                IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, channel,
0496                         chip->type, chip->dir),
0497                timestamp);
0498 
0499     return IRQ_HANDLED;
0500 }
0501 
0502 static irqreturn_t ad7150_event_handler_ch1(int irq, void *private)
0503 {
0504     return __ad7150_event_handler(private, AD7150_STATUS_OUT1, 0);
0505 }
0506 
0507 static irqreturn_t ad7150_event_handler_ch2(int irq, void *private)
0508 {
0509     return __ad7150_event_handler(private, AD7150_STATUS_OUT2, 1);
0510 }
0511 
0512 static IIO_CONST_ATTR(in_capacitance_thresh_adaptive_timeout_available,
0513               "[0 0.01 0.15]");
0514 
0515 static struct attribute *ad7150_event_attributes[] = {
0516     &iio_const_attr_in_capacitance_thresh_adaptive_timeout_available
0517     .dev_attr.attr,
0518     NULL,
0519 };
0520 
0521 static const struct attribute_group ad7150_event_attribute_group = {
0522     .attrs = ad7150_event_attributes,
0523     .name = "events",
0524 };
0525 
0526 static const struct iio_info ad7150_info = {
0527     .event_attrs = &ad7150_event_attribute_group,
0528     .read_raw = &ad7150_read_raw,
0529     .read_event_config = &ad7150_read_event_config,
0530     .write_event_config = &ad7150_write_event_config,
0531     .read_event_value = &ad7150_read_event_value,
0532     .write_event_value = &ad7150_write_event_value,
0533 };
0534 
0535 static const struct iio_info ad7150_info_no_irq = {
0536     .read_raw = &ad7150_read_raw,
0537 };
0538 
0539 static void ad7150_reg_disable(void *data)
0540 {
0541     struct regulator *reg = data;
0542 
0543     regulator_disable(reg);
0544 }
0545 
0546 static int ad7150_probe(struct i2c_client *client,
0547             const struct i2c_device_id *id)
0548 {
0549     struct ad7150_chip_info *chip;
0550     struct iio_dev *indio_dev;
0551     struct regulator *reg;
0552     int ret;
0553 
0554     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
0555     if (!indio_dev)
0556         return -ENOMEM;
0557 
0558     chip = iio_priv(indio_dev);
0559     mutex_init(&chip->state_lock);
0560     chip->client = client;
0561 
0562     indio_dev->name = id->name;
0563 
0564     indio_dev->modes = INDIO_DIRECT_MODE;
0565 
0566     reg = devm_regulator_get(&client->dev, "vdd");
0567     if (IS_ERR(reg))
0568         return PTR_ERR(reg);
0569 
0570     ret = regulator_enable(reg);
0571     if (ret)
0572         return ret;
0573 
0574     ret = devm_add_action_or_reset(&client->dev, ad7150_reg_disable, reg);
0575     if (ret)
0576         return ret;
0577 
0578     chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0);
0579     if (chip->interrupts[0] < 0)
0580         return chip->interrupts[0];
0581     if (id->driver_data == AD7150) {
0582         chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1);
0583         if (chip->interrupts[1] < 0)
0584             return chip->interrupts[1];
0585     }
0586     if (chip->interrupts[0] &&
0587         (id->driver_data == AD7151 || chip->interrupts[1])) {
0588         irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN);
0589         ret = devm_request_threaded_irq(&client->dev,
0590                         chip->interrupts[0],
0591                         NULL,
0592                         &ad7150_event_handler_ch1,
0593                         IRQF_TRIGGER_RISING |
0594                         IRQF_ONESHOT,
0595                         "ad7150_irq1",
0596                         indio_dev);
0597         if (ret)
0598             return ret;
0599 
0600         indio_dev->info = &ad7150_info;
0601         switch (id->driver_data) {
0602         case AD7150:
0603             indio_dev->channels = ad7150_channels;
0604             indio_dev->num_channels = ARRAY_SIZE(ad7150_channels);
0605             irq_set_status_flags(chip->interrupts[1], IRQ_NOAUTOEN);
0606             ret = devm_request_threaded_irq(&client->dev,
0607                             chip->interrupts[1],
0608                             NULL,
0609                             &ad7150_event_handler_ch2,
0610                             IRQF_TRIGGER_RISING |
0611                             IRQF_ONESHOT,
0612                             "ad7150_irq2",
0613                             indio_dev);
0614             if (ret)
0615                 return ret;
0616             break;
0617         case AD7151:
0618             indio_dev->channels = ad7151_channels;
0619             indio_dev->num_channels = ARRAY_SIZE(ad7151_channels);
0620             break;
0621         default:
0622             return -EINVAL;
0623         }
0624 
0625     } else {
0626         indio_dev->info = &ad7150_info_no_irq;
0627         switch (id->driver_data) {
0628         case AD7150:
0629             indio_dev->channels = ad7150_channels_no_irq;
0630             indio_dev->num_channels =
0631                 ARRAY_SIZE(ad7150_channels_no_irq);
0632             break;
0633         case AD7151:
0634             indio_dev->channels = ad7151_channels_no_irq;
0635             indio_dev->num_channels =
0636                 ARRAY_SIZE(ad7151_channels_no_irq);
0637             break;
0638         default:
0639             return -EINVAL;
0640         }
0641     }
0642 
0643     return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
0644 }
0645 
0646 static const struct i2c_device_id ad7150_id[] = {
0647     { "ad7150", AD7150 },
0648     { "ad7151", AD7151 },
0649     { "ad7156", AD7150 },
0650     {}
0651 };
0652 
0653 MODULE_DEVICE_TABLE(i2c, ad7150_id);
0654 
0655 static const struct of_device_id ad7150_of_match[] = {
0656     { "adi,ad7150" },
0657     { "adi,ad7151" },
0658     { "adi,ad7156" },
0659     {}
0660 };
0661 static struct i2c_driver ad7150_driver = {
0662     .driver = {
0663         .name = "ad7150",
0664         .of_match_table = ad7150_of_match,
0665     },
0666     .probe = ad7150_probe,
0667     .id_table = ad7150_id,
0668 };
0669 module_i2c_driver(ad7150_driver);
0670 
0671 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
0672 MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver");
0673 MODULE_LICENSE("GPL v2");
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