Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2021 Analog Devices, Inc.
0004  * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
0005  */
0006 
0007 #include <asm/unaligned.h>
0008 #include <linux/bitfield.h>
0009 #include <linux/crc8.h>
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/gpio/driver.h>
0013 #include <linux/iio/buffer.h>
0014 #include <linux/iio/iio.h>
0015 #include <linux/iio/sysfs.h>
0016 #include <linux/iio/trigger.h>
0017 #include <linux/iio/trigger_consumer.h>
0018 #include <linux/iio/triggered_buffer.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/property.h>
0022 #include <linux/regmap.h>
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/spi/spi.h>
0025 
0026 #include <dt-bindings/iio/addac/adi,ad74413r.h>
0027 
0028 #define AD74413R_CRC_POLYNOMIAL 0x7
0029 DECLARE_CRC8_TABLE(ad74413r_crc8_table);
0030 
0031 #define AD74413R_CHANNEL_MAX    4
0032 
0033 #define AD74413R_FRAME_SIZE 4
0034 
0035 struct ad74413r_chip_info {
0036     const char  *name;
0037     bool        hart_support;
0038 };
0039 
0040 struct ad74413r_channel_config {
0041     u32     func;
0042     bool        gpo_comparator;
0043     bool        initialized;
0044 };
0045 
0046 struct ad74413r_channels {
0047     struct iio_chan_spec    *channels;
0048     unsigned int        num_channels;
0049 };
0050 
0051 struct ad74413r_state {
0052     struct ad74413r_channel_config  channel_configs[AD74413R_CHANNEL_MAX];
0053     unsigned int            gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
0054     unsigned int            comp_gpio_offsets[AD74413R_CHANNEL_MAX];
0055     struct gpio_chip        gpo_gpiochip;
0056     struct gpio_chip        comp_gpiochip;
0057     struct completion       adc_data_completion;
0058     unsigned int            num_gpo_gpios;
0059     unsigned int            num_comparator_gpios;
0060     u32             sense_resistor_ohms;
0061 
0062     /*
0063      * Synchronize consecutive operations when doing a one-shot
0064      * conversion and when updating the ADC samples SPI message.
0065      */
0066     struct mutex            lock;
0067 
0068     const struct ad74413r_chip_info *chip_info;
0069     struct spi_device       *spi;
0070     struct regulator        *refin_reg;
0071     struct regmap           *regmap;
0072     struct device           *dev;
0073     struct iio_trigger      *trig;
0074 
0075     size_t          adc_active_channels;
0076     struct spi_message  adc_samples_msg;
0077     struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
0078 
0079     /*
0080      * DMA (thus cache coherency maintenance) may require the
0081      * transfer buffers to live in their own cache lines.
0082      */
0083     struct {
0084         u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
0085         s64 timestamp;
0086     } adc_samples_buf __aligned(IIO_DMA_MINALIGN);
0087 
0088     u8  adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
0089     u8  reg_tx_buf[AD74413R_FRAME_SIZE];
0090     u8  reg_rx_buf[AD74413R_FRAME_SIZE];
0091 };
0092 
0093 #define AD74413R_REG_NOP        0x00
0094 
0095 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
0096 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
0097 
0098 #define AD74413R_REG_ADC_CONFIG_X(x)        (0x05 + (x))
0099 #define AD74413R_ADC_CONFIG_RANGE_MASK      GENMASK(7, 5)
0100 #define AD74413R_ADC_CONFIG_REJECTION_MASK  GENMASK(4, 3)
0101 #define AD74413R_ADC_RANGE_10V          0b000
0102 #define AD74413R_ADC_RANGE_2P5V_EXT_POW     0b001
0103 #define AD74413R_ADC_RANGE_2P5V_INT_POW     0b010
0104 #define AD74413R_ADC_RANGE_5V_BI_DIR        0b011
0105 #define AD74413R_ADC_REJECTION_50_60        0b00
0106 #define AD74413R_ADC_REJECTION_NONE     0b01
0107 #define AD74413R_ADC_REJECTION_50_60_HART   0b10
0108 #define AD74413R_ADC_REJECTION_HART     0b11
0109 
0110 #define AD74413R_REG_DIN_CONFIG_X(x)    (0x09 + (x))
0111 #define AD74413R_DIN_DEBOUNCE_MASK  GENMASK(4, 0)
0112 #define AD74413R_DIN_DEBOUNCE_LEN   BIT(5)
0113 
0114 #define AD74413R_REG_DAC_CODE_X(x)  (0x16 + (x))
0115 #define AD74413R_DAC_CODE_MAX       GENMASK(12, 0)
0116 #define AD74413R_DAC_VOLTAGE_MAX    11000
0117 
0118 #define AD74413R_REG_GPO_PAR_DATA       0x0d
0119 #define AD74413R_REG_GPO_CONFIG_X(x)        (0x0e + (x))
0120 #define AD74413R_GPO_CONFIG_DATA_MASK   BIT(3)
0121 #define AD74413R_GPO_CONFIG_SELECT_MASK     GENMASK(2, 0)
0122 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN  0b000
0123 #define AD74413R_GPO_CONFIG_LOGIC       0b001
0124 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL  0b010
0125 #define AD74413R_GPO_CONFIG_COMPARATOR      0b011
0126 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE  0b100
0127 
0128 #define AD74413R_REG_ADC_CONV_CTRL  0x23
0129 #define AD74413R_CONV_SEQ_MASK      GENMASK(9, 8)
0130 #define AD74413R_CONV_SEQ_ON        0b00
0131 #define AD74413R_CONV_SEQ_SINGLE    0b01
0132 #define AD74413R_CONV_SEQ_CONTINUOUS    0b10
0133 #define AD74413R_CONV_SEQ_OFF       0b11
0134 #define AD74413R_CH_EN_MASK(x)      BIT(x)
0135 
0136 #define AD74413R_REG_DIN_COMP_OUT       0x25
0137 
0138 #define AD74413R_REG_ADC_RESULT_X(x)    (0x26 + (x))
0139 #define AD74413R_ADC_RESULT_MAX     GENMASK(15, 0)
0140 
0141 #define AD74413R_REG_READ_SELECT    0x41
0142 
0143 #define AD74413R_REG_CMD_KEY        0x44
0144 #define AD74413R_CMD_KEY_LDAC       0x953a
0145 #define AD74413R_CMD_KEY_RESET1     0x15fa
0146 #define AD74413R_CMD_KEY_RESET2     0xaf51
0147 
0148 static const int ad74413r_adc_sampling_rates[] = {
0149     20, 4800,
0150 };
0151 
0152 static const int ad74413r_adc_sampling_rates_hart[] = {
0153     10, 20, 1200, 4800,
0154 };
0155 
0156 static int ad74413r_crc(u8 *buf)
0157 {
0158     return crc8(ad74413r_crc8_table, buf, 3, 0);
0159 }
0160 
0161 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
0162 {
0163     buf[0] = reg;
0164     put_unaligned_be16(val, &buf[1]);
0165     buf[3] = ad74413r_crc(buf);
0166 }
0167 
0168 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
0169 {
0170     struct ad74413r_state *st = context;
0171 
0172     ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
0173 
0174     return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
0175 }
0176 
0177 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
0178 {
0179     u8 expected_crc = ad74413r_crc(buf);
0180 
0181     if (buf[3] != expected_crc) {
0182         dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
0183             buf[3], buf[0], buf[1], buf[2]);
0184         return -EINVAL;
0185     }
0186 
0187     return 0;
0188 }
0189 
0190 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
0191 {
0192     struct ad74413r_state *st = context;
0193     struct spi_transfer reg_read_xfer[] = {
0194         {
0195             .tx_buf = st->reg_tx_buf,
0196             .len = AD74413R_FRAME_SIZE,
0197             .cs_change = 1,
0198         },
0199         {
0200             .rx_buf = st->reg_rx_buf,
0201             .len = AD74413R_FRAME_SIZE,
0202         },
0203     };
0204     int ret;
0205 
0206     ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
0207                   st->reg_tx_buf);
0208 
0209     ret = spi_sync_transfer(st->spi, reg_read_xfer,
0210                 ARRAY_SIZE(reg_read_xfer));
0211     if (ret)
0212         return ret;
0213 
0214     ret = ad74413r_crc_check(st, st->reg_rx_buf);
0215     if (ret)
0216         return ret;
0217 
0218     *val = get_unaligned_be16(&st->reg_rx_buf[1]);
0219 
0220     return 0;
0221 }
0222 
0223 static const struct regmap_config ad74413r_regmap_config = {
0224     .reg_bits = 8,
0225     .val_bits = 16,
0226     .reg_read = ad74413r_reg_read,
0227     .reg_write = ad74413r_reg_write,
0228 };
0229 
0230 static int ad74413r_set_gpo_config(struct ad74413r_state *st,
0231                    unsigned int offset, u8 mode)
0232 {
0233     return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
0234                   AD74413R_GPO_CONFIG_SELECT_MASK, mode);
0235 }
0236 
0237 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
0238     0,     13,    18,    24,    32,    42,    56,    75,
0239     100,   130,   180,   240,   320,   420,   560,   750,
0240     1000,  1300,  1800,  2400,  3200,  4200,  5600,  7500,
0241     10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
0242 };
0243 
0244 static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
0245                       unsigned int offset,
0246                       unsigned int debounce)
0247 {
0248     unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
0249     unsigned int i;
0250 
0251     for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
0252         if (debounce <= ad74413r_debounce_map[i]) {
0253             val = i;
0254             break;
0255         }
0256 
0257     return regmap_update_bits(st->regmap,
0258                   AD74413R_REG_DIN_CONFIG_X(offset),
0259                   AD74413R_DIN_DEBOUNCE_MASK,
0260                   val);
0261 }
0262 
0263 static void ad74413r_gpio_set(struct gpio_chip *chip,
0264                   unsigned int offset, int val)
0265 {
0266     struct ad74413r_state *st = gpiochip_get_data(chip);
0267     unsigned int real_offset = st->gpo_gpio_offsets[offset];
0268     int ret;
0269 
0270     ret = ad74413r_set_gpo_config(st, real_offset,
0271                       AD74413R_GPO_CONFIG_LOGIC);
0272     if (ret)
0273         return;
0274 
0275     regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset),
0276                AD74413R_GPO_CONFIG_DATA_MASK,
0277                val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
0278 }
0279 
0280 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip,
0281                        unsigned long *mask,
0282                        unsigned long *bits)
0283 {
0284     struct ad74413r_state *st = gpiochip_get_data(chip);
0285     unsigned long real_mask = 0;
0286     unsigned long real_bits = 0;
0287     unsigned int offset;
0288     int ret;
0289 
0290     for_each_set_bit(offset, mask, chip->ngpio) {
0291         unsigned int real_offset = st->gpo_gpio_offsets[offset];
0292 
0293         ret = ad74413r_set_gpo_config(st, real_offset,
0294             AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
0295         if (ret)
0296             return;
0297 
0298         real_mask |= BIT(real_offset);
0299         if (*bits & offset)
0300             real_bits |= BIT(real_offset);
0301     }
0302 
0303     regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
0304                real_mask, real_bits);
0305 }
0306 
0307 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
0308 {
0309     struct ad74413r_state *st = gpiochip_get_data(chip);
0310     unsigned int real_offset = st->comp_gpio_offsets[offset];
0311     unsigned int status;
0312     int ret;
0313 
0314     ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
0315     if (ret)
0316         return ret;
0317 
0318     status &= BIT(real_offset);
0319 
0320     return status ? 1 : 0;
0321 }
0322 
0323 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
0324                       unsigned long *mask,
0325                       unsigned long *bits)
0326 {
0327     struct ad74413r_state *st = gpiochip_get_data(chip);
0328     unsigned int offset;
0329     unsigned int val;
0330     int ret;
0331 
0332     ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
0333     if (ret)
0334         return ret;
0335 
0336     for_each_set_bit(offset, mask, chip->ngpio) {
0337         unsigned int real_offset = st->comp_gpio_offsets[offset];
0338 
0339         __assign_bit(offset, bits, val & BIT(real_offset));
0340     }
0341 
0342     return ret;
0343 }
0344 
0345 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
0346                        unsigned int offset)
0347 {
0348     return GPIO_LINE_DIRECTION_OUT;
0349 }
0350 
0351 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
0352                         unsigned int offset)
0353 {
0354     return GPIO_LINE_DIRECTION_IN;
0355 }
0356 
0357 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
0358                     unsigned int offset,
0359                     unsigned long config)
0360 {
0361     struct ad74413r_state *st = gpiochip_get_data(chip);
0362     unsigned int real_offset = st->gpo_gpio_offsets[offset];
0363 
0364     switch (pinconf_to_config_param(config)) {
0365     case PIN_CONFIG_BIAS_PULL_DOWN:
0366         return ad74413r_set_gpo_config(st, real_offset,
0367             AD74413R_GPO_CONFIG_100K_PULL_DOWN);
0368     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0369         return ad74413r_set_gpo_config(st, real_offset,
0370             AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
0371     default:
0372         return -ENOTSUPP;
0373     }
0374 }
0375 
0376 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
0377                      unsigned int offset,
0378                      unsigned long config)
0379 {
0380     struct ad74413r_state *st = gpiochip_get_data(chip);
0381     unsigned int real_offset = st->comp_gpio_offsets[offset];
0382 
0383     switch (pinconf_to_config_param(config)) {
0384     case PIN_CONFIG_INPUT_DEBOUNCE:
0385         return ad74413r_set_comp_debounce(st, real_offset,
0386             pinconf_to_config_argument(config));
0387     default:
0388         return -ENOTSUPP;
0389     }
0390 }
0391 
0392 static int ad74413r_reset(struct ad74413r_state *st)
0393 {
0394     int ret;
0395 
0396     ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
0397                AD74413R_CMD_KEY_RESET1);
0398     if (ret)
0399         return ret;
0400 
0401     return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
0402                 AD74413R_CMD_KEY_RESET2);
0403 }
0404 
0405 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
0406                      unsigned int channel, int dac_code)
0407 {
0408     struct reg_sequence reg_seq[2] = {
0409         { AD74413R_REG_DAC_CODE_X(channel), dac_code },
0410         { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
0411     };
0412 
0413     return regmap_multi_reg_write(st->regmap, reg_seq, 2);
0414 }
0415 
0416 static int ad74413r_set_channel_function(struct ad74413r_state *st,
0417                      unsigned int channel, u8 func)
0418 {
0419     return regmap_update_bits(st->regmap,
0420                   AD74413R_REG_CH_FUNC_SETUP_X(channel),
0421                   AD74413R_CH_FUNC_SETUP_MASK, func);
0422 }
0423 
0424 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
0425                      unsigned int status)
0426 {
0427     int ret;
0428 
0429     /*
0430      * These bits do not clear when a conversion completes.
0431      * To enable a subsequent conversion, repeat the write.
0432      */
0433     ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
0434                 AD74413R_CONV_SEQ_MASK,
0435                 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
0436     if (ret)
0437         return ret;
0438 
0439     /*
0440      * Wait 100us before starting conversions.
0441      */
0442     usleep_range(100, 120);
0443 
0444     return 0;
0445 }
0446 
0447 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
0448                        unsigned int channel,
0449                        bool status)
0450 {
0451     return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
0452                   AD74413R_CH_EN_MASK(channel),
0453                   status ? AD74413R_CH_EN_MASK(channel) : 0);
0454 }
0455 
0456 static int ad74413r_get_adc_range(struct ad74413r_state *st,
0457                   unsigned int channel,
0458                   unsigned int *val)
0459 {
0460     int ret;
0461 
0462     ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
0463     if (ret)
0464         return ret;
0465 
0466     *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
0467 
0468     return 0;
0469 }
0470 
0471 static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
0472                       unsigned int channel,
0473                       unsigned int *val)
0474 {
0475     int ret;
0476 
0477     ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
0478     if (ret)
0479         return ret;
0480 
0481     *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
0482 
0483     return 0;
0484 }
0485 
0486 static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
0487                       unsigned int channel,
0488                       unsigned int val)
0489 {
0490     return regmap_update_bits(st->regmap,
0491                   AD74413R_REG_ADC_CONFIG_X(channel),
0492                   AD74413R_ADC_CONFIG_REJECTION_MASK,
0493                   FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
0494                          val));
0495 }
0496 
0497 static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
0498                       unsigned int rej, int *val)
0499 {
0500     switch (rej) {
0501     case AD74413R_ADC_REJECTION_50_60:
0502         *val = 20;
0503         return 0;
0504     case AD74413R_ADC_REJECTION_NONE:
0505         *val = 4800;
0506         return 0;
0507     case AD74413R_ADC_REJECTION_50_60_HART:
0508         *val = 10;
0509         return 0;
0510     case AD74413R_ADC_REJECTION_HART:
0511         *val = 1200;
0512         return 0;
0513     default:
0514         dev_err(st->dev, "ADC rejection invalid\n");
0515         return -EINVAL;
0516     }
0517 }
0518 
0519 static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
0520                       int rate, unsigned int *val)
0521 {
0522     switch (rate) {
0523     case 20:
0524         *val = AD74413R_ADC_REJECTION_50_60;
0525         return 0;
0526     case 4800:
0527         *val = AD74413R_ADC_REJECTION_NONE;
0528         return 0;
0529     case 10:
0530         *val = AD74413R_ADC_REJECTION_50_60_HART;
0531         return 0;
0532     case 1200:
0533         *val = AD74413R_ADC_REJECTION_HART;
0534         return 0;
0535     default:
0536         dev_err(st->dev, "ADC rate invalid\n");
0537         return -EINVAL;
0538     }
0539 }
0540 
0541 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
0542                        unsigned int range, int *val)
0543 {
0544     switch (range) {
0545     case AD74413R_ADC_RANGE_10V:
0546         *val = 10000;
0547         return 0;
0548     case AD74413R_ADC_RANGE_2P5V_EXT_POW:
0549     case AD74413R_ADC_RANGE_2P5V_INT_POW:
0550         *val = 2500;
0551         return 0;
0552     case AD74413R_ADC_RANGE_5V_BI_DIR:
0553         *val = 5000;
0554         return 0;
0555     default:
0556         dev_err(st->dev, "ADC range invalid\n");
0557         return -EINVAL;
0558     }
0559 }
0560 
0561 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
0562                         unsigned int range, int *val)
0563 {
0564     switch (range) {
0565     case AD74413R_ADC_RANGE_10V:
0566     case AD74413R_ADC_RANGE_2P5V_EXT_POW:
0567         *val = 0;
0568         return 0;
0569     case AD74413R_ADC_RANGE_2P5V_INT_POW:
0570     case AD74413R_ADC_RANGE_5V_BI_DIR:
0571         *val = -2500;
0572         return 0;
0573     default:
0574         dev_err(st->dev, "ADC range invalid\n");
0575         return -EINVAL;
0576     }
0577 }
0578 
0579 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
0580                         unsigned int range, int *val)
0581 {
0582     switch (range) {
0583     case AD74413R_ADC_RANGE_10V:
0584     case AD74413R_ADC_RANGE_2P5V_EXT_POW:
0585         *val = 0;
0586         return 0;
0587     case AD74413R_ADC_RANGE_2P5V_INT_POW:
0588         *val = -((int)AD74413R_ADC_RESULT_MAX);
0589         return 0;
0590     case AD74413R_ADC_RANGE_5V_BI_DIR:
0591         *val = -((int)AD74413R_ADC_RESULT_MAX / 2);
0592         return 0;
0593     default:
0594         dev_err(st->dev, "ADC range invalid\n");
0595         return -EINVAL;
0596     }
0597 }
0598 
0599 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
0600                          int *val, int *val2)
0601 {
0602     *val = AD74413R_DAC_VOLTAGE_MAX;
0603     *val2 = AD74413R_DAC_CODE_MAX;
0604 
0605     return IIO_VAL_FRACTIONAL;
0606 }
0607 
0608 static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
0609                          int *val, int *val2)
0610 {
0611     *val = regulator_get_voltage(st->refin_reg);
0612     *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
0613 
0614     return IIO_VAL_FRACTIONAL;
0615 }
0616 
0617 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
0618                         unsigned int channel,
0619                         int *val, int *val2)
0620 {
0621     unsigned int range;
0622     int ret;
0623 
0624     ret = ad74413r_get_adc_range(st, channel, &range);
0625     if (ret)
0626         return ret;
0627 
0628     ret = ad74413r_range_to_voltage_range(st, range, val);
0629     if (ret)
0630         return ret;
0631 
0632     *val2 = AD74413R_ADC_RESULT_MAX;
0633 
0634     return IIO_VAL_FRACTIONAL;
0635 }
0636 
0637 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
0638                          unsigned int channel, int *val)
0639 {
0640     unsigned int range;
0641     int ret;
0642 
0643     ret = ad74413r_get_adc_range(st, channel, &range);
0644     if (ret)
0645         return ret;
0646 
0647     ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
0648     if (ret)
0649         return ret;
0650 
0651     return IIO_VAL_INT;
0652 }
0653 
0654 static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
0655                         unsigned int channel, int *val,
0656                         int *val2)
0657 {
0658     unsigned int range;
0659     int ret;
0660 
0661     ret = ad74413r_get_adc_range(st, channel, &range);
0662     if (ret)
0663         return ret;
0664 
0665     ret = ad74413r_range_to_voltage_range(st, range, val);
0666     if (ret)
0667         return ret;
0668 
0669     *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
0670 
0671     return IIO_VAL_FRACTIONAL;
0672 }
0673 
0674 static int ad74413_get_input_current_offset(struct ad74413r_state *st,
0675                         unsigned int channel, int *val)
0676 {
0677     unsigned int range;
0678     int voltage_range;
0679     int voltage_offset;
0680     int ret;
0681 
0682     ret = ad74413r_get_adc_range(st, channel, &range);
0683     if (ret)
0684         return ret;
0685 
0686     ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
0687     if (ret)
0688         return ret;
0689 
0690     ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
0691     if (ret)
0692         return ret;
0693 
0694     *val = voltage_offset * AD74413R_ADC_RESULT_MAX / voltage_range;
0695 
0696     return IIO_VAL_INT;
0697 }
0698 
0699 static int ad74413r_get_adc_rate(struct ad74413r_state *st,
0700                  unsigned int channel, int *val)
0701 {
0702     unsigned int rejection;
0703     int ret;
0704 
0705     ret = ad74413r_get_adc_rejection(st, channel, &rejection);
0706     if (ret)
0707         return ret;
0708 
0709     ret = ad74413r_rejection_to_rate(st, rejection, val);
0710     if (ret)
0711         return ret;
0712 
0713     return IIO_VAL_INT;
0714 }
0715 
0716 static int ad74413r_set_adc_rate(struct ad74413r_state *st,
0717                  unsigned int channel, int val)
0718 {
0719     unsigned int rejection;
0720     int ret;
0721 
0722     ret = ad74413r_rate_to_rejection(st, val, &rejection);
0723     if (ret)
0724         return ret;
0725 
0726     return ad74413r_set_adc_rejection(st, channel, rejection);
0727 }
0728 
0729 static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
0730 {
0731     struct iio_poll_func *pf = p;
0732     struct iio_dev *indio_dev = pf->indio_dev;
0733     struct ad74413r_state *st = iio_priv(indio_dev);
0734     u8 *rx_buf = st->adc_samples_buf.rx_buf;
0735     unsigned int i;
0736     int ret;
0737 
0738     ret = spi_sync(st->spi, &st->adc_samples_msg);
0739     if (ret)
0740         goto out;
0741 
0742     for (i = 0; i < st->adc_active_channels; i++)
0743         ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
0744 
0745     iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
0746                        iio_get_time_ns(indio_dev));
0747 
0748 out:
0749     iio_trigger_notify_done(indio_dev->trig);
0750 
0751     return IRQ_HANDLED;
0752 }
0753 
0754 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
0755 {
0756     struct iio_dev *indio_dev = data;
0757     struct ad74413r_state *st = iio_priv(indio_dev);
0758 
0759     if (iio_buffer_enabled(indio_dev))
0760         iio_trigger_poll(st->trig);
0761     else
0762         complete(&st->adc_data_completion);
0763 
0764     return IRQ_HANDLED;
0765 }
0766 
0767 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
0768                        unsigned int channel, int *val)
0769 {
0770     unsigned int uval;
0771     int ret;
0772 
0773     reinit_completion(&st->adc_data_completion);
0774 
0775     ret = ad74413r_set_adc_channel_enable(st, channel, true);
0776     if (ret)
0777         return ret;
0778 
0779     ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
0780     if (ret)
0781         return ret;
0782 
0783     ret = wait_for_completion_timeout(&st->adc_data_completion,
0784                       msecs_to_jiffies(1000));
0785     if (!ret) {
0786         ret = -ETIMEDOUT;
0787         return ret;
0788     }
0789 
0790     ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
0791               &uval);
0792     if (ret)
0793         return ret;
0794 
0795     ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
0796     if (ret)
0797         return ret;
0798 
0799     ret = ad74413r_set_adc_channel_enable(st, channel, false);
0800     if (ret)
0801         return ret;
0802 
0803     *val = uval;
0804 
0805     return IIO_VAL_INT;
0806 }
0807 
0808 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
0809                       unsigned int channel, int *val)
0810 {
0811     struct ad74413r_state *st = iio_priv(indio_dev);
0812     int ret;
0813 
0814     ret = iio_device_claim_direct_mode(indio_dev);
0815     if (ret)
0816         return ret;
0817 
0818     mutex_lock(&st->lock);
0819     ret = _ad74413r_get_single_adc_result(st, channel, val);
0820     mutex_unlock(&st->lock);
0821 
0822     iio_device_release_direct_mode(indio_dev);
0823 
0824     return ret;
0825 }
0826 
0827 static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
0828 {
0829     if (adc_result == AD74413R_ADC_RESULT_MAX)
0830         adc_result = AD74413R_ADC_RESULT_MAX - 1;
0831 
0832     *val = DIV_ROUND_CLOSEST(adc_result * 2100,
0833                  AD74413R_ADC_RESULT_MAX - adc_result);
0834 }
0835 
0836 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
0837                      const unsigned long *active_scan_mask)
0838 {
0839     struct ad74413r_state *st = iio_priv(indio_dev);
0840     struct spi_transfer *xfer = st->adc_samples_xfer;
0841     u8 *rx_buf = st->adc_samples_buf.rx_buf;
0842     u8 *tx_buf = st->adc_samples_tx_buf;
0843     unsigned int channel;
0844     int ret = -EINVAL;
0845 
0846     mutex_lock(&st->lock);
0847 
0848     spi_message_init(&st->adc_samples_msg);
0849     st->adc_active_channels = 0;
0850 
0851     for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
0852         ret = ad74413r_set_adc_channel_enable(st, channel, false);
0853         if (ret)
0854             goto out;
0855     }
0856 
0857     if (*active_scan_mask == 0)
0858         goto out;
0859 
0860     /*
0861      * The read select register is used to select which register's value
0862      * will be sent by the slave on the next SPI frame.
0863      *
0864      * Create an SPI message that, on each step, writes to the read select
0865      * register to select the ADC result of the next enabled channel, and
0866      * reads the ADC result of the previous enabled channel.
0867      *
0868      * Example:
0869      * W: [WCH1] [WCH2] [WCH2] [WCH3] [    ]
0870      * R: [    ] [RCH1] [RCH2] [RCH3] [RCH4]
0871      */
0872 
0873     for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
0874         ret = ad74413r_set_adc_channel_enable(st, channel, true);
0875         if (ret)
0876             goto out;
0877 
0878         st->adc_active_channels++;
0879 
0880         if (xfer == st->adc_samples_xfer)
0881             xfer->rx_buf = NULL;
0882         else
0883             xfer->rx_buf = rx_buf;
0884 
0885         xfer->tx_buf = tx_buf;
0886         xfer->len = AD74413R_FRAME_SIZE;
0887         xfer->cs_change = 1;
0888 
0889         ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
0890                       AD74413R_REG_ADC_RESULT_X(channel),
0891                       tx_buf);
0892 
0893         spi_message_add_tail(xfer, &st->adc_samples_msg);
0894 
0895         tx_buf += AD74413R_FRAME_SIZE;
0896         if (xfer != st->adc_samples_xfer)
0897             rx_buf += AD74413R_FRAME_SIZE;
0898         xfer++;
0899     }
0900 
0901     xfer->rx_buf = rx_buf;
0902     xfer->tx_buf = NULL;
0903     xfer->len = AD74413R_FRAME_SIZE;
0904     xfer->cs_change = 0;
0905 
0906     spi_message_add_tail(xfer, &st->adc_samples_msg);
0907 
0908 out:
0909     mutex_unlock(&st->lock);
0910 
0911     return ret;
0912 }
0913 
0914 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
0915 {
0916     struct ad74413r_state *st = iio_priv(indio_dev);
0917 
0918     return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
0919 }
0920 
0921 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
0922 {
0923     struct ad74413r_state *st = iio_priv(indio_dev);
0924 
0925     return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
0926 }
0927 
0928 static int ad74413r_read_raw(struct iio_dev *indio_dev,
0929                  struct iio_chan_spec const *chan,
0930                  int *val, int *val2, long info)
0931 {
0932     struct ad74413r_state *st = iio_priv(indio_dev);
0933 
0934     switch (info) {
0935     case IIO_CHAN_INFO_SCALE:
0936         switch (chan->type) {
0937         case IIO_VOLTAGE:
0938             if (chan->output)
0939                 return ad74413r_get_output_voltage_scale(st,
0940                     val, val2);
0941             else
0942                 return ad74413r_get_input_voltage_scale(st,
0943                     chan->channel, val, val2);
0944         case IIO_CURRENT:
0945             if (chan->output)
0946                 return ad74413r_get_output_current_scale(st,
0947                     val, val2);
0948             else
0949                 return ad74413r_get_input_current_scale(st,
0950                     chan->channel, val, val2);
0951         default:
0952             return -EINVAL;
0953         }
0954     case IIO_CHAN_INFO_OFFSET:
0955         switch (chan->type) {
0956         case IIO_VOLTAGE:
0957             return ad74413r_get_input_voltage_offset(st,
0958                 chan->channel, val);
0959         case IIO_CURRENT:
0960             return ad74413_get_input_current_offset(st,
0961                 chan->channel, val);
0962         default:
0963             return -EINVAL;
0964         }
0965     case IIO_CHAN_INFO_RAW:
0966         if (chan->output)
0967             return -EINVAL;
0968 
0969         return ad74413r_get_single_adc_result(indio_dev, chan->channel,
0970                               val);
0971     case IIO_CHAN_INFO_PROCESSED: {
0972         int ret;
0973 
0974         ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
0975                              val);
0976         if (ret)
0977             return ret;
0978 
0979         ad74413r_adc_to_resistance_result(*val, val);
0980 
0981         return ret;
0982     }
0983     case IIO_CHAN_INFO_SAMP_FREQ:
0984         return ad74413r_get_adc_rate(st, chan->channel, val);
0985     default:
0986         return -EINVAL;
0987     }
0988 }
0989 
0990 static int ad74413r_write_raw(struct iio_dev *indio_dev,
0991                   struct iio_chan_spec const *chan,
0992                   int val, int val2, long info)
0993 {
0994     struct ad74413r_state *st = iio_priv(indio_dev);
0995 
0996     switch (info) {
0997     case IIO_CHAN_INFO_RAW:
0998         if (!chan->output)
0999             return -EINVAL;
1000 
1001         if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1002             dev_err(st->dev, "Invalid DAC code\n");
1003             return -EINVAL;
1004         }
1005 
1006         return ad74413r_set_channel_dac_code(st, chan->channel, val);
1007     case IIO_CHAN_INFO_SAMP_FREQ:
1008         return ad74413r_set_adc_rate(st, chan->channel, val);
1009     default:
1010         return -EINVAL;
1011     }
1012 }
1013 
1014 static int ad74413r_read_avail(struct iio_dev *indio_dev,
1015                    struct iio_chan_spec const *chan,
1016                    const int **vals, int *type, int *length,
1017                    long info)
1018 {
1019     struct ad74413r_state *st = iio_priv(indio_dev);
1020 
1021     switch (info) {
1022     case IIO_CHAN_INFO_SAMP_FREQ:
1023         if (st->chip_info->hart_support) {
1024             *vals = ad74413r_adc_sampling_rates_hart;
1025             *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1026         } else {
1027             *vals = ad74413r_adc_sampling_rates;
1028             *length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1029         }
1030         *type = IIO_VAL_INT;
1031         return IIO_AVAIL_LIST;
1032     default:
1033         return -EINVAL;
1034     }
1035 }
1036 
1037 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1038     .postenable = &ad74413r_buffer_postenable,
1039     .predisable = &ad74413r_buffer_predisable,
1040 };
1041 
1042 static const struct iio_trigger_ops ad74413r_trigger_ops = {
1043     .validate_device = iio_trigger_validate_own_device,
1044 };
1045 
1046 static const struct iio_info ad74413r_info = {
1047     .read_raw = &ad74413r_read_raw,
1048     .write_raw = &ad74413r_write_raw,
1049     .read_avail = &ad74413r_read_avail,
1050     .update_scan_mode = &ad74413r_update_scan_mode,
1051 };
1052 
1053 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate)        \
1054     {                               \
1055         .type = (_type),                    \
1056         .indexed = 1,                       \
1057         .output = 1,                        \
1058         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)        \
1059                       | (extra_mask_separate),      \
1060     }
1061 
1062 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate)        \
1063     {                               \
1064         .type = (_type),                    \
1065         .indexed = 1,                       \
1066         .output = 0,                        \
1067         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)        \
1068                       | BIT(IIO_CHAN_INFO_SAMP_FREQ)    \
1069                       | (extra_mask_separate),      \
1070         .info_mask_separate_available =             \
1071                     BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
1072         .scan_type = {                      \
1073             .sign = 'u',                    \
1074             .realbits = 16,                 \
1075             .storagebits = 32,              \
1076             .shift = 8,                 \
1077             .endianness = IIO_BE,               \
1078         },                          \
1079     }
1080 
1081 #define AD74413R_ADC_VOLTAGE_CHANNEL                    \
1082     AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)  \
1083                  | BIT(IIO_CHAN_INFO_OFFSET))
1084 
1085 #define AD74413R_ADC_CURRENT_CHANNEL                    \
1086     AD74413R_ADC_CHANNEL(IIO_CURRENT,  BIT(IIO_CHAN_INFO_SCALE) \
1087                  | BIT(IIO_CHAN_INFO_OFFSET))
1088 
1089 static struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1090     AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1091     AD74413R_ADC_CURRENT_CHANNEL,
1092 };
1093 
1094 static struct iio_chan_spec ad74413r_current_output_channels[] = {
1095     AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1096     AD74413R_ADC_VOLTAGE_CHANNEL,
1097 };
1098 
1099 static struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1100     AD74413R_ADC_VOLTAGE_CHANNEL,
1101 };
1102 
1103 static struct iio_chan_spec ad74413r_current_input_channels[] = {
1104     AD74413R_ADC_CURRENT_CHANNEL,
1105 };
1106 
1107 static struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1108     AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1109 };
1110 
1111 static struct iio_chan_spec ad74413r_digital_input_channels[] = {
1112     AD74413R_ADC_VOLTAGE_CHANNEL,
1113 };
1114 
1115 #define _AD74413R_CHANNELS(_channels)           \
1116     {                       \
1117         .channels = _channels,          \
1118         .num_channels = ARRAY_SIZE(_channels),  \
1119     }
1120 
1121 #define AD74413R_CHANNELS(name) \
1122     _AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1123 
1124 static const struct ad74413r_channels ad74413r_channels_map[] = {
1125     [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1126     [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1127     [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1128     [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1129     [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1130     [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input),
1131     [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1132     [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1133     [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1134     [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1135     [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1136 };
1137 
1138 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1139                      struct fwnode_handle *channel_node)
1140 {
1141     struct ad74413r_state *st = iio_priv(indio_dev);
1142     struct ad74413r_channel_config *config;
1143     u32 index;
1144     int ret;
1145 
1146     ret = fwnode_property_read_u32(channel_node, "reg", &index);
1147     if (ret) {
1148         dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1149         return ret;
1150     }
1151 
1152     if (index >= AD74413R_CHANNEL_MAX) {
1153         dev_err(st->dev, "Channel index %u is too large\n", index);
1154         return -EINVAL;
1155     }
1156 
1157     config = &st->channel_configs[index];
1158     if (config->initialized) {
1159         dev_err(st->dev, "Channel %u already initialized\n", index);
1160         return -EINVAL;
1161     }
1162 
1163     config->func = CH_FUNC_HIGH_IMPEDANCE;
1164     fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1165 
1166     if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1167         dev_err(st->dev, "Invalid channel function %u\n", config->func);
1168         return -EINVAL;
1169     }
1170 
1171     if (!st->chip_info->hart_support &&
1172         (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1173          config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1174         dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1175         return -EINVAL;
1176     }
1177 
1178     if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1179         config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1180         st->num_comparator_gpios++;
1181 
1182     config->gpo_comparator = fwnode_property_read_bool(channel_node,
1183         "adi,gpo-comparator");
1184 
1185     if (!config->gpo_comparator)
1186         st->num_gpo_gpios++;
1187 
1188     indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1189 
1190     config->initialized = true;
1191 
1192     return 0;
1193 }
1194 
1195 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1196 {
1197     struct ad74413r_state *st = iio_priv(indio_dev);
1198     struct fwnode_handle *channel_node = NULL;
1199     int ret;
1200 
1201     fwnode_for_each_available_child_node(dev_fwnode(st->dev), channel_node) {
1202         ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1203         if (ret)
1204             goto put_channel_node;
1205     }
1206 
1207     return 0;
1208 
1209 put_channel_node:
1210     fwnode_handle_put(channel_node);
1211 
1212     return ret;
1213 }
1214 
1215 static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1216 {
1217     struct ad74413r_state *st = iio_priv(indio_dev);
1218     struct ad74413r_channel_config *config;
1219     struct iio_chan_spec *channels, *chans;
1220     unsigned int i, num_chans, chan_i;
1221     int ret;
1222 
1223     channels = devm_kcalloc(st->dev, sizeof(*channels),
1224                 indio_dev->num_channels, GFP_KERNEL);
1225     if (!channels)
1226         return -ENOMEM;
1227 
1228     indio_dev->channels = channels;
1229 
1230     for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1231         config = &st->channel_configs[i];
1232         chans = ad74413r_channels_map[config->func].channels;
1233         num_chans = ad74413r_channels_map[config->func].num_channels;
1234 
1235         memcpy(channels, chans, num_chans * sizeof(*chans));
1236 
1237         for (chan_i = 0; chan_i < num_chans; chan_i++) {
1238             struct iio_chan_spec *chan = &channels[chan_i];
1239 
1240             chan->channel = i;
1241             if (chan->output)
1242                 chan->scan_index = -1;
1243             else
1244                 chan->scan_index = i;
1245         }
1246 
1247         ret = ad74413r_set_channel_function(st, i, config->func);
1248         if (ret)
1249             return ret;
1250 
1251         channels += num_chans;
1252     }
1253 
1254     return 0;
1255 }
1256 
1257 static int ad74413r_setup_gpios(struct ad74413r_state *st)
1258 {
1259     struct ad74413r_channel_config *config;
1260     unsigned int comp_gpio_i = 0;
1261     unsigned int gpo_gpio_i = 0;
1262     unsigned int i;
1263     u8 gpo_config;
1264     int ret;
1265 
1266     for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1267         config = &st->channel_configs[i];
1268 
1269         if (config->gpo_comparator) {
1270             gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1271         } else {
1272             gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1273             st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1274         }
1275 
1276         if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1277             config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1278             st->comp_gpio_offsets[comp_gpio_i++] = i;
1279 
1280         ret = ad74413r_set_gpo_config(st, i, gpo_config);
1281         if (ret)
1282             return ret;
1283     }
1284 
1285     return 0;
1286 }
1287 
1288 static void ad74413r_regulator_disable(void *regulator)
1289 {
1290     regulator_disable(regulator);
1291 }
1292 
1293 static int ad74413r_probe(struct spi_device *spi)
1294 {
1295     struct ad74413r_state *st;
1296     struct iio_dev *indio_dev;
1297     int ret;
1298 
1299     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1300     if (!indio_dev)
1301         return -ENOMEM;
1302 
1303     st = iio_priv(indio_dev);
1304 
1305     st->spi = spi;
1306     st->dev = &spi->dev;
1307     st->chip_info = device_get_match_data(&spi->dev);
1308     mutex_init(&st->lock);
1309     init_completion(&st->adc_data_completion);
1310 
1311     st->regmap = devm_regmap_init(st->dev, NULL, st,
1312                       &ad74413r_regmap_config);
1313     if (IS_ERR(st->regmap))
1314         return PTR_ERR(st->regmap);
1315 
1316     st->refin_reg = devm_regulator_get(st->dev, "refin");
1317     if (IS_ERR(st->refin_reg))
1318         return dev_err_probe(st->dev, PTR_ERR(st->refin_reg),
1319                      "Failed to get refin regulator\n");
1320 
1321     ret = regulator_enable(st->refin_reg);
1322     if (ret)
1323         return ret;
1324 
1325     ret = devm_add_action_or_reset(st->dev, ad74413r_regulator_disable,
1326                        st->refin_reg);
1327     if (ret)
1328         return ret;
1329 
1330     st->sense_resistor_ohms = 100000000;
1331     device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1332                  &st->sense_resistor_ohms);
1333     st->sense_resistor_ohms /= 1000000;
1334 
1335     st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1336                       st->chip_info->name, iio_device_id(indio_dev));
1337     if (!st->trig)
1338         return -ENOMEM;
1339 
1340     st->trig->ops = &ad74413r_trigger_ops;
1341     iio_trigger_set_drvdata(st->trig, st);
1342 
1343     ret = devm_iio_trigger_register(st->dev, st->trig);
1344     if (ret)
1345         return ret;
1346 
1347     indio_dev->name = st->chip_info->name;
1348     indio_dev->modes = INDIO_DIRECT_MODE;
1349     indio_dev->info = &ad74413r_info;
1350     indio_dev->trig = iio_trigger_get(st->trig);
1351 
1352     ret = ad74413r_reset(st);
1353     if (ret)
1354         return ret;
1355 
1356     ret = ad74413r_parse_channel_configs(indio_dev);
1357     if (ret)
1358         return ret;
1359 
1360     ret = ad74413r_setup_channels(indio_dev);
1361     if (ret)
1362         return ret;
1363 
1364     ret = ad74413r_setup_gpios(st);
1365     if (ret)
1366         return ret;
1367 
1368     if (st->num_gpo_gpios) {
1369         st->gpo_gpiochip.owner = THIS_MODULE;
1370         st->gpo_gpiochip.label = st->chip_info->name;
1371         st->gpo_gpiochip.base = -1;
1372         st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1373         st->gpo_gpiochip.parent = st->dev;
1374         st->gpo_gpiochip.can_sleep = true;
1375         st->gpo_gpiochip.set = ad74413r_gpio_set;
1376         st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1377         st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1378         st->gpo_gpiochip.get_direction =
1379             ad74413r_gpio_get_gpo_direction;
1380 
1381         ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1382         if (ret)
1383             return ret;
1384     }
1385 
1386     if (st->num_comparator_gpios) {
1387         st->comp_gpiochip.owner = THIS_MODULE;
1388         st->comp_gpiochip.label = st->chip_info->name;
1389         st->comp_gpiochip.base = -1;
1390         st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1391         st->comp_gpiochip.parent = st->dev;
1392         st->comp_gpiochip.can_sleep = true;
1393         st->comp_gpiochip.get = ad74413r_gpio_get;
1394         st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1395         st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1396         st->comp_gpiochip.get_direction =
1397             ad74413r_gpio_get_comp_direction;
1398 
1399         ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1400         if (ret)
1401             return ret;
1402     }
1403 
1404     ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1405     if (ret)
1406         return ret;
1407 
1408     ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1409                    0, st->chip_info->name, indio_dev);
1410     if (ret)
1411         return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1412 
1413     ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1414                           &iio_pollfunc_store_time,
1415                           &ad74413r_trigger_handler,
1416                           &ad74413r_buffer_ops);
1417     if (ret)
1418         return ret;
1419 
1420     return devm_iio_device_register(st->dev, indio_dev);
1421 }
1422 
1423 static int ad74413r_unregister_driver(struct spi_driver *spi)
1424 {
1425     spi_unregister_driver(spi);
1426 
1427     return 0;
1428 }
1429 
1430 static int __init ad74413r_register_driver(struct spi_driver *spi)
1431 {
1432     crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1433 
1434     return spi_register_driver(spi);
1435 }
1436 
1437 static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1438     .hart_support = false,
1439     .name = "ad74412r",
1440 };
1441 
1442 static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1443     .hart_support = true,
1444     .name = "ad74413r",
1445 };
1446 
1447 static const struct of_device_id ad74413r_dt_id[] = {
1448     {
1449         .compatible = "adi,ad74412r",
1450         .data = &ad74412r_chip_info_data,
1451     },
1452     {
1453         .compatible = "adi,ad74413r",
1454         .data = &ad74413r_chip_info_data,
1455     },
1456     {},
1457 };
1458 MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1459 
1460 static struct spi_driver ad74413r_driver = {
1461     .driver = {
1462            .name = "ad74413r",
1463            .of_match_table = ad74413r_dt_id,
1464     },
1465     .probe = ad74413r_probe,
1466 };
1467 
1468 module_driver(ad74413r_driver,
1469           ad74413r_register_driver,
1470           ad74413r_unregister_driver);
1471 
1472 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1473 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1474 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!