iio/adc/xilinx-xadc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Xilinx XADC driver
0004  *
0005  * Copyright 2013 Analog Devices Inc.
0006  *  Author: Lars-Peter Clausen <lars@metafoo.de>
0007  */
0008
0009 #ifndef __IIO_XILINX_XADC__
0010 #define __IIO_XILINX_XADC__
0011
0012 #include <linux/interrupt.h>
0013 #include <linux/mutex.h>
0014 #include <linux/spinlock.h>
0015
0016 struct iio_dev;
0017 struct clk;
0018 struct xadc_ops;
0019 struct platform_device;
0020
0021 void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
0022
0023 int xadc_read_event_config(struct iio_dev *indio_dev,
0024     const struct iio_chan_spec *chan, enum iio_event_type type,
0025     enum iio_event_direction dir);
0026 int xadc_write_event_config(struct iio_dev *indio_dev,
0027     const struct iio_chan_spec *chan, enum iio_event_type type,
0028     enum iio_event_direction dir, int state);
0029 int xadc_read_event_value(struct iio_dev *indio_dev,
0030     const struct iio_chan_spec *chan, enum iio_event_type type,
0031     enum iio_event_direction dir, enum iio_event_info info,
0032     int *val, int *val2);
0033 int xadc_write_event_value(struct iio_dev *indio_dev,
0034     const struct iio_chan_spec *chan, enum iio_event_type type,
0035     enum iio_event_direction dir, enum iio_event_info info,
0036     int val, int val2);
0037
0038 enum xadc_external_mux_mode {
0039     XADC_EXTERNAL_MUX_NONE,
0040     XADC_EXTERNAL_MUX_SINGLE,
0041     XADC_EXTERNAL_MUX_DUAL,
0042 };
0043
0044 struct xadc {
0045     void __iomem *base;
0046     struct clk *clk;
0047
0048     const struct xadc_ops *ops;
0049
0050     uint16_t threshold[16];
0051     uint16_t temp_hysteresis;
0052     unsigned int alarm_mask;
0053
0054     uint16_t *data;
0055
0056     struct iio_trigger *trigger;
0057     struct iio_trigger *convst_trigger;
0058     struct iio_trigger *samplerate_trigger;
0059
0060     enum xadc_external_mux_mode external_mux_mode;
0061
0062     unsigned int zynq_masked_alarm;
0063     unsigned int zynq_intmask;
0064     struct delayed_work zynq_unmask_work;
0065
0066     struct mutex mutex;
0067     spinlock_t lock;
0068
0069     struct completion completion;
0070 };
0071
0072 enum xadc_type {
0073     XADC_TYPE_S7, /* Series 7 */
0074     XADC_TYPE_US, /* UltraScale and UltraScale+ */
0075 };
0076
0077 struct xadc_ops {
0078     int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
0079     int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
0080     int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
0081             int irq);
0082     void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
0083     unsigned long (*get_dclk_rate)(struct xadc *xadc);
0084     irqreturn_t (*interrupt_handler)(int irq, void *devid);
0085
0086     unsigned int flags;
0087     enum xadc_type type;
0088 };
0089
0090 static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
0091     uint16_t *val)
0092 {
0093     lockdep_assert_held(&xadc->mutex);
0094     return xadc->ops->read(xadc, reg, val);
0095 }
0096
0097 static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
0098     uint16_t val)
0099 {
0100     lockdep_assert_held(&xadc->mutex);
0101     return xadc->ops->write(xadc, reg, val);
0102 }
0103
0104 static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
0105     uint16_t *val)
0106 {
0107     int ret;
0108
0109     mutex_lock(&xadc->mutex);
0110     ret = _xadc_read_adc_reg(xadc, reg, val);
0111     mutex_unlock(&xadc->mutex);
0112     return ret;
0113 }
0114
0115 static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
0116     uint16_t val)
0117 {
0118     int ret;
0119
0120     mutex_lock(&xadc->mutex);
0121     ret = _xadc_write_adc_reg(xadc, reg, val);
0122     mutex_unlock(&xadc->mutex);
0123     return ret;
0124 }
0125
0126 /* XADC hardmacro register definitions */
0127 #define XADC_REG_TEMP       0x00
0128 #define XADC_REG_VCCINT     0x01
0129 #define XADC_REG_VCCAUX     0x02
0130 #define XADC_REG_VPVN       0x03
0131 #define XADC_REG_VREFP      0x04
0132 #define XADC_REG_VREFN      0x05
0133 #define XADC_REG_VCCBRAM    0x06
0134
0135 #define XADC_REG_VCCPINT    0x0d
0136 #define XADC_REG_VCCPAUX    0x0e
0137 #define XADC_REG_VCCO_DDR   0x0f
0138 #define XADC_REG_VAUX(x)    (0x10 + (x))
0139
0140 #define XADC_REG_MAX_TEMP   0x20
0141 #define XADC_REG_MAX_VCCINT 0x21
0142 #define XADC_REG_MAX_VCCAUX 0x22
0143 #define XADC_REG_MAX_VCCBRAM    0x23
0144 #define XADC_REG_MIN_TEMP   0x24
0145 #define XADC_REG_MIN_VCCINT 0x25
0146 #define XADC_REG_MIN_VCCAUX 0x26
0147 #define XADC_REG_MIN_VCCBRAM    0x27
0148 #define XADC_REG_MAX_VCCPINT    0x28
0149 #define XADC_REG_MAX_VCCPAUX    0x29
0150 #define XADC_REG_MAX_VCCO_DDR   0x2a
0151 #define XADC_REG_MIN_VCCPINT    0x2c
0152 #define XADC_REG_MIN_VCCPAUX    0x2d
0153 #define XADC_REG_MIN_VCCO_DDR   0x2e
0154
0155 #define XADC_REG_CONF0      0x40
0156 #define XADC_REG_CONF1      0x41
0157 #define XADC_REG_CONF2      0x42
0158 #define XADC_REG_SEQ(x)     (0x48 + (x))
0159 #define XADC_REG_INPUT_MODE(x)  (0x4c + (x))
0160 #define XADC_REG_THRESHOLD(x)   (0x50 + (x))
0161
0162 #define XADC_REG_FLAG       0x3f
0163
0164 #define XADC_CONF0_EC           BIT(9)
0165 #define XADC_CONF0_ACQ          BIT(8)
0166 #define XADC_CONF0_MUX          BIT(11)
0167 #define XADC_CONF0_CHAN(x)      (x)
0168
0169 #define XADC_CONF1_SEQ_MASK     (0xf << 12)
0170 #define XADC_CONF1_SEQ_DEFAULT      (0 << 12)
0171 #define XADC_CONF1_SEQ_SINGLE_PASS  (1 << 12)
0172 #define XADC_CONF1_SEQ_CONTINUOUS   (2 << 12)
0173 #define XADC_CONF1_SEQ_SINGLE_CHANNEL   (3 << 12)
0174 #define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12)
0175 #define XADC_CONF1_SEQ_INDEPENDENT  (8 << 12)
0176 #define XADC_CONF1_ALARM_MASK       0x0f0f
0177
0178 #define XADC_CONF2_DIV_MASK 0xff00
0179 #define XADC_CONF2_DIV_OFFSET   8
0180
0181 #define XADC_CONF2_PD_MASK  (0x3 << 4)
0182 #define XADC_CONF2_PD_NONE  (0x0 << 4)
0183 #define XADC_CONF2_PD_ADC_B (0x2 << 4)
0184 #define XADC_CONF2_PD_BOTH  (0x3 << 4)
0185
0186 #define XADC_ALARM_TEMP_MASK        BIT(0)
0187 #define XADC_ALARM_VCCINT_MASK      BIT(1)
0188 #define XADC_ALARM_VCCAUX_MASK      BIT(2)
0189 #define XADC_ALARM_OT_MASK      BIT(3)
0190 #define XADC_ALARM_VCCBRAM_MASK     BIT(4)
0191 #define XADC_ALARM_VCCPINT_MASK     BIT(5)
0192 #define XADC_ALARM_VCCPAUX_MASK     BIT(6)
0193 #define XADC_ALARM_VCCODDR_MASK     BIT(7)
0194
0195 #define XADC_THRESHOLD_TEMP_MAX     0x0
0196 #define XADC_THRESHOLD_VCCINT_MAX   0x1
0197 #define XADC_THRESHOLD_VCCAUX_MAX   0x2
0198 #define XADC_THRESHOLD_OT_MAX       0x3
0199 #define XADC_THRESHOLD_TEMP_MIN     0x4
0200 #define XADC_THRESHOLD_VCCINT_MIN   0x5
0201 #define XADC_THRESHOLD_VCCAUX_MIN   0x6
0202 #define XADC_THRESHOLD_OT_MIN       0x7
0203 #define XADC_THRESHOLD_VCCBRAM_MAX  0x8
0204 #define XADC_THRESHOLD_VCCPINT_MAX  0x9
0205 #define XADC_THRESHOLD_VCCPAUX_MAX  0xa
0206 #define XADC_THRESHOLD_VCCODDR_MAX  0xb
0207 #define XADC_THRESHOLD_VCCBRAM_MIN  0xc
0208 #define XADC_THRESHOLD_VCCPINT_MIN  0xd
0209 #define XADC_THRESHOLD_VCCPAUX_MIN  0xe
0210 #define XADC_THRESHOLD_VCCODDR_MIN  0xf
0211
0212 #endif