iio/adc/xilinx-xadc-events.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Xilinx XADC driver
0004  *
0005  * Copyright 2013 Analog Devices Inc.
0006  *  Author: Lars-Peter Clausen <lars@metafoo.de>
0007  */
0008
0009 #include <linux/iio/events.h>
0010 #include <linux/iio/iio.h>
0011 #include <linux/kernel.h>
0012
0013 #include "xilinx-xadc.h"
0014
0015 static const struct iio_chan_spec *xadc_event_to_channel(
0016     struct iio_dev *indio_dev, unsigned int event)
0017 {
0018     switch (event) {
0019     case XADC_THRESHOLD_OT_MAX:
0020     case XADC_THRESHOLD_TEMP_MAX:
0021         return &indio_dev->channels[0];
0022     case XADC_THRESHOLD_VCCINT_MAX:
0023     case XADC_THRESHOLD_VCCAUX_MAX:
0024         return &indio_dev->channels[event];
0025     default:
0026         return &indio_dev->channels[event-1];
0027     }
0028 }
0029
0030 static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
0031 {
0032     const struct iio_chan_spec *chan;
0033
0034     /* Temperature threshold error, we don't handle this yet */
0035     if (event == 0)
0036         return;
0037
0038     chan = xadc_event_to_channel(indio_dev, event);
0039
0040     if (chan->type == IIO_TEMP) {
0041         /*
0042          * The temperature channel only supports over-temperature
0043          * events.
0044          */
0045         iio_push_event(indio_dev,
0046             IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
0047                 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
0048             iio_get_time_ns(indio_dev));
0049     } else {
0050         /*
0051          * For other channels we don't know whether it is a upper or
0052          * lower threshold event. Userspace will have to check the
0053          * channel value if it wants to know.
0054          */
0055         iio_push_event(indio_dev,
0056             IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
0057                 IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER),
0058             iio_get_time_ns(indio_dev));
0059     }
0060 }
0061
0062 void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events)
0063 {
0064     unsigned int i;
0065
0066     for_each_set_bit(i, &events, 8)
0067         xadc_handle_event(indio_dev, i);
0068 }
0069
0070 static unsigned int xadc_get_threshold_offset(const struct iio_chan_spec *chan,
0071     enum iio_event_direction dir)
0072 {
0073     unsigned int offset;
0074
0075     if (chan->type == IIO_TEMP) {
0076         offset = XADC_THRESHOLD_OT_MAX;
0077     } else {
0078         if (chan->channel < 2)
0079             offset = chan->channel + 1;
0080         else
0081             offset = chan->channel + 6;
0082     }
0083
0084     if (dir == IIO_EV_DIR_FALLING)
0085         offset += 4;
0086
0087     return offset;
0088 }
0089
0090 static unsigned int xadc_get_alarm_mask(const struct iio_chan_spec *chan)
0091 {
0092     if (chan->type == IIO_TEMP)
0093         return XADC_ALARM_OT_MASK;
0094     switch (chan->channel) {
0095     case 0:
0096         return XADC_ALARM_VCCINT_MASK;
0097     case 1:
0098         return XADC_ALARM_VCCAUX_MASK;
0099     case 2:
0100         return XADC_ALARM_VCCBRAM_MASK;
0101     case 3:
0102         return XADC_ALARM_VCCPINT_MASK;
0103     case 4:
0104         return XADC_ALARM_VCCPAUX_MASK;
0105     case 5:
0106         return XADC_ALARM_VCCODDR_MASK;
0107     default:
0108         /* We will never get here */
0109         return 0;
0110     }
0111 }
0112
0113 int xadc_read_event_config(struct iio_dev *indio_dev,
0114     const struct iio_chan_spec *chan, enum iio_event_type type,
0115     enum iio_event_direction dir)
0116 {
0117     struct xadc *xadc = iio_priv(indio_dev);
0118
0119     return (bool)(xadc->alarm_mask & xadc_get_alarm_mask(chan));
0120 }
0121
0122 int xadc_write_event_config(struct iio_dev *indio_dev,
0123     const struct iio_chan_spec *chan, enum iio_event_type type,
0124     enum iio_event_direction dir, int state)
0125 {
0126     unsigned int alarm = xadc_get_alarm_mask(chan);
0127     struct xadc *xadc = iio_priv(indio_dev);
0128     uint16_t cfg, old_cfg;
0129     int ret;
0130
0131     mutex_lock(&xadc->mutex);
0132
0133     if (state)
0134         xadc->alarm_mask |= alarm;
0135     else
0136         xadc->alarm_mask &= ~alarm;
0137
0138     xadc->ops->update_alarm(xadc, xadc->alarm_mask);
0139
0140     ret = _xadc_read_adc_reg(xadc, XADC_REG_CONF1, &cfg);
0141     if (ret)
0142         goto err_out;
0143
0144     old_cfg = cfg;
0145     cfg |= XADC_CONF1_ALARM_MASK;
0146     cfg &= ~((xadc->alarm_mask & 0xf0) << 4); /* bram, pint, paux, ddr */
0147     cfg &= ~((xadc->alarm_mask & 0x08) >> 3); /* ot */
0148     cfg &= ~((xadc->alarm_mask & 0x07) << 1); /* temp, vccint, vccaux */
0149     if (old_cfg != cfg)
0150         ret = _xadc_write_adc_reg(xadc, XADC_REG_CONF1, cfg);
0151
0152 err_out:
0153     mutex_unlock(&xadc->mutex);
0154
0155     return ret;
0156 }
0157
0158 int xadc_read_event_value(struct iio_dev *indio_dev,
0159     const struct iio_chan_spec *chan, enum iio_event_type type,
0160     enum iio_event_direction dir, enum iio_event_info info,
0161     int *val, int *val2)
0162 {
0163     unsigned int offset = xadc_get_threshold_offset(chan, dir);
0164     struct xadc *xadc = iio_priv(indio_dev);
0165
0166     switch (info) {
0167     case IIO_EV_INFO_VALUE:
0168         *val = xadc->threshold[offset];
0169         break;
0170     case IIO_EV_INFO_HYSTERESIS:
0171         *val = xadc->temp_hysteresis;
0172         break;
0173     default:
0174         return -EINVAL;
0175     }
0176
0177     /* MSB aligned */
0178     *val >>= 16 - chan->scan_type.realbits;
0179
0180     return IIO_VAL_INT;
0181 }
0182
0183 int xadc_write_event_value(struct iio_dev *indio_dev,
0184     const struct iio_chan_spec *chan, enum iio_event_type type,
0185     enum iio_event_direction dir, enum iio_event_info info,
0186     int val, int val2)
0187 {
0188     unsigned int offset = xadc_get_threshold_offset(chan, dir);
0189     struct xadc *xadc = iio_priv(indio_dev);
0190     int ret = 0;
0191
0192     /* MSB aligned */
0193     val <<= 16 - chan->scan_type.realbits;
0194
0195     if (val < 0 || val > 0xffff)
0196         return -EINVAL;
0197
0198     mutex_lock(&xadc->mutex);
0199
0200     switch (info) {
0201     case IIO_EV_INFO_VALUE:
0202         xadc->threshold[offset] = val;
0203         break;
0204     case IIO_EV_INFO_HYSTERESIS:
0205         xadc->temp_hysteresis = val;
0206         break;
0207     default:
0208         mutex_unlock(&xadc->mutex);
0209         return -EINVAL;
0210     }
0211
0212     if (chan->type == IIO_TEMP) {
0213         /*
0214          * According to the datasheet we need to set the lower 4 bits to
0215          * 0x3, otherwise 125 degree celsius will be used as the
0216          * threshold.
0217          */
0218         val |= 0x3;
0219
0220         /*
0221          * Since we store the hysteresis as relative (to the threshold)
0222          * value, but the hardware expects an absolute value we need to
0223          * recalcualte this value whenever the hysteresis or the
0224          * threshold changes.
0225          */
0226         if (xadc->threshold[offset] < xadc->temp_hysteresis)
0227             xadc->threshold[offset + 4] = 0;
0228         else
0229             xadc->threshold[offset + 4] = xadc->threshold[offset] -
0230                     xadc->temp_hysteresis;
0231         ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset + 4),
0232             xadc->threshold[offset + 4]);
0233         if (ret)
0234             goto out_unlock;
0235     }
0236
0237     if (info == IIO_EV_INFO_VALUE)
0238         ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset), val);
0239
0240 out_unlock:
0241     mutex_unlock(&xadc->mutex);
0242
0243     return ret;
0244 }