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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Xilinx XADC driver
0004  *
0005  * Copyright 2013-2014 Analog Devices Inc.
0006  *  Author: Lars-Peter Clausen <lars@metafoo.de>
0007  *
0008  * Documentation for the parts can be found at:
0009  *  - XADC hardmacro: Xilinx UG480
0010  *  - ZYNQ XADC interface: Xilinx UG585
0011  *  - AXI XADC interface: Xilinx PG019
0012  */
0013 
0014 #include <linux/clk.h>
0015 #include <linux/device.h>
0016 #include <linux/err.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/kernel.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/module.h>
0022 #include <linux/overflow.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/property.h>
0025 #include <linux/slab.h>
0026 #include <linux/sysfs.h>
0027 
0028 #include <linux/iio/buffer.h>
0029 #include <linux/iio/events.h>
0030 #include <linux/iio/iio.h>
0031 #include <linux/iio/sysfs.h>
0032 #include <linux/iio/trigger.h>
0033 #include <linux/iio/trigger_consumer.h>
0034 #include <linux/iio/triggered_buffer.h>
0035 
0036 #include "xilinx-xadc.h"
0037 
0038 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
0039 
0040 /* ZYNQ register definitions */
0041 #define XADC_ZYNQ_REG_CFG   0x00
0042 #define XADC_ZYNQ_REG_INTSTS    0x04
0043 #define XADC_ZYNQ_REG_INTMSK    0x08
0044 #define XADC_ZYNQ_REG_STATUS    0x0c
0045 #define XADC_ZYNQ_REG_CFIFO 0x10
0046 #define XADC_ZYNQ_REG_DFIFO 0x14
0047 #define XADC_ZYNQ_REG_CTL       0x18
0048 
0049 #define XADC_ZYNQ_CFG_ENABLE        BIT(31)
0050 #define XADC_ZYNQ_CFG_CFIFOTH_MASK  (0xf << 20)
0051 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET    20
0052 #define XADC_ZYNQ_CFG_DFIFOTH_MASK  (0xf << 16)
0053 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET    16
0054 #define XADC_ZYNQ_CFG_WEDGE     BIT(13)
0055 #define XADC_ZYNQ_CFG_REDGE     BIT(12)
0056 #define XADC_ZYNQ_CFG_TCKRATE_MASK  (0x3 << 8)
0057 #define XADC_ZYNQ_CFG_TCKRATE_DIV2  (0x0 << 8)
0058 #define XADC_ZYNQ_CFG_TCKRATE_DIV4  (0x1 << 8)
0059 #define XADC_ZYNQ_CFG_TCKRATE_DIV8  (0x2 << 8)
0060 #define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
0061 #define XADC_ZYNQ_CFG_IGAP_MASK     0x1f
0062 #define XADC_ZYNQ_CFG_IGAP(x)       (x)
0063 
0064 #define XADC_ZYNQ_INT_CFIFO_LTH     BIT(9)
0065 #define XADC_ZYNQ_INT_DFIFO_GTH     BIT(8)
0066 #define XADC_ZYNQ_INT_ALARM_MASK    0xff
0067 #define XADC_ZYNQ_INT_ALARM_OFFSET  0
0068 
0069 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
0070 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET   16
0071 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
0072 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET   12
0073 #define XADC_ZYNQ_STATUS_CFIFOF     BIT(11)
0074 #define XADC_ZYNQ_STATUS_CFIFOE     BIT(10)
0075 #define XADC_ZYNQ_STATUS_DFIFOF     BIT(9)
0076 #define XADC_ZYNQ_STATUS_DFIFOE     BIT(8)
0077 #define XADC_ZYNQ_STATUS_OT     BIT(7)
0078 #define XADC_ZYNQ_STATUS_ALM(x)     BIT(x)
0079 
0080 #define XADC_ZYNQ_CTL_RESET     BIT(4)
0081 
0082 #define XADC_ZYNQ_CMD_NOP       0x00
0083 #define XADC_ZYNQ_CMD_READ      0x01
0084 #define XADC_ZYNQ_CMD_WRITE     0x02
0085 
0086 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
0087 
0088 /* AXI register definitions */
0089 #define XADC_AXI_REG_RESET      0x00
0090 #define XADC_AXI_REG_STATUS     0x04
0091 #define XADC_AXI_REG_ALARM_STATUS   0x08
0092 #define XADC_AXI_REG_CONVST     0x0c
0093 #define XADC_AXI_REG_XADC_RESET     0x10
0094 #define XADC_AXI_REG_GIER       0x5c
0095 #define XADC_AXI_REG_IPISR      0x60
0096 #define XADC_AXI_REG_IPIER      0x68
0097 
0098 /* 7 Series */
0099 #define XADC_7S_AXI_ADC_REG_OFFSET  0x200
0100 
0101 /* UltraScale */
0102 #define XADC_US_AXI_ADC_REG_OFFSET  0x400
0103 
0104 #define XADC_AXI_RESET_MAGIC        0xa
0105 #define XADC_AXI_GIER_ENABLE        BIT(31)
0106 
0107 #define XADC_AXI_INT_EOS        BIT(4)
0108 #define XADC_AXI_INT_ALARM_MASK     0x3c0f
0109 
0110 #define XADC_FLAGS_BUFFERED BIT(0)
0111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
0112 
0113 /*
0114  * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
0115  * not have a hardware FIFO. Which means an interrupt is generated for each
0116  * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
0117  * overloaded by the interrupts that it soft-lockups. For this reason the driver
0118  * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
0119  * but still responsive.
0120  */
0121 #define XADC_MAX_SAMPLERATE 150000
0122 
0123 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
0124     uint32_t val)
0125 {
0126     writel(val, xadc->base + reg);
0127 }
0128 
0129 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
0130     uint32_t *val)
0131 {
0132     *val = readl(xadc->base + reg);
0133 }
0134 
0135 /*
0136  * The ZYNQ interface uses two asynchronous FIFOs for communication with the
0137  * XADC. Reads and writes to the XADC register are performed by submitting a
0138  * request to the command FIFO (CFIFO), once the request has been completed the
0139  * result can be read from the data FIFO (DFIFO). The method currently used in
0140  * this driver is to submit the request for a read/write operation, then go to
0141  * sleep and wait for an interrupt that signals that a response is available in
0142  * the data FIFO.
0143  */
0144 
0145 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
0146     unsigned int n)
0147 {
0148     unsigned int i;
0149 
0150     for (i = 0; i < n; i++)
0151         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
0152 }
0153 
0154 static void xadc_zynq_drain_fifo(struct xadc *xadc)
0155 {
0156     uint32_t status, tmp;
0157 
0158     xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
0159 
0160     while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
0161         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
0162         xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
0163     }
0164 }
0165 
0166 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
0167     unsigned int val)
0168 {
0169     xadc->zynq_intmask &= ~mask;
0170     xadc->zynq_intmask |= val;
0171 
0172     xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
0173         xadc->zynq_intmask | xadc->zynq_masked_alarm);
0174 }
0175 
0176 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
0177     uint16_t val)
0178 {
0179     uint32_t cmd[1];
0180     uint32_t tmp;
0181     int ret;
0182 
0183     spin_lock_irq(&xadc->lock);
0184     xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
0185             XADC_ZYNQ_INT_DFIFO_GTH);
0186 
0187     reinit_completion(&xadc->completion);
0188 
0189     cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
0190     xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
0191     xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
0192     tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
0193     tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
0194     xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
0195 
0196     xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
0197     spin_unlock_irq(&xadc->lock);
0198 
0199     ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
0200     if (ret == 0)
0201         ret = -EIO;
0202     else
0203         ret = 0;
0204 
0205     xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
0206 
0207     return ret;
0208 }
0209 
0210 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
0211     uint16_t *val)
0212 {
0213     uint32_t cmd[2];
0214     uint32_t resp, tmp;
0215     int ret;
0216 
0217     cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
0218     cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
0219 
0220     spin_lock_irq(&xadc->lock);
0221     xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
0222             XADC_ZYNQ_INT_DFIFO_GTH);
0223     xadc_zynq_drain_fifo(xadc);
0224     reinit_completion(&xadc->completion);
0225 
0226     xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
0227     xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
0228     tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
0229     tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
0230     xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
0231 
0232     xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
0233     spin_unlock_irq(&xadc->lock);
0234     ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
0235     if (ret == 0)
0236         ret = -EIO;
0237     if (ret < 0)
0238         return ret;
0239 
0240     xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
0241     xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
0242 
0243     *val = resp & 0xffff;
0244 
0245     return 0;
0246 }
0247 
0248 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
0249 {
0250     return ((alarm & 0x80) >> 4) |
0251         ((alarm & 0x78) << 1) |
0252         (alarm & 0x07);
0253 }
0254 
0255 /*
0256  * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
0257  * threshold condition go way from within the interrupt handler, this means as
0258  * soon as a threshold condition is present we would enter the interrupt handler
0259  * again and again. To work around this we mask all active thresholds interrupts
0260  * in the interrupt handler and start a timer. In this timer we poll the
0261  * interrupt status and only if the interrupt is inactive we unmask it again.
0262  */
0263 static void xadc_zynq_unmask_worker(struct work_struct *work)
0264 {
0265     struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
0266     unsigned int misc_sts, unmask;
0267 
0268     xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
0269 
0270     misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
0271 
0272     spin_lock_irq(&xadc->lock);
0273 
0274     /* Clear those bits which are not active anymore */
0275     unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
0276     xadc->zynq_masked_alarm &= misc_sts;
0277 
0278     /* Also clear those which are masked out anyway */
0279     xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
0280 
0281     /* Clear the interrupts before we unmask them */
0282     xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
0283 
0284     xadc_zynq_update_intmsk(xadc, 0, 0);
0285 
0286     spin_unlock_irq(&xadc->lock);
0287 
0288     /* if still pending some alarm re-trigger the timer */
0289     if (xadc->zynq_masked_alarm) {
0290         schedule_delayed_work(&xadc->zynq_unmask_work,
0291                 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
0292     }
0293 
0294 }
0295 
0296 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
0297 {
0298     struct iio_dev *indio_dev = devid;
0299     struct xadc *xadc = iio_priv(indio_dev);
0300     uint32_t status;
0301 
0302     xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
0303 
0304     status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
0305 
0306     if (!status)
0307         return IRQ_NONE;
0308 
0309     spin_lock(&xadc->lock);
0310 
0311     xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
0312 
0313     if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
0314         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
0315             XADC_ZYNQ_INT_DFIFO_GTH);
0316         complete(&xadc->completion);
0317     }
0318 
0319     status &= XADC_ZYNQ_INT_ALARM_MASK;
0320     if (status) {
0321         xadc->zynq_masked_alarm |= status;
0322         /*
0323          * mask the current event interrupt,
0324          * unmask it when the interrupt is no more active.
0325          */
0326         xadc_zynq_update_intmsk(xadc, 0, 0);
0327 
0328         xadc_handle_events(indio_dev,
0329                 xadc_zynq_transform_alarm(status));
0330 
0331         /* unmask the required interrupts in timer. */
0332         schedule_delayed_work(&xadc->zynq_unmask_work,
0333                 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
0334     }
0335     spin_unlock(&xadc->lock);
0336 
0337     return IRQ_HANDLED;
0338 }
0339 
0340 #define XADC_ZYNQ_TCK_RATE_MAX 50000000
0341 #define XADC_ZYNQ_IGAP_DEFAULT 20
0342 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
0343 
0344 static int xadc_zynq_setup(struct platform_device *pdev,
0345     struct iio_dev *indio_dev, int irq)
0346 {
0347     struct xadc *xadc = iio_priv(indio_dev);
0348     unsigned long pcap_rate;
0349     unsigned int tck_div;
0350     unsigned int div;
0351     unsigned int igap;
0352     unsigned int tck_rate;
0353     int ret;
0354 
0355     /* TODO: Figure out how to make igap and tck_rate configurable */
0356     igap = XADC_ZYNQ_IGAP_DEFAULT;
0357     tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
0358 
0359     xadc->zynq_intmask = ~0;
0360 
0361     pcap_rate = clk_get_rate(xadc->clk);
0362     if (!pcap_rate)
0363         return -EINVAL;
0364 
0365     if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
0366         ret = clk_set_rate(xadc->clk,
0367                    (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
0368         if (ret)
0369             return ret;
0370     }
0371 
0372     if (tck_rate > pcap_rate / 2) {
0373         div = 2;
0374     } else {
0375         div = pcap_rate / tck_rate;
0376         if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
0377             div++;
0378     }
0379 
0380     if (div <= 3)
0381         tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
0382     else if (div <= 7)
0383         tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
0384     else if (div <= 15)
0385         tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
0386     else
0387         tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
0388 
0389     xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
0390     xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
0391     xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
0392     xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
0393     xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
0394             XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
0395             tck_div | XADC_ZYNQ_CFG_IGAP(igap));
0396 
0397     if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
0398         ret = clk_set_rate(xadc->clk, pcap_rate);
0399         if (ret)
0400             return ret;
0401     }
0402 
0403     return 0;
0404 }
0405 
0406 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
0407 {
0408     unsigned int div;
0409     uint32_t val;
0410 
0411     xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
0412 
0413     switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
0414     case XADC_ZYNQ_CFG_TCKRATE_DIV4:
0415         div = 4;
0416         break;
0417     case XADC_ZYNQ_CFG_TCKRATE_DIV8:
0418         div = 8;
0419         break;
0420     case XADC_ZYNQ_CFG_TCKRATE_DIV16:
0421         div = 16;
0422         break;
0423     default:
0424         div = 2;
0425         break;
0426     }
0427 
0428     return clk_get_rate(xadc->clk) / div;
0429 }
0430 
0431 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
0432 {
0433     unsigned long flags;
0434     uint32_t status;
0435 
0436     /* Move OT to bit 7 */
0437     alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
0438 
0439     spin_lock_irqsave(&xadc->lock, flags);
0440 
0441     /* Clear previous interrupts if any. */
0442     xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
0443     xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
0444 
0445     xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
0446         ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
0447 
0448     spin_unlock_irqrestore(&xadc->lock, flags);
0449 }
0450 
0451 static const struct xadc_ops xadc_zynq_ops = {
0452     .read = xadc_zynq_read_adc_reg,
0453     .write = xadc_zynq_write_adc_reg,
0454     .setup = xadc_zynq_setup,
0455     .get_dclk_rate = xadc_zynq_get_dclk_rate,
0456     .interrupt_handler = xadc_zynq_interrupt_handler,
0457     .update_alarm = xadc_zynq_update_alarm,
0458     .type = XADC_TYPE_S7,
0459 };
0460 
0461 static const unsigned int xadc_axi_reg_offsets[] = {
0462     [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
0463     [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
0464 };
0465 
0466 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
0467     uint16_t *val)
0468 {
0469     uint32_t val32;
0470 
0471     xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
0472         &val32);
0473     *val = val32 & 0xffff;
0474 
0475     return 0;
0476 }
0477 
0478 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
0479     uint16_t val)
0480 {
0481     xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
0482         val);
0483 
0484     return 0;
0485 }
0486 
0487 static int xadc_axi_setup(struct platform_device *pdev,
0488     struct iio_dev *indio_dev, int irq)
0489 {
0490     struct xadc *xadc = iio_priv(indio_dev);
0491 
0492     xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
0493     xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
0494 
0495     return 0;
0496 }
0497 
0498 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
0499 {
0500     struct iio_dev *indio_dev = devid;
0501     struct xadc *xadc = iio_priv(indio_dev);
0502     uint32_t status, mask;
0503     unsigned int events;
0504 
0505     xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
0506     xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
0507     status &= mask;
0508 
0509     if (!status)
0510         return IRQ_NONE;
0511 
0512     if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
0513         iio_trigger_poll(xadc->trigger);
0514 
0515     if (status & XADC_AXI_INT_ALARM_MASK) {
0516         /*
0517          * The order of the bits in the AXI-XADC status register does
0518          * not match the order of the bits in the XADC alarm enable
0519          * register. xadc_handle_events() expects the events to be in
0520          * the same order as the XADC alarm enable register.
0521          */
0522         events = (status & 0x000e) >> 1;
0523         events |= (status & 0x0001) << 3;
0524         events |= (status & 0x3c00) >> 6;
0525         xadc_handle_events(indio_dev, events);
0526     }
0527 
0528     xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
0529 
0530     return IRQ_HANDLED;
0531 }
0532 
0533 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
0534 {
0535     uint32_t val;
0536     unsigned long flags;
0537 
0538     /*
0539      * The order of the bits in the AXI-XADC status register does not match
0540      * the order of the bits in the XADC alarm enable register. We get
0541      * passed the alarm mask in the same order as in the XADC alarm enable
0542      * register.
0543      */
0544     alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
0545             ((alarm & 0xf0) << 6);
0546 
0547     spin_lock_irqsave(&xadc->lock, flags);
0548     xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
0549     val &= ~XADC_AXI_INT_ALARM_MASK;
0550     val |= alarm;
0551     xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
0552     spin_unlock_irqrestore(&xadc->lock, flags);
0553 }
0554 
0555 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
0556 {
0557     return clk_get_rate(xadc->clk);
0558 }
0559 
0560 static const struct xadc_ops xadc_7s_axi_ops = {
0561     .read = xadc_axi_read_adc_reg,
0562     .write = xadc_axi_write_adc_reg,
0563     .setup = xadc_axi_setup,
0564     .get_dclk_rate = xadc_axi_get_dclk,
0565     .update_alarm = xadc_axi_update_alarm,
0566     .interrupt_handler = xadc_axi_interrupt_handler,
0567     .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
0568     .type = XADC_TYPE_S7,
0569 };
0570 
0571 static const struct xadc_ops xadc_us_axi_ops = {
0572     .read = xadc_axi_read_adc_reg,
0573     .write = xadc_axi_write_adc_reg,
0574     .setup = xadc_axi_setup,
0575     .get_dclk_rate = xadc_axi_get_dclk,
0576     .update_alarm = xadc_axi_update_alarm,
0577     .interrupt_handler = xadc_axi_interrupt_handler,
0578     .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
0579     .type = XADC_TYPE_US,
0580 };
0581 
0582 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
0583     uint16_t mask, uint16_t val)
0584 {
0585     uint16_t tmp;
0586     int ret;
0587 
0588     ret = _xadc_read_adc_reg(xadc, reg, &tmp);
0589     if (ret)
0590         return ret;
0591 
0592     return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
0593 }
0594 
0595 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
0596     uint16_t mask, uint16_t val)
0597 {
0598     int ret;
0599 
0600     mutex_lock(&xadc->mutex);
0601     ret = _xadc_update_adc_reg(xadc, reg, mask, val);
0602     mutex_unlock(&xadc->mutex);
0603 
0604     return ret;
0605 }
0606 
0607 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
0608 {
0609     return xadc->ops->get_dclk_rate(xadc);
0610 }
0611 
0612 static int xadc_update_scan_mode(struct iio_dev *indio_dev,
0613     const unsigned long *mask)
0614 {
0615     struct xadc *xadc = iio_priv(indio_dev);
0616     size_t new_size, n;
0617     void *data;
0618 
0619     n = bitmap_weight(mask, indio_dev->masklength);
0620 
0621     if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))
0622         return -ENOMEM;
0623 
0624     data = devm_krealloc(indio_dev->dev.parent, xadc->data,
0625                  new_size, GFP_KERNEL);
0626     if (!data)
0627         return -ENOMEM;
0628 
0629     memset(data, 0, new_size);
0630     xadc->data = data;
0631 
0632     return 0;
0633 }
0634 
0635 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
0636 {
0637     switch (scan_index) {
0638     case 5:
0639         return XADC_REG_VCCPINT;
0640     case 6:
0641         return XADC_REG_VCCPAUX;
0642     case 7:
0643         return XADC_REG_VCCO_DDR;
0644     case 8:
0645         return XADC_REG_TEMP;
0646     case 9:
0647         return XADC_REG_VCCINT;
0648     case 10:
0649         return XADC_REG_VCCAUX;
0650     case 11:
0651         return XADC_REG_VPVN;
0652     case 12:
0653         return XADC_REG_VREFP;
0654     case 13:
0655         return XADC_REG_VREFN;
0656     case 14:
0657         return XADC_REG_VCCBRAM;
0658     default:
0659         return XADC_REG_VAUX(scan_index - 16);
0660     }
0661 }
0662 
0663 static irqreturn_t xadc_trigger_handler(int irq, void *p)
0664 {
0665     struct iio_poll_func *pf = p;
0666     struct iio_dev *indio_dev = pf->indio_dev;
0667     struct xadc *xadc = iio_priv(indio_dev);
0668     unsigned int chan;
0669     int i, j;
0670 
0671     if (!xadc->data)
0672         goto out;
0673 
0674     j = 0;
0675     for_each_set_bit(i, indio_dev->active_scan_mask,
0676         indio_dev->masklength) {
0677         chan = xadc_scan_index_to_channel(i);
0678         xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
0679         j++;
0680     }
0681 
0682     iio_push_to_buffers(indio_dev, xadc->data);
0683 
0684 out:
0685     iio_trigger_notify_done(indio_dev->trig);
0686 
0687     return IRQ_HANDLED;
0688 }
0689 
0690 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
0691 {
0692     struct xadc *xadc = iio_trigger_get_drvdata(trigger);
0693     unsigned long flags;
0694     unsigned int convst;
0695     unsigned int val;
0696     int ret = 0;
0697 
0698     mutex_lock(&xadc->mutex);
0699 
0700     if (state) {
0701         /* Only one of the two triggers can be active at a time. */
0702         if (xadc->trigger != NULL) {
0703             ret = -EBUSY;
0704             goto err_out;
0705         } else {
0706             xadc->trigger = trigger;
0707             if (trigger == xadc->convst_trigger)
0708                 convst = XADC_CONF0_EC;
0709             else
0710                 convst = 0;
0711         }
0712         ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
0713                     convst);
0714         if (ret)
0715             goto err_out;
0716     } else {
0717         xadc->trigger = NULL;
0718     }
0719 
0720     spin_lock_irqsave(&xadc->lock, flags);
0721     xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
0722     xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
0723     if (state)
0724         val |= XADC_AXI_INT_EOS;
0725     else
0726         val &= ~XADC_AXI_INT_EOS;
0727     xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
0728     spin_unlock_irqrestore(&xadc->lock, flags);
0729 
0730 err_out:
0731     mutex_unlock(&xadc->mutex);
0732 
0733     return ret;
0734 }
0735 
0736 static const struct iio_trigger_ops xadc_trigger_ops = {
0737     .set_trigger_state = &xadc_trigger_set_state,
0738 };
0739 
0740 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
0741     const char *name)
0742 {
0743     struct device *dev = indio_dev->dev.parent;
0744     struct iio_trigger *trig;
0745     int ret;
0746 
0747     trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
0748                       iio_device_id(indio_dev), name);
0749     if (trig == NULL)
0750         return ERR_PTR(-ENOMEM);
0751 
0752     trig->ops = &xadc_trigger_ops;
0753     iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
0754 
0755     ret = devm_iio_trigger_register(dev, trig);
0756     if (ret)
0757         return ERR_PTR(ret);
0758 
0759     return trig;
0760 }
0761 
0762 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
0763 {
0764     uint16_t val;
0765 
0766     /*
0767      * As per datasheet the power-down bits are don't care in the
0768      * UltraScale, but as per reality setting the power-down bit for the
0769      * non-existing ADC-B powers down the main ADC, so just return and don't
0770      * do anything.
0771      */
0772     if (xadc->ops->type == XADC_TYPE_US)
0773         return 0;
0774 
0775     /* Powerdown the ADC-B when it is not needed. */
0776     switch (seq_mode) {
0777     case XADC_CONF1_SEQ_SIMULTANEOUS:
0778     case XADC_CONF1_SEQ_INDEPENDENT:
0779         val = 0;
0780         break;
0781     default:
0782         val = XADC_CONF2_PD_ADC_B;
0783         break;
0784     }
0785 
0786     return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
0787         val);
0788 }
0789 
0790 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
0791 {
0792     unsigned int aux_scan_mode = scan_mode >> 16;
0793 
0794     /* UltraScale has only one ADC and supports only continuous mode */
0795     if (xadc->ops->type == XADC_TYPE_US)
0796         return XADC_CONF1_SEQ_CONTINUOUS;
0797 
0798     if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
0799         return XADC_CONF1_SEQ_SIMULTANEOUS;
0800 
0801     if ((aux_scan_mode & 0xff00) == 0 ||
0802         (aux_scan_mode & 0x00ff) == 0)
0803         return XADC_CONF1_SEQ_CONTINUOUS;
0804 
0805     return XADC_CONF1_SEQ_SIMULTANEOUS;
0806 }
0807 
0808 static int xadc_postdisable(struct iio_dev *indio_dev)
0809 {
0810     struct xadc *xadc = iio_priv(indio_dev);
0811     unsigned long scan_mask;
0812     int ret;
0813     int i;
0814 
0815     scan_mask = 1; /* Run calibration as part of the sequence */
0816     for (i = 0; i < indio_dev->num_channels; i++)
0817         scan_mask |= BIT(indio_dev->channels[i].scan_index);
0818 
0819     /* Enable all channels and calibration */
0820     ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
0821     if (ret)
0822         return ret;
0823 
0824     ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
0825     if (ret)
0826         return ret;
0827 
0828     ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
0829         XADC_CONF1_SEQ_CONTINUOUS);
0830     if (ret)
0831         return ret;
0832 
0833     return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
0834 }
0835 
0836 static int xadc_preenable(struct iio_dev *indio_dev)
0837 {
0838     struct xadc *xadc = iio_priv(indio_dev);
0839     unsigned long scan_mask;
0840     int seq_mode;
0841     int ret;
0842 
0843     ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
0844         XADC_CONF1_SEQ_DEFAULT);
0845     if (ret)
0846         goto err;
0847 
0848     scan_mask = *indio_dev->active_scan_mask;
0849     seq_mode = xadc_get_seq_mode(xadc, scan_mask);
0850 
0851     ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
0852     if (ret)
0853         goto err;
0854 
0855     /*
0856      * In simultaneous mode the upper and lower aux channels are samples at
0857      * the same time. In this mode the upper 8 bits in the sequencer
0858      * register are don't care and the lower 8 bits control two channels
0859      * each. As such we must set the bit if either the channel in the lower
0860      * group or the upper group is enabled.
0861      */
0862     if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
0863         scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
0864 
0865     ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
0866     if (ret)
0867         goto err;
0868 
0869     ret = xadc_power_adc_b(xadc, seq_mode);
0870     if (ret)
0871         goto err;
0872 
0873     ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
0874         seq_mode);
0875     if (ret)
0876         goto err;
0877 
0878     return 0;
0879 err:
0880     xadc_postdisable(indio_dev);
0881     return ret;
0882 }
0883 
0884 static const struct iio_buffer_setup_ops xadc_buffer_ops = {
0885     .preenable = &xadc_preenable,
0886     .postdisable = &xadc_postdisable,
0887 };
0888 
0889 static int xadc_read_samplerate(struct xadc *xadc)
0890 {
0891     unsigned int div;
0892     uint16_t val16;
0893     int ret;
0894 
0895     ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
0896     if (ret)
0897         return ret;
0898 
0899     div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
0900     if (div < 2)
0901         div = 2;
0902 
0903     return xadc_get_dclk_rate(xadc) / div / 26;
0904 }
0905 
0906 static int xadc_read_raw(struct iio_dev *indio_dev,
0907     struct iio_chan_spec const *chan, int *val, int *val2, long info)
0908 {
0909     struct xadc *xadc = iio_priv(indio_dev);
0910     unsigned int bits = chan->scan_type.realbits;
0911     uint16_t val16;
0912     int ret;
0913 
0914     switch (info) {
0915     case IIO_CHAN_INFO_RAW:
0916         if (iio_buffer_enabled(indio_dev))
0917             return -EBUSY;
0918         ret = xadc_read_adc_reg(xadc, chan->address, &val16);
0919         if (ret < 0)
0920             return ret;
0921 
0922         val16 >>= chan->scan_type.shift;
0923         if (chan->scan_type.sign == 'u')
0924             *val = val16;
0925         else
0926             *val = sign_extend32(val16, bits - 1);
0927 
0928         return IIO_VAL_INT;
0929     case IIO_CHAN_INFO_SCALE:
0930         switch (chan->type) {
0931         case IIO_VOLTAGE:
0932             /* V = (val * 3.0) / 2**bits */
0933             switch (chan->address) {
0934             case XADC_REG_VCCINT:
0935             case XADC_REG_VCCAUX:
0936             case XADC_REG_VREFP:
0937             case XADC_REG_VREFN:
0938             case XADC_REG_VCCBRAM:
0939             case XADC_REG_VCCPINT:
0940             case XADC_REG_VCCPAUX:
0941             case XADC_REG_VCCO_DDR:
0942                 *val = 3000;
0943                 break;
0944             default:
0945                 *val = 1000;
0946                 break;
0947             }
0948             *val2 = bits;
0949             return IIO_VAL_FRACTIONAL_LOG2;
0950         case IIO_TEMP:
0951             /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
0952             *val = 503975;
0953             *val2 = bits;
0954             return IIO_VAL_FRACTIONAL_LOG2;
0955         default:
0956             return -EINVAL;
0957         }
0958     case IIO_CHAN_INFO_OFFSET:
0959         /* Only the temperature channel has an offset */
0960         *val = -((273150 << bits) / 503975);
0961         return IIO_VAL_INT;
0962     case IIO_CHAN_INFO_SAMP_FREQ:
0963         ret = xadc_read_samplerate(xadc);
0964         if (ret < 0)
0965             return ret;
0966 
0967         *val = ret;
0968         return IIO_VAL_INT;
0969     default:
0970         return -EINVAL;
0971     }
0972 }
0973 
0974 static int xadc_write_samplerate(struct xadc *xadc, int val)
0975 {
0976     unsigned long clk_rate = xadc_get_dclk_rate(xadc);
0977     unsigned int div;
0978 
0979     if (!clk_rate)
0980         return -EINVAL;
0981 
0982     if (val <= 0)
0983         return -EINVAL;
0984 
0985     /* Max. 150 kSPS */
0986     if (val > XADC_MAX_SAMPLERATE)
0987         val = XADC_MAX_SAMPLERATE;
0988 
0989     val *= 26;
0990 
0991     /* Min 1MHz */
0992     if (val < 1000000)
0993         val = 1000000;
0994 
0995     /*
0996      * We want to round down, but only if we do not exceed the 150 kSPS
0997      * limit.
0998      */
0999     div = clk_rate / val;
1000     if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
1001         div++;
1002     if (div < 2)
1003         div = 2;
1004     else if (div > 0xff)
1005         div = 0xff;
1006 
1007     return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1008         div << XADC_CONF2_DIV_OFFSET);
1009 }
1010 
1011 static int xadc_write_raw(struct iio_dev *indio_dev,
1012     struct iio_chan_spec const *chan, int val, int val2, long info)
1013 {
1014     struct xadc *xadc = iio_priv(indio_dev);
1015 
1016     if (info != IIO_CHAN_INFO_SAMP_FREQ)
1017         return -EINVAL;
1018 
1019     return xadc_write_samplerate(xadc, val);
1020 }
1021 
1022 static const struct iio_event_spec xadc_temp_events[] = {
1023     {
1024         .type = IIO_EV_TYPE_THRESH,
1025         .dir = IIO_EV_DIR_RISING,
1026         .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1027                 BIT(IIO_EV_INFO_VALUE) |
1028                 BIT(IIO_EV_INFO_HYSTERESIS),
1029     },
1030 };
1031 
1032 /* Separate values for upper and lower thresholds, but only a shared enabled */
1033 static const struct iio_event_spec xadc_voltage_events[] = {
1034     {
1035         .type = IIO_EV_TYPE_THRESH,
1036         .dir = IIO_EV_DIR_RISING,
1037         .mask_separate = BIT(IIO_EV_INFO_VALUE),
1038     }, {
1039         .type = IIO_EV_TYPE_THRESH,
1040         .dir = IIO_EV_DIR_FALLING,
1041         .mask_separate = BIT(IIO_EV_INFO_VALUE),
1042     }, {
1043         .type = IIO_EV_TYPE_THRESH,
1044         .dir = IIO_EV_DIR_EITHER,
1045         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1046     },
1047 };
1048 
1049 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1050     .type = IIO_TEMP, \
1051     .indexed = 1, \
1052     .channel = (_chan), \
1053     .address = (_addr), \
1054     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1055         BIT(IIO_CHAN_INFO_SCALE) | \
1056         BIT(IIO_CHAN_INFO_OFFSET), \
1057     .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1058     .event_spec = xadc_temp_events, \
1059     .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1060     .scan_index = (_scan_index), \
1061     .scan_type = { \
1062         .sign = 'u', \
1063         .realbits = (_bits), \
1064         .storagebits = 16, \
1065         .shift = 16 - (_bits), \
1066         .endianness = IIO_CPU, \
1067     }, \
1068 }
1069 
1070 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1071     .type = IIO_VOLTAGE, \
1072     .indexed = 1, \
1073     .channel = (_chan), \
1074     .address = (_addr), \
1075     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1076         BIT(IIO_CHAN_INFO_SCALE), \
1077     .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1078     .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1079     .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1080     .scan_index = (_scan_index), \
1081     .scan_type = { \
1082         .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1083         .realbits = (_bits), \
1084         .storagebits = 16, \
1085         .shift = 16 - (_bits), \
1086         .endianness = IIO_CPU, \
1087     }, \
1088     .extend_name = _ext, \
1089 }
1090 
1091 /* 7 Series */
1092 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1093     XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1094 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1095     XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1096 
1097 static const struct iio_chan_spec xadc_7s_channels[] = {
1098     XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1099     XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1100     XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1101     XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1102     XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1103     XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1104     XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1105     XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1106     XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1107     XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1108     XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1109     XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1110     XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1111     XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1112     XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1113     XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1114     XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1115     XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1116     XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1117     XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1118     XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1119     XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1120     XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1121     XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1122     XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1123     XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1124 };
1125 
1126 /* UltraScale */
1127 #define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1128     XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1129 #define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1130     XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1131 
1132 static const struct iio_chan_spec xadc_us_channels[] = {
1133     XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1134     XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1135     XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1136     XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1137     XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1138     XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1139     XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1140     XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1141     XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1142     XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1143     XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1144     XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1145     XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1146     XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1147     XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1148     XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1149     XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1150     XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1151     XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1152     XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1153     XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1154     XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1155     XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1156     XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1157     XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1158     XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1159 };
1160 
1161 static const struct iio_info xadc_info = {
1162     .read_raw = &xadc_read_raw,
1163     .write_raw = &xadc_write_raw,
1164     .read_event_config = &xadc_read_event_config,
1165     .write_event_config = &xadc_write_event_config,
1166     .read_event_value = &xadc_read_event_value,
1167     .write_event_value = &xadc_write_event_value,
1168     .update_scan_mode = &xadc_update_scan_mode,
1169 };
1170 
1171 static const struct of_device_id xadc_of_match_table[] = {
1172     {
1173         .compatible = "xlnx,zynq-xadc-1.00.a",
1174         .data = &xadc_zynq_ops
1175     }, {
1176         .compatible = "xlnx,axi-xadc-1.00.a",
1177         .data = &xadc_7s_axi_ops
1178     }, {
1179         .compatible = "xlnx,system-management-wiz-1.3",
1180         .data = &xadc_us_axi_ops
1181     },
1182     { },
1183 };
1184 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1185 
1186 static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
1187 {
1188     struct device *dev = indio_dev->dev.parent;
1189     struct xadc *xadc = iio_priv(indio_dev);
1190     const struct iio_chan_spec *channel_templates;
1191     struct iio_chan_spec *channels, *chan;
1192     struct fwnode_handle *chan_node, *child;
1193     unsigned int max_channels;
1194     unsigned int num_channels;
1195     const char *external_mux;
1196     u32 ext_mux_chan;
1197     u32 reg;
1198     int ret;
1199     int i;
1200 
1201     *conf = 0;
1202 
1203     ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);
1204     if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1205         xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1206     else if (strcasecmp(external_mux, "single") == 0)
1207         xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1208     else if (strcasecmp(external_mux, "dual") == 0)
1209         xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1210     else
1211         return -EINVAL;
1212 
1213     if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1214         ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);
1215         if (ret < 0)
1216             return ret;
1217 
1218         if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1219             if (ext_mux_chan == 0)
1220                 ext_mux_chan = XADC_REG_VPVN;
1221             else if (ext_mux_chan <= 16)
1222                 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1223             else
1224                 return -EINVAL;
1225         } else {
1226             if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1227                 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1228             else
1229                 return -EINVAL;
1230         }
1231 
1232         *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1233     }
1234     if (xadc->ops->type == XADC_TYPE_S7) {
1235         channel_templates = xadc_7s_channels;
1236         max_channels = ARRAY_SIZE(xadc_7s_channels);
1237     } else {
1238         channel_templates = xadc_us_channels;
1239         max_channels = ARRAY_SIZE(xadc_us_channels);
1240     }
1241     channels = devm_kmemdup(dev, channel_templates,
1242                 sizeof(channels[0]) * max_channels, GFP_KERNEL);
1243     if (!channels)
1244         return -ENOMEM;
1245 
1246     num_channels = 9;
1247     chan = &channels[9];
1248 
1249     chan_node = device_get_named_child_node(dev, "xlnx,channels");
1250     fwnode_for_each_child_node(chan_node, child) {
1251         if (num_channels >= max_channels) {
1252             fwnode_handle_put(child);
1253             break;
1254         }
1255 
1256         ret = fwnode_property_read_u32(child, "reg", &reg);
1257         if (ret || reg > 16)
1258             continue;
1259 
1260         if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1261             chan->scan_type.sign = 's';
1262 
1263         if (reg == 0) {
1264             chan->scan_index = 11;
1265             chan->address = XADC_REG_VPVN;
1266         } else {
1267             chan->scan_index = 15 + reg;
1268             chan->address = XADC_REG_VAUX(reg - 1);
1269         }
1270         num_channels++;
1271         chan++;
1272     }
1273     fwnode_handle_put(chan_node);
1274 
1275     /* No IRQ => no events */
1276     if (irq <= 0) {
1277         for (i = 0; i < num_channels; i++) {
1278             channels[i].event_spec = NULL;
1279             channels[i].num_event_specs = 0;
1280         }
1281     }
1282 
1283     indio_dev->num_channels = num_channels;
1284     indio_dev->channels = devm_krealloc(dev, channels,
1285                         sizeof(*channels) * num_channels,
1286                         GFP_KERNEL);
1287     /* If we can't resize the channels array, just use the original */
1288     if (!indio_dev->channels)
1289         indio_dev->channels = channels;
1290 
1291     return 0;
1292 }
1293 
1294 static const char * const xadc_type_names[] = {
1295     [XADC_TYPE_S7] = "xadc",
1296     [XADC_TYPE_US] = "xilinx-system-monitor",
1297 };
1298 
1299 static void xadc_clk_disable_unprepare(void *data)
1300 {
1301     struct clk *clk = data;
1302 
1303     clk_disable_unprepare(clk);
1304 }
1305 
1306 static void xadc_cancel_delayed_work(void *data)
1307 {
1308     struct delayed_work *work = data;
1309 
1310     cancel_delayed_work_sync(work);
1311 }
1312 
1313 static int xadc_probe(struct platform_device *pdev)
1314 {
1315     struct device *dev = &pdev->dev;
1316     const struct xadc_ops *ops;
1317     struct iio_dev *indio_dev;
1318     unsigned int bipolar_mask;
1319     unsigned int conf0;
1320     struct xadc *xadc;
1321     int ret;
1322     int irq;
1323     int i;
1324 
1325     ops = device_get_match_data(dev);
1326     if (!ops)
1327         return -EINVAL;
1328 
1329     irq = platform_get_irq_optional(pdev, 0);
1330     if (irq < 0 &&
1331         (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
1332         return irq;
1333 
1334     indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1335     if (!indio_dev)
1336         return -ENOMEM;
1337 
1338     xadc = iio_priv(indio_dev);
1339     xadc->ops = ops;
1340     init_completion(&xadc->completion);
1341     mutex_init(&xadc->mutex);
1342     spin_lock_init(&xadc->lock);
1343     INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1344 
1345     xadc->base = devm_platform_ioremap_resource(pdev, 0);
1346     if (IS_ERR(xadc->base))
1347         return PTR_ERR(xadc->base);
1348 
1349     indio_dev->name = xadc_type_names[xadc->ops->type];
1350     indio_dev->modes = INDIO_DIRECT_MODE;
1351     indio_dev->info = &xadc_info;
1352 
1353     ret = xadc_parse_dt(indio_dev, &conf0, irq);
1354     if (ret)
1355         return ret;
1356 
1357     if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1358         ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1359                               &iio_pollfunc_store_time,
1360                               &xadc_trigger_handler,
1361                               &xadc_buffer_ops);
1362         if (ret)
1363             return ret;
1364 
1365         if (irq > 0) {
1366             xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1367             if (IS_ERR(xadc->convst_trigger))
1368                 return PTR_ERR(xadc->convst_trigger);
1369 
1370             xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1371                 "samplerate");
1372             if (IS_ERR(xadc->samplerate_trigger))
1373                 return PTR_ERR(xadc->samplerate_trigger);
1374         }
1375     }
1376 
1377     xadc->clk = devm_clk_get(dev, NULL);
1378     if (IS_ERR(xadc->clk))
1379         return PTR_ERR(xadc->clk);
1380 
1381     ret = clk_prepare_enable(xadc->clk);
1382     if (ret)
1383         return ret;
1384 
1385     ret = devm_add_action_or_reset(dev,
1386                        xadc_clk_disable_unprepare, xadc->clk);
1387     if (ret)
1388         return ret;
1389 
1390     /*
1391      * Make sure not to exceed the maximum samplerate since otherwise the
1392      * resulting interrupt storm will soft-lock the system.
1393      */
1394     if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1395         ret = xadc_read_samplerate(xadc);
1396         if (ret < 0)
1397             return ret;
1398 
1399         if (ret > XADC_MAX_SAMPLERATE) {
1400             ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1401             if (ret < 0)
1402                 return ret;
1403         }
1404     }
1405 
1406     if (irq > 0) {
1407         ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,
1408                        0, dev_name(dev), indio_dev);
1409         if (ret)
1410             return ret;
1411 
1412         ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1413                            &xadc->zynq_unmask_work);
1414         if (ret)
1415             return ret;
1416     }
1417 
1418     ret = xadc->ops->setup(pdev, indio_dev, irq);
1419     if (ret)
1420         return ret;
1421 
1422     for (i = 0; i < 16; i++)
1423         xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1424             &xadc->threshold[i]);
1425 
1426     ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1427     if (ret)
1428         return ret;
1429 
1430     bipolar_mask = 0;
1431     for (i = 0; i < indio_dev->num_channels; i++) {
1432         if (indio_dev->channels[i].scan_type.sign == 's')
1433             bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1434     }
1435 
1436     ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1437     if (ret)
1438         return ret;
1439 
1440     ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1441         bipolar_mask >> 16);
1442     if (ret)
1443         return ret;
1444 
1445     /* Disable all alarms */
1446     ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
1447                   XADC_CONF1_ALARM_MASK);
1448     if (ret)
1449         return ret;
1450 
1451     /* Set thresholds to min/max */
1452     for (i = 0; i < 16; i++) {
1453         /*
1454          * Set max voltage threshold and both temperature thresholds to
1455          * 0xffff, min voltage threshold to 0.
1456          */
1457         if (i % 8 < 4 || i == 7)
1458             xadc->threshold[i] = 0xffff;
1459         else
1460             xadc->threshold[i] = 0;
1461         ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1462             xadc->threshold[i]);
1463         if (ret)
1464             return ret;
1465     }
1466 
1467     /* Go to non-buffered mode */
1468     xadc_postdisable(indio_dev);
1469 
1470     return devm_iio_device_register(dev, indio_dev);
1471 }
1472 
1473 static struct platform_driver xadc_driver = {
1474     .probe = xadc_probe,
1475     .driver = {
1476         .name = "xadc",
1477         .of_match_table = xadc_of_match_table,
1478     },
1479 };
1480 module_platform_driver(xadc_driver);
1481 
1482 MODULE_LICENSE("GPL v2");
1483 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1484 MODULE_DESCRIPTION("Xilinx XADC IIO driver");
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