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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Xilinx AMS driver
0004  *
0005  *  Copyright (C) 2021 Xilinx, Inc.
0006  *
0007  *  Manish Narani <mnarani@xilinx.com>
0008  *  Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
0009  */
0010 
0011 #include <linux/bits.h>
0012 #include <linux/bitfield.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/devm-helpers.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/iopoll.h>
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/mod_devicetable.h>
0022 #include <linux/overflow.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/property.h>
0025 #include <linux/slab.h>
0026 
0027 #include <linux/iio/events.h>
0028 #include <linux/iio/iio.h>
0029 
0030 /* AMS registers definitions */
0031 #define AMS_ISR_0           0x010
0032 #define AMS_ISR_1           0x014
0033 #define AMS_IER_0           0x020
0034 #define AMS_IER_1           0x024
0035 #define AMS_IDR_0           0x028
0036 #define AMS_IDR_1           0x02C
0037 #define AMS_PS_CSTS         0x040
0038 #define AMS_PL_CSTS         0x044
0039 
0040 #define AMS_VCC_PSPLL0          0x060
0041 #define AMS_VCC_PSPLL3          0x06C
0042 #define AMS_VCCINT          0x078
0043 #define AMS_VCCBRAM         0x07C
0044 #define AMS_VCCAUX          0x080
0045 #define AMS_PSDDRPLL            0x084
0046 #define AMS_PSINTFPDDR          0x09C
0047 
0048 #define AMS_VCC_PSPLL0_CH       48
0049 #define AMS_VCC_PSPLL3_CH       51
0050 #define AMS_VCCINT_CH           54
0051 #define AMS_VCCBRAM_CH          55
0052 #define AMS_VCCAUX_CH           56
0053 #define AMS_PSDDRPLL_CH         57
0054 #define AMS_PSINTFPDDR_CH       63
0055 
0056 #define AMS_REG_CONFIG0         0x100
0057 #define AMS_REG_CONFIG1         0x104
0058 #define AMS_REG_CONFIG3         0x10C
0059 #define AMS_REG_CONFIG4         0x110
0060 #define AMS_REG_SEQ_CH0         0x120
0061 #define AMS_REG_SEQ_CH1         0x124
0062 #define AMS_REG_SEQ_CH2         0x118
0063 
0064 #define AMS_VUSER0_MASK         BIT(0)
0065 #define AMS_VUSER1_MASK         BIT(1)
0066 #define AMS_VUSER2_MASK         BIT(2)
0067 #define AMS_VUSER3_MASK         BIT(3)
0068 
0069 #define AMS_TEMP            0x000
0070 #define AMS_SUPPLY1         0x004
0071 #define AMS_SUPPLY2         0x008
0072 #define AMS_VP_VN           0x00C
0073 #define AMS_VREFP           0x010
0074 #define AMS_VREFN           0x014
0075 #define AMS_SUPPLY3         0x018
0076 #define AMS_SUPPLY4         0x034
0077 #define AMS_SUPPLY5         0x038
0078 #define AMS_SUPPLY6         0x03C
0079 #define AMS_SUPPLY7         0x200
0080 #define AMS_SUPPLY8         0x204
0081 #define AMS_SUPPLY9         0x208
0082 #define AMS_SUPPLY10            0x20C
0083 #define AMS_VCCAMS          0x210
0084 #define AMS_TEMP_REMOTE         0x214
0085 
0086 #define AMS_REG_VAUX(x)         (0x40 + 4 * (x))
0087 
0088 #define AMS_PS_RESET_VALUE      0xFFFF
0089 #define AMS_PL_RESET_VALUE      0xFFFF
0090 
0091 #define AMS_CONF0_CHANNEL_NUM_MASK  GENMASK(6, 0)
0092 
0093 #define AMS_CONF1_SEQ_MASK      GENMASK(15, 12)
0094 #define AMS_CONF1_SEQ_DEFAULT       FIELD_PREP(AMS_CONF1_SEQ_MASK, 0)
0095 #define AMS_CONF1_SEQ_CONTINUOUS    FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
0096 #define AMS_CONF1_SEQ_SINGLE_CHANNEL    FIELD_PREP(AMS_CONF1_SEQ_MASK, 3)
0097 
0098 #define AMS_REG_SEQ0_MASK       GENMASK(15, 0)
0099 #define AMS_REG_SEQ2_MASK       GENMASK(21, 16)
0100 #define AMS_REG_SEQ1_MASK       GENMASK_ULL(37, 22)
0101 
0102 #define AMS_PS_SEQ_MASK         GENMASK(21, 0)
0103 #define AMS_PL_SEQ_MASK         GENMASK_ULL(59, 22)
0104 
0105 #define AMS_ALARM_TEMP          0x140
0106 #define AMS_ALARM_SUPPLY1       0x144
0107 #define AMS_ALARM_SUPPLY2       0x148
0108 #define AMS_ALARM_SUPPLY3       0x160
0109 #define AMS_ALARM_SUPPLY4       0x164
0110 #define AMS_ALARM_SUPPLY5       0x168
0111 #define AMS_ALARM_SUPPLY6       0x16C
0112 #define AMS_ALARM_SUPPLY7       0x180
0113 #define AMS_ALARM_SUPPLY8       0x184
0114 #define AMS_ALARM_SUPPLY9       0x188
0115 #define AMS_ALARM_SUPPLY10      0x18C
0116 #define AMS_ALARM_VCCAMS        0x190
0117 #define AMS_ALARM_TEMP_REMOTE       0x194
0118 #define AMS_ALARM_THRESHOLD_OFF_10  0x10
0119 #define AMS_ALARM_THRESHOLD_OFF_20  0x20
0120 
0121 #define AMS_ALARM_THR_DIRECT_MASK   BIT(1)
0122 #define AMS_ALARM_THR_MIN       0x0000
0123 #define AMS_ALARM_THR_MAX       (BIT(16) - 1)
0124 
0125 #define AMS_ALARM_MASK          GENMASK_ULL(63, 0)
0126 #define AMS_NO_OF_ALARMS        32
0127 #define AMS_PL_ALARM_START      16
0128 #define AMS_PL_ALARM_MASK       GENMASK(31, 16)
0129 #define AMS_ISR0_ALARM_MASK     GENMASK(31, 0)
0130 #define AMS_ISR1_ALARM_MASK     (GENMASK(31, 29) | GENMASK(4, 0))
0131 #define AMS_ISR1_EOC_MASK       BIT(3)
0132 #define AMS_ISR1_INTR_MASK      GENMASK_ULL(63, 32)
0133 #define AMS_ISR0_ALARM_2_TO_0_MASK  GENMASK(2, 0)
0134 #define AMS_ISR0_ALARM_6_TO_3_MASK  GENMASK(6, 3)
0135 #define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8)
0136 #define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1)
0137 #define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8)
0138 #define AMS_CONF1_ALARM_12_TO_7_MASK    GENMASK(5, 0)
0139 #define AMS_REGCFG1_ALARM_MASK  \
0140     (AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0))
0141 #define AMS_REGCFG3_ALARM_MASK      AMS_CONF1_ALARM_12_TO_7_MASK
0142 
0143 #define AMS_PS_CSTS_PS_READY        (BIT(27) | BIT(16))
0144 #define AMS_PL_CSTS_ACCESS_MASK     BIT(1)
0145 
0146 #define AMS_PL_MAX_FIXED_CHANNEL    10
0147 #define AMS_PL_MAX_EXT_CHANNEL      20
0148 
0149 #define AMS_INIT_POLL_TIME_US       200
0150 #define AMS_INIT_TIMEOUT_US     10000
0151 #define AMS_UNMASK_TIMEOUT_MS       500
0152 
0153 /*
0154  * Following scale and offset value is derived from
0155  * UG580 (v1.7) December 20, 2016
0156  */
0157 #define AMS_SUPPLY_SCALE_1VOLT_mV       1000
0158 #define AMS_SUPPLY_SCALE_3VOLT_mV       3000
0159 #define AMS_SUPPLY_SCALE_6VOLT_mV       6000
0160 #define AMS_SUPPLY_SCALE_DIV_BIT    16
0161 
0162 #define AMS_TEMP_SCALE          509314
0163 #define AMS_TEMP_SCALE_DIV_BIT      16
0164 #define AMS_TEMP_OFFSET         -((280230LL << 16) / 509314)
0165 
0166 enum ams_alarm_bit {
0167     AMS_ALARM_BIT_TEMP = 0,
0168     AMS_ALARM_BIT_SUPPLY1 = 1,
0169     AMS_ALARM_BIT_SUPPLY2 = 2,
0170     AMS_ALARM_BIT_SUPPLY3 = 3,
0171     AMS_ALARM_BIT_SUPPLY4 = 4,
0172     AMS_ALARM_BIT_SUPPLY5 = 5,
0173     AMS_ALARM_BIT_SUPPLY6 = 6,
0174     AMS_ALARM_BIT_RESERVED = 7,
0175     AMS_ALARM_BIT_SUPPLY7 = 8,
0176     AMS_ALARM_BIT_SUPPLY8 = 9,
0177     AMS_ALARM_BIT_SUPPLY9 = 10,
0178     AMS_ALARM_BIT_SUPPLY10 = 11,
0179     AMS_ALARM_BIT_VCCAMS = 12,
0180     AMS_ALARM_BIT_TEMP_REMOTE = 13,
0181 };
0182 
0183 enum ams_seq {
0184     AMS_SEQ_VCC_PSPLL = 0,
0185     AMS_SEQ_VCC_PSBATT = 1,
0186     AMS_SEQ_VCCINT = 2,
0187     AMS_SEQ_VCCBRAM = 3,
0188     AMS_SEQ_VCCAUX = 4,
0189     AMS_SEQ_PSDDRPLL = 5,
0190     AMS_SEQ_INTDDR = 6,
0191 };
0192 
0193 enum ams_ps_pl_seq {
0194     AMS_SEQ_CALIB = 0,
0195     AMS_SEQ_RSVD_1 = 1,
0196     AMS_SEQ_RSVD_2 = 2,
0197     AMS_SEQ_TEST = 3,
0198     AMS_SEQ_RSVD_4 = 4,
0199     AMS_SEQ_SUPPLY4 = 5,
0200     AMS_SEQ_SUPPLY5 = 6,
0201     AMS_SEQ_SUPPLY6 = 7,
0202     AMS_SEQ_TEMP = 8,
0203     AMS_SEQ_SUPPLY2 = 9,
0204     AMS_SEQ_SUPPLY1 = 10,
0205     AMS_SEQ_VP_VN = 11,
0206     AMS_SEQ_VREFP = 12,
0207     AMS_SEQ_VREFN = 13,
0208     AMS_SEQ_SUPPLY3 = 14,
0209     AMS_SEQ_CURRENT_MON = 15,
0210     AMS_SEQ_SUPPLY7 = 16,
0211     AMS_SEQ_SUPPLY8 = 17,
0212     AMS_SEQ_SUPPLY9 = 18,
0213     AMS_SEQ_SUPPLY10 = 19,
0214     AMS_SEQ_VCCAMS = 20,
0215     AMS_SEQ_TEMP_REMOTE = 21,
0216     AMS_SEQ_MAX = 22
0217 };
0218 
0219 #define AMS_PS_SEQ_MAX      AMS_SEQ_MAX
0220 #define AMS_SEQ(x)      (AMS_SEQ_MAX + (x))
0221 #define PS_SEQ(x)       (x)
0222 #define PL_SEQ(x)       (AMS_PS_SEQ_MAX + (x))
0223 #define AMS_CTRL_SEQ_BASE   (AMS_PS_SEQ_MAX * 3)
0224 
0225 #define AMS_CHAN_TEMP(_scan_index, _addr) { \
0226     .type = IIO_TEMP, \
0227     .indexed = 1, \
0228     .address = (_addr), \
0229     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0230         BIT(IIO_CHAN_INFO_SCALE) | \
0231         BIT(IIO_CHAN_INFO_OFFSET), \
0232     .event_spec = ams_temp_events, \
0233     .scan_index = _scan_index, \
0234     .num_event_specs = ARRAY_SIZE(ams_temp_events), \
0235 }
0236 
0237 #define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm) { \
0238     .type = IIO_VOLTAGE, \
0239     .indexed = 1, \
0240     .address = (_addr), \
0241     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0242         BIT(IIO_CHAN_INFO_SCALE), \
0243     .event_spec = (_alarm) ? ams_voltage_events : NULL, \
0244     .scan_index = _scan_index, \
0245     .num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \
0246 }
0247 
0248 #define AMS_PS_CHAN_TEMP(_scan_index, _addr) \
0249     AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr)
0250 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr) \
0251     AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true)
0252 
0253 #define AMS_PL_CHAN_TEMP(_scan_index, _addr) \
0254     AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr)
0255 #define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm) \
0256     AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm)
0257 #define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \
0258     AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false)
0259 #define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr) \
0260     AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false)
0261 
0262 /**
0263  * struct ams - This structure contains necessary state for xilinx-ams to operate
0264  * @base: physical base address of device
0265  * @ps_base: physical base address of PS device
0266  * @pl_base: physical base address of PL device
0267  * @clk: clocks associated with the device
0268  * @dev: pointer to device struct
0269  * @lock: to handle multiple user interaction
0270  * @intr_lock: to protect interrupt mask values
0271  * @alarm_mask: alarm configuration
0272  * @current_masked_alarm: currently masked due to alarm
0273  * @intr_mask: interrupt configuration
0274  * @ams_unmask_work: re-enables event once the event condition disappears
0275  *
0276  */
0277 struct ams {
0278     void __iomem *base;
0279     void __iomem *ps_base;
0280     void __iomem *pl_base;
0281     struct clk *clk;
0282     struct device *dev;
0283     struct mutex lock;
0284     spinlock_t intr_lock;
0285     unsigned int alarm_mask;
0286     unsigned int current_masked_alarm;
0287     u64 intr_mask;
0288     struct delayed_work ams_unmask_work;
0289 };
0290 
0291 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset,
0292                      u32 mask, u32 data)
0293 {
0294     u32 val, regval;
0295 
0296     val = readl(ams->ps_base + offset);
0297     regval = (val & ~mask) | (data & mask);
0298     writel(regval, ams->ps_base + offset);
0299 }
0300 
0301 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset,
0302                      u32 mask, u32 data)
0303 {
0304     u32 val, regval;
0305 
0306     val = readl(ams->pl_base + offset);
0307     regval = (val & ~mask) | (data & mask);
0308     writel(regval, ams->pl_base + offset);
0309 }
0310 
0311 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
0312 {
0313     u32 regval;
0314 
0315     ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask);
0316 
0317     regval = ~(ams->intr_mask | ams->current_masked_alarm);
0318     writel(regval, ams->base + AMS_IER_0);
0319 
0320     regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));
0321     writel(regval, ams->base + AMS_IER_1);
0322 
0323     regval = ams->intr_mask | ams->current_masked_alarm;
0324     writel(regval, ams->base + AMS_IDR_0);
0325 
0326     regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);
0327     writel(regval, ams->base + AMS_IDR_1);
0328 }
0329 
0330 static void ams_disable_all_alarms(struct ams *ams)
0331 {
0332     /* disable PS module alarm */
0333     if (ams->ps_base) {
0334         ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
0335                   AMS_REGCFG1_ALARM_MASK);
0336         ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
0337                   AMS_REGCFG3_ALARM_MASK);
0338     }
0339 
0340     /* disable PL module alarm */
0341     if (ams->pl_base) {
0342         ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
0343                   AMS_REGCFG1_ALARM_MASK);
0344         ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
0345                   AMS_REGCFG3_ALARM_MASK);
0346     }
0347 }
0348 
0349 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask)
0350 {
0351     u32 cfg;
0352     u32 val;
0353 
0354     val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask);
0355     cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
0356 
0357     val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask);
0358     cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
0359 
0360     ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
0361 
0362     val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask);
0363     cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
0364     ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
0365 }
0366 
0367 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask)
0368 {
0369     unsigned long pl_alarm_mask;
0370     u32 cfg;
0371     u32 val;
0372 
0373     pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask);
0374 
0375     val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask);
0376     cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
0377 
0378     val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask);
0379     cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
0380 
0381     ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
0382 
0383     val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask);
0384     cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
0385     ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
0386 }
0387 
0388 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask)
0389 {
0390     unsigned long flags;
0391 
0392     if (ams->ps_base)
0393         ams_update_ps_alarm(ams, alarm_mask);
0394 
0395     if (ams->pl_base)
0396         ams_update_pl_alarm(ams, alarm_mask);
0397 
0398     spin_lock_irqsave(&ams->intr_lock, flags);
0399     ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask);
0400     spin_unlock_irqrestore(&ams->intr_lock, flags);
0401 }
0402 
0403 static void ams_enable_channel_sequence(struct iio_dev *indio_dev)
0404 {
0405     struct ams *ams = iio_priv(indio_dev);
0406     unsigned long long scan_mask;
0407     int i;
0408     u32 regval;
0409 
0410     /*
0411      * Enable channel sequence. First 22 bits of scan_mask represent
0412      * PS channels, and next remaining bits represent PL channels.
0413      */
0414 
0415     /* Run calibration of PS & PL as part of the sequence */
0416     scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX);
0417     for (i = 0; i < indio_dev->num_channels; i++)
0418         scan_mask |= BIT_ULL(indio_dev->channels[i].scan_index);
0419 
0420     if (ams->ps_base) {
0421         /* put sysmon in a soft reset to change the sequence */
0422         ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0423                   AMS_CONF1_SEQ_DEFAULT);
0424 
0425         /* configure basic channels */
0426         regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
0427         writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);
0428 
0429         regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
0430         writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);
0431 
0432         /* set continuous sequence mode */
0433         ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0434                   AMS_CONF1_SEQ_CONTINUOUS);
0435     }
0436 
0437     if (ams->pl_base) {
0438         /* put sysmon in a soft reset to change the sequence */
0439         ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0440                   AMS_CONF1_SEQ_DEFAULT);
0441 
0442         /* configure basic channels */
0443         scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask);
0444 
0445         regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
0446         writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);
0447 
0448         regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask);
0449         writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);
0450 
0451         regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
0452         writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);
0453 
0454         /* set continuous sequence mode */
0455         ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0456                   AMS_CONF1_SEQ_CONTINUOUS);
0457     }
0458 }
0459 
0460 static int ams_init_device(struct ams *ams)
0461 {
0462     u32 expect = AMS_PS_CSTS_PS_READY;
0463     u32 reg, value;
0464     int ret;
0465 
0466     /* reset AMS */
0467     if (ams->ps_base) {
0468         writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN);
0469 
0470         ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect),
0471                      AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
0472         if (ret)
0473             return ret;
0474 
0475         /* put sysmon in a default state */
0476         ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0477                   AMS_CONF1_SEQ_DEFAULT);
0478     }
0479 
0480     if (ams->pl_base) {
0481         value = readl(ams->base + AMS_PL_CSTS);
0482         if (value == 0)
0483             return 0;
0484 
0485         writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN);
0486 
0487         /* put sysmon in a default state */
0488         ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0489                   AMS_CONF1_SEQ_DEFAULT);
0490     }
0491 
0492     ams_disable_all_alarms(ams);
0493 
0494     /* Disable interrupt */
0495     ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK);
0496 
0497     /* Clear any pending interrupt */
0498     writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0);
0499     writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1);
0500 
0501     return 0;
0502 }
0503 
0504 static int ams_enable_single_channel(struct ams *ams, unsigned int offset)
0505 {
0506     u8 channel_num;
0507 
0508     switch (offset) {
0509     case AMS_VCC_PSPLL0:
0510         channel_num = AMS_VCC_PSPLL0_CH;
0511         break;
0512     case AMS_VCC_PSPLL3:
0513         channel_num = AMS_VCC_PSPLL3_CH;
0514         break;
0515     case AMS_VCCINT:
0516         channel_num = AMS_VCCINT_CH;
0517         break;
0518     case AMS_VCCBRAM:
0519         channel_num = AMS_VCCBRAM_CH;
0520         break;
0521     case AMS_VCCAUX:
0522         channel_num = AMS_VCCAUX_CH;
0523         break;
0524     case AMS_PSDDRPLL:
0525         channel_num = AMS_PSDDRPLL_CH;
0526         break;
0527     case AMS_PSINTFPDDR:
0528         channel_num = AMS_PSINTFPDDR_CH;
0529         break;
0530     default:
0531         return -EINVAL;
0532     }
0533 
0534     /* put sysmon in a soft reset to change the sequence */
0535     ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0536               AMS_CONF1_SEQ_DEFAULT);
0537 
0538     /* write the channel number */
0539     ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK,
0540               channel_num);
0541 
0542     /* set single channel, sequencer off mode */
0543     ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
0544               AMS_CONF1_SEQ_SINGLE_CHANNEL);
0545 
0546     return 0;
0547 }
0548 
0549 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data)
0550 {
0551     u32 expect = AMS_ISR1_EOC_MASK;
0552     u32 reg;
0553     int ret;
0554 
0555     ret = ams_enable_single_channel(ams, offset);
0556     if (ret)
0557         return ret;
0558 
0559     /* clear end-of-conversion flag, wait for next conversion to complete */
0560     writel(expect, ams->base + AMS_ISR_1);
0561     ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect),
0562                  AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
0563     if (ret)
0564         return ret;
0565 
0566     *data = readl(ams->base + offset);
0567 
0568     return 0;
0569 }
0570 
0571 static int ams_get_ps_scale(int address)
0572 {
0573     int val;
0574 
0575     switch (address) {
0576     case AMS_SUPPLY1:
0577     case AMS_SUPPLY2:
0578     case AMS_SUPPLY3:
0579     case AMS_SUPPLY4:
0580     case AMS_SUPPLY9:
0581     case AMS_SUPPLY10:
0582     case AMS_VCCAMS:
0583         val = AMS_SUPPLY_SCALE_3VOLT_mV;
0584         break;
0585     case AMS_SUPPLY5:
0586     case AMS_SUPPLY6:
0587     case AMS_SUPPLY7:
0588     case AMS_SUPPLY8:
0589         val = AMS_SUPPLY_SCALE_6VOLT_mV;
0590         break;
0591     default:
0592         val = AMS_SUPPLY_SCALE_1VOLT_mV;
0593         break;
0594     }
0595 
0596     return val;
0597 }
0598 
0599 static int ams_get_pl_scale(struct ams *ams, int address)
0600 {
0601     int val, regval;
0602 
0603     switch (address) {
0604     case AMS_SUPPLY1:
0605     case AMS_SUPPLY2:
0606     case AMS_SUPPLY3:
0607     case AMS_SUPPLY4:
0608     case AMS_SUPPLY5:
0609     case AMS_SUPPLY6:
0610     case AMS_VCCAMS:
0611     case AMS_VREFP:
0612     case AMS_VREFN:
0613         val = AMS_SUPPLY_SCALE_3VOLT_mV;
0614         break;
0615     case AMS_SUPPLY7:
0616         regval = readl(ams->pl_base + AMS_REG_CONFIG4);
0617         if (FIELD_GET(AMS_VUSER0_MASK, regval))
0618             val = AMS_SUPPLY_SCALE_6VOLT_mV;
0619         else
0620             val = AMS_SUPPLY_SCALE_3VOLT_mV;
0621         break;
0622     case AMS_SUPPLY8:
0623         regval = readl(ams->pl_base + AMS_REG_CONFIG4);
0624         if (FIELD_GET(AMS_VUSER1_MASK, regval))
0625             val = AMS_SUPPLY_SCALE_6VOLT_mV;
0626         else
0627             val = AMS_SUPPLY_SCALE_3VOLT_mV;
0628         break;
0629     case AMS_SUPPLY9:
0630         regval = readl(ams->pl_base + AMS_REG_CONFIG4);
0631         if (FIELD_GET(AMS_VUSER2_MASK, regval))
0632             val = AMS_SUPPLY_SCALE_6VOLT_mV;
0633         else
0634             val = AMS_SUPPLY_SCALE_3VOLT_mV;
0635         break;
0636     case AMS_SUPPLY10:
0637         regval = readl(ams->pl_base + AMS_REG_CONFIG4);
0638         if (FIELD_GET(AMS_VUSER3_MASK, regval))
0639             val = AMS_SUPPLY_SCALE_6VOLT_mV;
0640         else
0641             val = AMS_SUPPLY_SCALE_3VOLT_mV;
0642         break;
0643     case AMS_VP_VN:
0644     case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15):
0645         val = AMS_SUPPLY_SCALE_1VOLT_mV;
0646         break;
0647     default:
0648         val = AMS_SUPPLY_SCALE_1VOLT_mV;
0649         break;
0650     }
0651 
0652     return val;
0653 }
0654 
0655 static int ams_get_ctrl_scale(int address)
0656 {
0657     int val;
0658 
0659     switch (address) {
0660     case AMS_VCC_PSPLL0:
0661     case AMS_VCC_PSPLL3:
0662     case AMS_VCCINT:
0663     case AMS_VCCBRAM:
0664     case AMS_VCCAUX:
0665     case AMS_PSDDRPLL:
0666     case AMS_PSINTFPDDR:
0667         val = AMS_SUPPLY_SCALE_3VOLT_mV;
0668         break;
0669     default:
0670         val = AMS_SUPPLY_SCALE_1VOLT_mV;
0671         break;
0672     }
0673 
0674     return val;
0675 }
0676 
0677 static int ams_read_raw(struct iio_dev *indio_dev,
0678             struct iio_chan_spec const *chan,
0679             int *val, int *val2, long mask)
0680 {
0681     struct ams *ams = iio_priv(indio_dev);
0682     int ret;
0683 
0684     switch (mask) {
0685     case IIO_CHAN_INFO_RAW:
0686         mutex_lock(&ams->lock);
0687         if (chan->scan_index >= AMS_CTRL_SEQ_BASE) {
0688             ret = ams_read_vcc_reg(ams, chan->address, val);
0689             if (ret)
0690                 goto unlock_mutex;
0691             ams_enable_channel_sequence(indio_dev);
0692         } else if (chan->scan_index >= AMS_PS_SEQ_MAX)
0693             *val = readl(ams->pl_base + chan->address);
0694         else
0695             *val = readl(ams->ps_base + chan->address);
0696 
0697         ret = IIO_VAL_INT;
0698 unlock_mutex:
0699         mutex_unlock(&ams->lock);
0700         return ret;
0701     case IIO_CHAN_INFO_SCALE:
0702         switch (chan->type) {
0703         case IIO_VOLTAGE:
0704             if (chan->scan_index < AMS_PS_SEQ_MAX)
0705                 *val = ams_get_ps_scale(chan->address);
0706             else if (chan->scan_index >= AMS_PS_SEQ_MAX &&
0707                  chan->scan_index < AMS_CTRL_SEQ_BASE)
0708                 *val = ams_get_pl_scale(ams, chan->address);
0709             else
0710                 *val = ams_get_ctrl_scale(chan->address);
0711 
0712             *val2 = AMS_SUPPLY_SCALE_DIV_BIT;
0713             return IIO_VAL_FRACTIONAL_LOG2;
0714         case IIO_TEMP:
0715             *val = AMS_TEMP_SCALE;
0716             *val2 = AMS_TEMP_SCALE_DIV_BIT;
0717             return IIO_VAL_FRACTIONAL_LOG2;
0718         default:
0719             return -EINVAL;
0720         }
0721     case IIO_CHAN_INFO_OFFSET:
0722         /* Only the temperature channel has an offset */
0723         *val = AMS_TEMP_OFFSET;
0724         return IIO_VAL_INT;
0725     default:
0726         return -EINVAL;
0727     }
0728 }
0729 
0730 static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir)
0731 {
0732     int offset;
0733 
0734     if (scan_index >= AMS_PS_SEQ_MAX)
0735         scan_index -= AMS_PS_SEQ_MAX;
0736 
0737     if (dir == IIO_EV_DIR_FALLING) {
0738         if (scan_index < AMS_SEQ_SUPPLY7)
0739             offset = AMS_ALARM_THRESHOLD_OFF_10;
0740         else
0741             offset = AMS_ALARM_THRESHOLD_OFF_20;
0742     } else {
0743         offset = 0;
0744     }
0745 
0746     switch (scan_index) {
0747     case AMS_SEQ_TEMP:
0748         return AMS_ALARM_TEMP + offset;
0749     case AMS_SEQ_SUPPLY1:
0750         return AMS_ALARM_SUPPLY1 + offset;
0751     case AMS_SEQ_SUPPLY2:
0752         return AMS_ALARM_SUPPLY2 + offset;
0753     case AMS_SEQ_SUPPLY3:
0754         return AMS_ALARM_SUPPLY3 + offset;
0755     case AMS_SEQ_SUPPLY4:
0756         return AMS_ALARM_SUPPLY4 + offset;
0757     case AMS_SEQ_SUPPLY5:
0758         return AMS_ALARM_SUPPLY5 + offset;
0759     case AMS_SEQ_SUPPLY6:
0760         return AMS_ALARM_SUPPLY6 + offset;
0761     case AMS_SEQ_SUPPLY7:
0762         return AMS_ALARM_SUPPLY7 + offset;
0763     case AMS_SEQ_SUPPLY8:
0764         return AMS_ALARM_SUPPLY8 + offset;
0765     case AMS_SEQ_SUPPLY9:
0766         return AMS_ALARM_SUPPLY9 + offset;
0767     case AMS_SEQ_SUPPLY10:
0768         return AMS_ALARM_SUPPLY10 + offset;
0769     case AMS_SEQ_VCCAMS:
0770         return AMS_ALARM_VCCAMS + offset;
0771     case AMS_SEQ_TEMP_REMOTE:
0772         return AMS_ALARM_TEMP_REMOTE + offset;
0773     default:
0774         return 0;
0775     }
0776 }
0777 
0778 static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev,
0779                             u32 event)
0780 {
0781     int scan_index = 0, i;
0782 
0783     if (event >= AMS_PL_ALARM_START) {
0784         event -= AMS_PL_ALARM_START;
0785         scan_index = AMS_PS_SEQ_MAX;
0786     }
0787 
0788     switch (event) {
0789     case AMS_ALARM_BIT_TEMP:
0790         scan_index += AMS_SEQ_TEMP;
0791         break;
0792     case AMS_ALARM_BIT_SUPPLY1:
0793         scan_index += AMS_SEQ_SUPPLY1;
0794         break;
0795     case AMS_ALARM_BIT_SUPPLY2:
0796         scan_index += AMS_SEQ_SUPPLY2;
0797         break;
0798     case AMS_ALARM_BIT_SUPPLY3:
0799         scan_index += AMS_SEQ_SUPPLY3;
0800         break;
0801     case AMS_ALARM_BIT_SUPPLY4:
0802         scan_index += AMS_SEQ_SUPPLY4;
0803         break;
0804     case AMS_ALARM_BIT_SUPPLY5:
0805         scan_index += AMS_SEQ_SUPPLY5;
0806         break;
0807     case AMS_ALARM_BIT_SUPPLY6:
0808         scan_index += AMS_SEQ_SUPPLY6;
0809         break;
0810     case AMS_ALARM_BIT_SUPPLY7:
0811         scan_index += AMS_SEQ_SUPPLY7;
0812         break;
0813     case AMS_ALARM_BIT_SUPPLY8:
0814         scan_index += AMS_SEQ_SUPPLY8;
0815         break;
0816     case AMS_ALARM_BIT_SUPPLY9:
0817         scan_index += AMS_SEQ_SUPPLY9;
0818         break;
0819     case AMS_ALARM_BIT_SUPPLY10:
0820         scan_index += AMS_SEQ_SUPPLY10;
0821         break;
0822     case AMS_ALARM_BIT_VCCAMS:
0823         scan_index += AMS_SEQ_VCCAMS;
0824         break;
0825     case AMS_ALARM_BIT_TEMP_REMOTE:
0826         scan_index += AMS_SEQ_TEMP_REMOTE;
0827         break;
0828     default:
0829         break;
0830     }
0831 
0832     for (i = 0; i < dev->num_channels; i++)
0833         if (dev->channels[i].scan_index == scan_index)
0834             break;
0835 
0836     return &dev->channels[i];
0837 }
0838 
0839 static int ams_get_alarm_mask(int scan_index)
0840 {
0841     int bit = 0;
0842 
0843     if (scan_index >= AMS_PS_SEQ_MAX) {
0844         bit = AMS_PL_ALARM_START;
0845         scan_index -= AMS_PS_SEQ_MAX;
0846     }
0847 
0848     switch (scan_index) {
0849     case AMS_SEQ_TEMP:
0850         return BIT(AMS_ALARM_BIT_TEMP + bit);
0851     case AMS_SEQ_SUPPLY1:
0852         return BIT(AMS_ALARM_BIT_SUPPLY1 + bit);
0853     case AMS_SEQ_SUPPLY2:
0854         return BIT(AMS_ALARM_BIT_SUPPLY2 + bit);
0855     case AMS_SEQ_SUPPLY3:
0856         return BIT(AMS_ALARM_BIT_SUPPLY3 + bit);
0857     case AMS_SEQ_SUPPLY4:
0858         return BIT(AMS_ALARM_BIT_SUPPLY4 + bit);
0859     case AMS_SEQ_SUPPLY5:
0860         return BIT(AMS_ALARM_BIT_SUPPLY5 + bit);
0861     case AMS_SEQ_SUPPLY6:
0862         return BIT(AMS_ALARM_BIT_SUPPLY6 + bit);
0863     case AMS_SEQ_SUPPLY7:
0864         return BIT(AMS_ALARM_BIT_SUPPLY7 + bit);
0865     case AMS_SEQ_SUPPLY8:
0866         return BIT(AMS_ALARM_BIT_SUPPLY8 + bit);
0867     case AMS_SEQ_SUPPLY9:
0868         return BIT(AMS_ALARM_BIT_SUPPLY9 + bit);
0869     case AMS_SEQ_SUPPLY10:
0870         return BIT(AMS_ALARM_BIT_SUPPLY10 + bit);
0871     case AMS_SEQ_VCCAMS:
0872         return BIT(AMS_ALARM_BIT_VCCAMS + bit);
0873     case AMS_SEQ_TEMP_REMOTE:
0874         return BIT(AMS_ALARM_BIT_TEMP_REMOTE + bit);
0875     default:
0876         return 0;
0877     }
0878 }
0879 
0880 static int ams_read_event_config(struct iio_dev *indio_dev,
0881                  const struct iio_chan_spec *chan,
0882                  enum iio_event_type type,
0883                  enum iio_event_direction dir)
0884 {
0885     struct ams *ams = iio_priv(indio_dev);
0886 
0887     return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index));
0888 }
0889 
0890 static int ams_write_event_config(struct iio_dev *indio_dev,
0891                   const struct iio_chan_spec *chan,
0892                   enum iio_event_type type,
0893                   enum iio_event_direction dir,
0894                   int state)
0895 {
0896     struct ams *ams = iio_priv(indio_dev);
0897     unsigned int alarm;
0898 
0899     alarm = ams_get_alarm_mask(chan->scan_index);
0900 
0901     mutex_lock(&ams->lock);
0902 
0903     if (state)
0904         ams->alarm_mask |= alarm;
0905     else
0906         ams->alarm_mask &= ~alarm;
0907 
0908     ams_update_alarm(ams, ams->alarm_mask);
0909 
0910     mutex_unlock(&ams->lock);
0911 
0912     return 0;
0913 }
0914 
0915 static int ams_read_event_value(struct iio_dev *indio_dev,
0916                 const struct iio_chan_spec *chan,
0917                 enum iio_event_type type,
0918                 enum iio_event_direction dir,
0919                 enum iio_event_info info, int *val, int *val2)
0920 {
0921     struct ams *ams = iio_priv(indio_dev);
0922     unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir);
0923 
0924     mutex_lock(&ams->lock);
0925 
0926     if (chan->scan_index >= AMS_PS_SEQ_MAX)
0927         *val = readl(ams->pl_base + offset);
0928     else
0929         *val = readl(ams->ps_base + offset);
0930 
0931     mutex_unlock(&ams->lock);
0932 
0933     return IIO_VAL_INT;
0934 }
0935 
0936 static int ams_write_event_value(struct iio_dev *indio_dev,
0937                  const struct iio_chan_spec *chan,
0938                  enum iio_event_type type,
0939                  enum iio_event_direction dir,
0940                  enum iio_event_info info, int val, int val2)
0941 {
0942     struct ams *ams = iio_priv(indio_dev);
0943     unsigned int offset;
0944 
0945     mutex_lock(&ams->lock);
0946 
0947     /* Set temperature channel threshold to direct threshold */
0948     if (chan->type == IIO_TEMP) {
0949         offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING);
0950 
0951         if (chan->scan_index >= AMS_PS_SEQ_MAX)
0952             ams_pl_update_reg(ams, offset,
0953                       AMS_ALARM_THR_DIRECT_MASK,
0954                       AMS_ALARM_THR_DIRECT_MASK);
0955         else
0956             ams_ps_update_reg(ams, offset,
0957                       AMS_ALARM_THR_DIRECT_MASK,
0958                       AMS_ALARM_THR_DIRECT_MASK);
0959     }
0960 
0961     offset = ams_get_alarm_offset(chan->scan_index, dir);
0962     if (chan->scan_index >= AMS_PS_SEQ_MAX)
0963         writel(val, ams->pl_base + offset);
0964     else
0965         writel(val, ams->ps_base + offset);
0966 
0967     mutex_unlock(&ams->lock);
0968 
0969     return 0;
0970 }
0971 
0972 static void ams_handle_event(struct iio_dev *indio_dev, u32 event)
0973 {
0974     const struct iio_chan_spec *chan;
0975 
0976     chan = ams_event_to_channel(indio_dev, event);
0977 
0978     if (chan->type == IIO_TEMP) {
0979         /*
0980          * The temperature channel only supports over-temperature
0981          * events.
0982          */
0983         iio_push_event(indio_dev,
0984                    IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
0985                             IIO_EV_TYPE_THRESH,
0986                             IIO_EV_DIR_RISING),
0987                    iio_get_time_ns(indio_dev));
0988     } else {
0989         /*
0990          * For other channels we don't know whether it is a upper or
0991          * lower threshold event. Userspace will have to check the
0992          * channel value if it wants to know.
0993          */
0994         iio_push_event(indio_dev,
0995                    IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
0996                             IIO_EV_TYPE_THRESH,
0997                             IIO_EV_DIR_EITHER),
0998                    iio_get_time_ns(indio_dev));
0999     }
1000 }
1001 
1002 static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events)
1003 {
1004     unsigned int bit;
1005 
1006     for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS)
1007         ams_handle_event(indio_dev, bit);
1008 }
1009 
1010 /**
1011  * ams_unmask_worker - ams alarm interrupt unmask worker
1012  * @work: work to be done
1013  *
1014  * The ZynqMP threshold interrupts are level sensitive. Since we can't make the
1015  * threshold condition go way from within the interrupt handler, this means as
1016  * soon as a threshold condition is present we would enter the interrupt handler
1017  * again and again. To work around this we mask all active threshold interrupts
1018  * in the interrupt handler and start a timer. In this timer we poll the
1019  * interrupt status and only if the interrupt is inactive we unmask it again.
1020  */
1021 static void ams_unmask_worker(struct work_struct *work)
1022 {
1023     struct ams *ams = container_of(work, struct ams, ams_unmask_work.work);
1024     unsigned int status, unmask;
1025 
1026     spin_lock_irq(&ams->intr_lock);
1027 
1028     status = readl(ams->base + AMS_ISR_0);
1029 
1030     /* Clear those bits which are not active anymore */
1031     unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm;
1032 
1033     /* Clear status of disabled alarm */
1034     unmask |= ams->intr_mask;
1035 
1036     ams->current_masked_alarm &= status;
1037 
1038     /* Also clear those which are masked out anyway */
1039     ams->current_masked_alarm &= ~ams->intr_mask;
1040 
1041     /* Clear the interrupts before we unmask them */
1042     writel(unmask, ams->base + AMS_ISR_0);
1043 
1044     ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1045 
1046     spin_unlock_irq(&ams->intr_lock);
1047 
1048     /* If still pending some alarm re-trigger the timer */
1049     if (ams->current_masked_alarm)
1050         schedule_delayed_work(&ams->ams_unmask_work,
1051                       msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1052 }
1053 
1054 static irqreturn_t ams_irq(int irq, void *data)
1055 {
1056     struct iio_dev *indio_dev = data;
1057     struct ams *ams = iio_priv(indio_dev);
1058     u32 isr0;
1059 
1060     spin_lock(&ams->intr_lock);
1061 
1062     isr0 = readl(ams->base + AMS_ISR_0);
1063 
1064     /* Only process alarms that are not masked */
1065     isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm);
1066     if (!isr0) {
1067         spin_unlock(&ams->intr_lock);
1068         return IRQ_NONE;
1069     }
1070 
1071     /* Clear interrupt */
1072     writel(isr0, ams->base + AMS_ISR_0);
1073 
1074     /* Mask the alarm interrupts until cleared */
1075     ams->current_masked_alarm |= isr0;
1076     ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1077 
1078     ams_handle_events(indio_dev, isr0);
1079 
1080     schedule_delayed_work(&ams->ams_unmask_work,
1081                   msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1082 
1083     spin_unlock(&ams->intr_lock);
1084 
1085     return IRQ_HANDLED;
1086 }
1087 
1088 static const struct iio_event_spec ams_temp_events[] = {
1089     {
1090         .type = IIO_EV_TYPE_THRESH,
1091         .dir = IIO_EV_DIR_RISING,
1092         .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
1093     },
1094 };
1095 
1096 static const struct iio_event_spec ams_voltage_events[] = {
1097     {
1098         .type = IIO_EV_TYPE_THRESH,
1099         .dir = IIO_EV_DIR_RISING,
1100         .mask_separate = BIT(IIO_EV_INFO_VALUE),
1101     },
1102     {
1103         .type = IIO_EV_TYPE_THRESH,
1104         .dir = IIO_EV_DIR_FALLING,
1105         .mask_separate = BIT(IIO_EV_INFO_VALUE),
1106     },
1107     {
1108         .type = IIO_EV_TYPE_THRESH,
1109         .dir = IIO_EV_DIR_EITHER,
1110         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1111     },
1112 };
1113 
1114 static const struct iio_chan_spec ams_ps_channels[] = {
1115     AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP),
1116     AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE),
1117     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1),
1118     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2),
1119     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3),
1120     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4),
1121     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5),
1122     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6),
1123     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7),
1124     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8),
1125     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9),
1126     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10),
1127     AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS),
1128 };
1129 
1130 static const struct iio_chan_spec ams_pl_channels[] = {
1131     AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP),
1132     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true),
1133     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true),
1134     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false),
1135     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false),
1136     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true),
1137     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true),
1138     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true),
1139     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true),
1140     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true),
1141     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false),
1142     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true),
1143     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true),
1144     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true),
1145     AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true),
1146     AMS_PL_AUX_CHAN_VOLTAGE(0),
1147     AMS_PL_AUX_CHAN_VOLTAGE(1),
1148     AMS_PL_AUX_CHAN_VOLTAGE(2),
1149     AMS_PL_AUX_CHAN_VOLTAGE(3),
1150     AMS_PL_AUX_CHAN_VOLTAGE(4),
1151     AMS_PL_AUX_CHAN_VOLTAGE(5),
1152     AMS_PL_AUX_CHAN_VOLTAGE(6),
1153     AMS_PL_AUX_CHAN_VOLTAGE(7),
1154     AMS_PL_AUX_CHAN_VOLTAGE(8),
1155     AMS_PL_AUX_CHAN_VOLTAGE(9),
1156     AMS_PL_AUX_CHAN_VOLTAGE(10),
1157     AMS_PL_AUX_CHAN_VOLTAGE(11),
1158     AMS_PL_AUX_CHAN_VOLTAGE(12),
1159     AMS_PL_AUX_CHAN_VOLTAGE(13),
1160     AMS_PL_AUX_CHAN_VOLTAGE(14),
1161     AMS_PL_AUX_CHAN_VOLTAGE(15),
1162 };
1163 
1164 static const struct iio_chan_spec ams_ctrl_channels[] = {
1165     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0),
1166     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3),
1167     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT),
1168     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM),
1169     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX),
1170     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL),
1171     AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR),
1172 };
1173 
1174 static int ams_get_ext_chan(struct fwnode_handle *chan_node,
1175                 struct iio_chan_spec *channels, int num_channels)
1176 {
1177     struct iio_chan_spec *chan;
1178     struct fwnode_handle *child;
1179     unsigned int reg, ext_chan;
1180     int ret;
1181 
1182     fwnode_for_each_child_node(chan_node, child) {
1183         ret = fwnode_property_read_u32(child, "reg", &reg);
1184         if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30)
1185             continue;
1186 
1187         chan = &channels[num_channels];
1188         ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30;
1189         memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels));
1190 
1191         if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1192             chan->scan_type.sign = 's';
1193 
1194         num_channels++;
1195     }
1196 
1197     return num_channels;
1198 }
1199 
1200 static void ams_iounmap_ps(void *data)
1201 {
1202     struct ams *ams = data;
1203 
1204     iounmap(ams->ps_base);
1205 }
1206 
1207 static void ams_iounmap_pl(void *data)
1208 {
1209     struct ams *ams = data;
1210 
1211     iounmap(ams->pl_base);
1212 }
1213 
1214 static int ams_init_module(struct iio_dev *indio_dev,
1215                struct fwnode_handle *fwnode,
1216                struct iio_chan_spec *channels)
1217 {
1218     struct device *dev = indio_dev->dev.parent;
1219     struct ams *ams = iio_priv(indio_dev);
1220     int num_channels = 0;
1221     int ret;
1222 
1223     if (fwnode_property_match_string(fwnode, "compatible",
1224                      "xlnx,zynqmp-ams-ps") == 0) {
1225         ams->ps_base = fwnode_iomap(fwnode, 0);
1226         if (!ams->ps_base)
1227             return -ENXIO;
1228         ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams);
1229         if (ret < 0)
1230             return ret;
1231 
1232         /* add PS channels to iio device channels */
1233         memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels));
1234         num_channels = ARRAY_SIZE(ams_ps_channels);
1235     } else if (fwnode_property_match_string(fwnode, "compatible",
1236                         "xlnx,zynqmp-ams-pl") == 0) {
1237         ams->pl_base = fwnode_iomap(fwnode, 0);
1238         if (!ams->pl_base)
1239             return -ENXIO;
1240 
1241         ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams);
1242         if (ret < 0)
1243             return ret;
1244 
1245         /* Copy only first 10 fix channels */
1246         memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels));
1247         num_channels += AMS_PL_MAX_FIXED_CHANNEL;
1248         num_channels = ams_get_ext_chan(fwnode, channels,
1249                         num_channels);
1250     } else if (fwnode_property_match_string(fwnode, "compatible",
1251                         "xlnx,zynqmp-ams") == 0) {
1252         /* add AMS channels to iio device channels */
1253         memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels));
1254         num_channels += ARRAY_SIZE(ams_ctrl_channels);
1255     } else {
1256         return -EINVAL;
1257     }
1258 
1259     return num_channels;
1260 }
1261 
1262 static int ams_parse_firmware(struct iio_dev *indio_dev)
1263 {
1264     struct ams *ams = iio_priv(indio_dev);
1265     struct iio_chan_spec *ams_channels, *dev_channels;
1266     struct device *dev = indio_dev->dev.parent;
1267     struct fwnode_handle *child = NULL;
1268     struct fwnode_handle *fwnode = dev_fwnode(dev);
1269     size_t ams_size, dev_size;
1270     int ret, ch_cnt = 0, i, rising_off, falling_off;
1271     unsigned int num_channels = 0;
1272 
1273     ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) +
1274         ARRAY_SIZE(ams_ctrl_channels);
1275 
1276     /* Initialize buffer for channel specification */
1277     ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL);
1278     if (!ams_channels)
1279         return -ENOMEM;
1280 
1281     if (fwnode_device_is_available(fwnode)) {
1282         ret = ams_init_module(indio_dev, fwnode, ams_channels);
1283         if (ret < 0)
1284             return ret;
1285 
1286         num_channels += ret;
1287     }
1288 
1289     fwnode_for_each_child_node(fwnode, child) {
1290         if (fwnode_device_is_available(child)) {
1291             ret = ams_init_module(indio_dev, child, ams_channels + num_channels);
1292             if (ret < 0) {
1293                 fwnode_handle_put(child);
1294                 return ret;
1295             }
1296 
1297             num_channels += ret;
1298         }
1299     }
1300 
1301     for (i = 0; i < num_channels; i++) {
1302         ams_channels[i].channel = ch_cnt++;
1303 
1304         if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) {
1305             /* set threshold to max and min for each channel */
1306             falling_off =
1307                 ams_get_alarm_offset(ams_channels[i].scan_index,
1308                              IIO_EV_DIR_FALLING);
1309             rising_off =
1310                 ams_get_alarm_offset(ams_channels[i].scan_index,
1311                              IIO_EV_DIR_RISING);
1312             if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) {
1313                 writel(AMS_ALARM_THR_MIN,
1314                        ams->pl_base + falling_off);
1315                 writel(AMS_ALARM_THR_MAX,
1316                        ams->pl_base + rising_off);
1317             } else {
1318                 writel(AMS_ALARM_THR_MIN,
1319                        ams->ps_base + falling_off);
1320                 writel(AMS_ALARM_THR_MAX,
1321                        ams->ps_base + rising_off);
1322             }
1323         }
1324     }
1325 
1326     dev_size = array_size(sizeof(*dev_channels), num_channels);
1327     if (dev_size == SIZE_MAX)
1328         return -ENOMEM;
1329 
1330     dev_channels = devm_krealloc(dev, ams_channels, dev_size, GFP_KERNEL);
1331     if (!dev_channels)
1332         ret = -ENOMEM;
1333 
1334     indio_dev->channels = dev_channels;
1335     indio_dev->num_channels = num_channels;
1336 
1337     return 0;
1338 }
1339 
1340 static const struct iio_info iio_ams_info = {
1341     .read_raw = &ams_read_raw,
1342     .read_event_config = &ams_read_event_config,
1343     .write_event_config = &ams_write_event_config,
1344     .read_event_value = &ams_read_event_value,
1345     .write_event_value = &ams_write_event_value,
1346 };
1347 
1348 static const struct of_device_id ams_of_match_table[] = {
1349     { .compatible = "xlnx,zynqmp-ams" },
1350     { }
1351 };
1352 MODULE_DEVICE_TABLE(of, ams_of_match_table);
1353 
1354 static void ams_clk_disable_unprepare(void *data)
1355 {
1356     clk_disable_unprepare(data);
1357 }
1358 
1359 static int ams_probe(struct platform_device *pdev)
1360 {
1361     struct iio_dev *indio_dev;
1362     struct ams *ams;
1363     int ret;
1364     int irq;
1365 
1366     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams));
1367     if (!indio_dev)
1368         return -ENOMEM;
1369 
1370     ams = iio_priv(indio_dev);
1371     mutex_init(&ams->lock);
1372     spin_lock_init(&ams->intr_lock);
1373 
1374     indio_dev->name = "xilinx-ams";
1375 
1376     indio_dev->info = &iio_ams_info;
1377     indio_dev->modes = INDIO_DIRECT_MODE;
1378 
1379     ams->base = devm_platform_ioremap_resource(pdev, 0);
1380     if (IS_ERR(ams->base))
1381         return PTR_ERR(ams->base);
1382 
1383     ams->clk = devm_clk_get(&pdev->dev, NULL);
1384     if (IS_ERR(ams->clk))
1385         return PTR_ERR(ams->clk);
1386 
1387     ret = clk_prepare_enable(ams->clk);
1388     if (ret < 0)
1389         return ret;
1390 
1391     ret = devm_add_action_or_reset(&pdev->dev, ams_clk_disable_unprepare, ams->clk);
1392     if (ret < 0)
1393         return ret;
1394 
1395     ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work,
1396                        ams_unmask_worker);
1397     if (ret < 0)
1398         return ret;
1399 
1400     ret = ams_parse_firmware(indio_dev);
1401     if (ret)
1402         return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n");
1403 
1404     ret = ams_init_device(ams);
1405     if (ret)
1406         return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n");
1407 
1408     ams_enable_channel_sequence(indio_dev);
1409 
1410     irq = platform_get_irq(pdev, 0);
1411     if (irq < 0)
1412         return irq;
1413 
1414     ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq",
1415                    indio_dev);
1416     if (ret < 0)
1417         return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n");
1418 
1419     platform_set_drvdata(pdev, indio_dev);
1420 
1421     return devm_iio_device_register(&pdev->dev, indio_dev);
1422 }
1423 
1424 static int ams_suspend(struct device *dev)
1425 {
1426     struct ams *ams = iio_priv(dev_get_drvdata(dev));
1427 
1428     clk_disable_unprepare(ams->clk);
1429 
1430     return 0;
1431 }
1432 
1433 static int ams_resume(struct device *dev)
1434 {
1435     struct ams *ams = iio_priv(dev_get_drvdata(dev));
1436 
1437     return clk_prepare_enable(ams->clk);
1438 }
1439 
1440 static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume);
1441 
1442 static struct platform_driver ams_driver = {
1443     .probe = ams_probe,
1444     .driver = {
1445         .name = "xilinx-ams",
1446         .pm = pm_sleep_ptr(&ams_pm_ops),
1447         .of_match_table = ams_of_match_table,
1448     },
1449 };
1450 module_platform_driver(ams_driver);
1451 
1452 MODULE_LICENSE("GPL v2");
1453 MODULE_AUTHOR("Xilinx, Inc.");
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