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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale Vybrid vf610 ADC driver
0004  *
0005  * Copyright 2013 Freescale Semiconductor, Inc.
0006  */
0007 
0008 #include <linux/mod_devicetable.h>
0009 #include <linux/module.h>
0010 #include <linux/property.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/delay.h>
0014 #include <linux/kernel.h>
0015 #include <linux/slab.h>
0016 #include <linux/io.h>
0017 #include <linux/clk.h>
0018 #include <linux/completion.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/err.h>
0021 
0022 #include <linux/iio/iio.h>
0023 #include <linux/iio/buffer.h>
0024 #include <linux/iio/sysfs.h>
0025 #include <linux/iio/trigger.h>
0026 #include <linux/iio/trigger_consumer.h>
0027 #include <linux/iio/triggered_buffer.h>
0028 
0029 /* This will be the driver name the kernel reports */
0030 #define DRIVER_NAME "vf610-adc"
0031 
0032 /* Vybrid/IMX ADC registers */
0033 #define VF610_REG_ADC_HC0       0x00
0034 #define VF610_REG_ADC_HC1       0x04
0035 #define VF610_REG_ADC_HS        0x08
0036 #define VF610_REG_ADC_R0        0x0c
0037 #define VF610_REG_ADC_R1        0x10
0038 #define VF610_REG_ADC_CFG       0x14
0039 #define VF610_REG_ADC_GC        0x18
0040 #define VF610_REG_ADC_GS        0x1c
0041 #define VF610_REG_ADC_CV        0x20
0042 #define VF610_REG_ADC_OFS       0x24
0043 #define VF610_REG_ADC_CAL       0x28
0044 #define VF610_REG_ADC_PCTL      0x30
0045 
0046 /* Configuration register field define */
0047 #define VF610_ADC_MODE_BIT8     0x00
0048 #define VF610_ADC_MODE_BIT10        0x04
0049 #define VF610_ADC_MODE_BIT12        0x08
0050 #define VF610_ADC_MODE_MASK     0x0c
0051 #define VF610_ADC_BUSCLK2_SEL       0x01
0052 #define VF610_ADC_ALTCLK_SEL        0x02
0053 #define VF610_ADC_ADACK_SEL     0x03
0054 #define VF610_ADC_ADCCLK_MASK       0x03
0055 #define VF610_ADC_CLK_DIV2      0x20
0056 #define VF610_ADC_CLK_DIV4      0x40
0057 #define VF610_ADC_CLK_DIV8      0x60
0058 #define VF610_ADC_CLK_MASK      0x60
0059 #define VF610_ADC_ADLSMP_LONG       0x10
0060 #define VF610_ADC_ADSTS_SHORT   0x100
0061 #define VF610_ADC_ADSTS_NORMAL  0x200
0062 #define VF610_ADC_ADSTS_LONG    0x300
0063 #define VF610_ADC_ADSTS_MASK        0x300
0064 #define VF610_ADC_ADLPC_EN      0x80
0065 #define VF610_ADC_ADHSC_EN      0x400
0066 #define VF610_ADC_REFSEL_VALT       0x800
0067 #define VF610_ADC_REFSEL_VBG        0x1000
0068 #define VF610_ADC_ADTRG_HARD        0x2000
0069 #define VF610_ADC_AVGS_8        0x4000
0070 #define VF610_ADC_AVGS_16       0x8000
0071 #define VF610_ADC_AVGS_32       0xC000
0072 #define VF610_ADC_AVGS_MASK     0xC000
0073 #define VF610_ADC_OVWREN        0x10000
0074 
0075 /* General control register field define */
0076 #define VF610_ADC_ADACKEN       0x1
0077 #define VF610_ADC_DMAEN         0x2
0078 #define VF610_ADC_ACREN         0x4
0079 #define VF610_ADC_ACFGT         0x8
0080 #define VF610_ADC_ACFE          0x10
0081 #define VF610_ADC_AVGEN         0x20
0082 #define VF610_ADC_ADCON         0x40
0083 #define VF610_ADC_CAL           0x80
0084 
0085 /* Other field define */
0086 #define VF610_ADC_ADCHC(x)      ((x) & 0x1F)
0087 #define VF610_ADC_AIEN          (0x1 << 7)
0088 #define VF610_ADC_CONV_DISABLE      0x1F
0089 #define VF610_ADC_HS_COCO0      0x1
0090 #define VF610_ADC_CALF          0x2
0091 #define VF610_ADC_TIMEOUT       msecs_to_jiffies(100)
0092 
0093 #define DEFAULT_SAMPLE_TIME     1000
0094 
0095 /* V at 25°C of 696 mV */
0096 #define VF610_VTEMP25_3V0       950
0097 /* V at 25°C of 699 mV */
0098 #define VF610_VTEMP25_3V3       867
0099 /* Typical sensor slope coefficient at all temperatures */
0100 #define VF610_TEMP_SLOPE_COEFF      1840
0101 
0102 enum clk_sel {
0103     VF610_ADCIOC_BUSCLK_SET,
0104     VF610_ADCIOC_ALTCLK_SET,
0105     VF610_ADCIOC_ADACK_SET,
0106 };
0107 
0108 enum vol_ref {
0109     VF610_ADCIOC_VR_VREF_SET,
0110     VF610_ADCIOC_VR_VALT_SET,
0111     VF610_ADCIOC_VR_VBG_SET,
0112 };
0113 
0114 enum average_sel {
0115     VF610_ADC_SAMPLE_1,
0116     VF610_ADC_SAMPLE_4,
0117     VF610_ADC_SAMPLE_8,
0118     VF610_ADC_SAMPLE_16,
0119     VF610_ADC_SAMPLE_32,
0120 };
0121 
0122 enum conversion_mode_sel {
0123     VF610_ADC_CONV_NORMAL,
0124     VF610_ADC_CONV_HIGH_SPEED,
0125     VF610_ADC_CONV_LOW_POWER,
0126 };
0127 
0128 enum lst_adder_sel {
0129     VF610_ADCK_CYCLES_3,
0130     VF610_ADCK_CYCLES_5,
0131     VF610_ADCK_CYCLES_7,
0132     VF610_ADCK_CYCLES_9,
0133     VF610_ADCK_CYCLES_13,
0134     VF610_ADCK_CYCLES_17,
0135     VF610_ADCK_CYCLES_21,
0136     VF610_ADCK_CYCLES_25,
0137 };
0138 
0139 struct vf610_adc_feature {
0140     enum clk_sel    clk_sel;
0141     enum vol_ref    vol_ref;
0142     enum conversion_mode_sel conv_mode;
0143 
0144     int clk_div;
0145     int     sample_rate;
0146     int res_mode;
0147     u32 lst_adder_index;
0148     u32 default_sample_time;
0149 
0150     bool    calibration;
0151     bool    ovwren;
0152 };
0153 
0154 struct vf610_adc {
0155     struct device *dev;
0156     void __iomem *regs;
0157     struct clk *clk;
0158 
0159     u32 vref_uv;
0160     u32 value;
0161     struct regulator *vref;
0162 
0163     u32 max_adck_rate[3];
0164     struct vf610_adc_feature adc_feature;
0165 
0166     u32 sample_freq_avail[5];
0167 
0168     struct completion completion;
0169     /* Ensure the timestamp is naturally aligned */
0170     struct {
0171         u16 chan;
0172         s64 timestamp __aligned(8);
0173     } scan;
0174 };
0175 
0176 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
0177 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
0178 
0179 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
0180 {
0181     struct vf610_adc_feature *adc_feature = &info->adc_feature;
0182     unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
0183     u32 adck_period, lst_addr_min;
0184     int divisor, i;
0185 
0186     adck_rate = info->max_adck_rate[adc_feature->conv_mode];
0187 
0188     if (adck_rate) {
0189         /* calculate clk divider which is within specification */
0190         divisor = ipg_rate / adck_rate;
0191         adc_feature->clk_div = 1 << fls(divisor + 1);
0192     } else {
0193         /* fall-back value using a safe divisor */
0194         adc_feature->clk_div = 8;
0195     }
0196 
0197     adck_rate = ipg_rate / adc_feature->clk_div;
0198 
0199     /*
0200      * Determine the long sample time adder value to be used based
0201      * on the default minimum sample time provided.
0202      */
0203     adck_period = NSEC_PER_SEC / adck_rate;
0204     lst_addr_min = adc_feature->default_sample_time / adck_period;
0205     for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
0206         if (vf610_lst_adder[i] > lst_addr_min) {
0207             adc_feature->lst_adder_index = i;
0208             break;
0209         }
0210     }
0211 
0212     /*
0213      * Calculate ADC sample frequencies
0214      * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
0215      * which is the same as bus clock.
0216      *
0217      * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
0218      * SFCAdder: fixed to 6 ADCK cycles
0219      * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
0220      * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
0221      * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
0222      */
0223     for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
0224         info->sample_freq_avail[i] =
0225             adck_rate / (6 + vf610_hw_avgs[i] *
0226              (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
0227 }
0228 
0229 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
0230 {
0231     struct vf610_adc_feature *adc_feature = &info->adc_feature;
0232 
0233     /* set default Configuration for ADC controller */
0234     adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
0235     adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
0236 
0237     adc_feature->calibration = true;
0238     adc_feature->ovwren = true;
0239 
0240     adc_feature->res_mode = 12;
0241     adc_feature->sample_rate = 1;
0242 
0243     adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
0244 
0245     vf610_adc_calculate_rates(info);
0246 }
0247 
0248 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
0249 {
0250     struct vf610_adc_feature *adc_feature = &info->adc_feature;
0251     int cfg_data = 0;
0252     int gc_data = 0;
0253 
0254     switch (adc_feature->clk_sel) {
0255     case VF610_ADCIOC_ALTCLK_SET:
0256         cfg_data |= VF610_ADC_ALTCLK_SEL;
0257         break;
0258     case VF610_ADCIOC_ADACK_SET:
0259         cfg_data |= VF610_ADC_ADACK_SEL;
0260         break;
0261     default:
0262         break;
0263     }
0264 
0265     /* low power set for calibration */
0266     cfg_data |= VF610_ADC_ADLPC_EN;
0267 
0268     /* enable high speed for calibration */
0269     cfg_data |= VF610_ADC_ADHSC_EN;
0270 
0271     /* voltage reference */
0272     switch (adc_feature->vol_ref) {
0273     case VF610_ADCIOC_VR_VREF_SET:
0274         break;
0275     case VF610_ADCIOC_VR_VALT_SET:
0276         cfg_data |= VF610_ADC_REFSEL_VALT;
0277         break;
0278     case VF610_ADCIOC_VR_VBG_SET:
0279         cfg_data |= VF610_ADC_REFSEL_VBG;
0280         break;
0281     default:
0282         dev_err(info->dev, "error voltage reference\n");
0283     }
0284 
0285     /* data overwrite enable */
0286     if (adc_feature->ovwren)
0287         cfg_data |= VF610_ADC_OVWREN;
0288 
0289     writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
0290     writel(gc_data, info->regs + VF610_REG_ADC_GC);
0291 }
0292 
0293 static void vf610_adc_calibration(struct vf610_adc *info)
0294 {
0295     int adc_gc, hc_cfg;
0296 
0297     if (!info->adc_feature.calibration)
0298         return;
0299 
0300     /* enable calibration interrupt */
0301     hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
0302     writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
0303 
0304     adc_gc = readl(info->regs + VF610_REG_ADC_GC);
0305     writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
0306 
0307     if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
0308         dev_err(info->dev, "Timeout for adc calibration\n");
0309 
0310     adc_gc = readl(info->regs + VF610_REG_ADC_GS);
0311     if (adc_gc & VF610_ADC_CALF)
0312         dev_err(info->dev, "ADC calibration failed\n");
0313 
0314     info->adc_feature.calibration = false;
0315 }
0316 
0317 static void vf610_adc_cfg_set(struct vf610_adc *info)
0318 {
0319     struct vf610_adc_feature *adc_feature = &(info->adc_feature);
0320     int cfg_data;
0321 
0322     cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
0323 
0324     cfg_data &= ~VF610_ADC_ADLPC_EN;
0325     if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
0326         cfg_data |= VF610_ADC_ADLPC_EN;
0327 
0328     cfg_data &= ~VF610_ADC_ADHSC_EN;
0329     if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
0330         cfg_data |= VF610_ADC_ADHSC_EN;
0331 
0332     writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
0333 }
0334 
0335 static void vf610_adc_sample_set(struct vf610_adc *info)
0336 {
0337     struct vf610_adc_feature *adc_feature = &(info->adc_feature);
0338     int cfg_data, gc_data;
0339 
0340     cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
0341     gc_data = readl(info->regs + VF610_REG_ADC_GC);
0342 
0343     /* resolution mode */
0344     cfg_data &= ~VF610_ADC_MODE_MASK;
0345     switch (adc_feature->res_mode) {
0346     case 8:
0347         cfg_data |= VF610_ADC_MODE_BIT8;
0348         break;
0349     case 10:
0350         cfg_data |= VF610_ADC_MODE_BIT10;
0351         break;
0352     case 12:
0353         cfg_data |= VF610_ADC_MODE_BIT12;
0354         break;
0355     default:
0356         dev_err(info->dev, "error resolution mode\n");
0357         break;
0358     }
0359 
0360     /* clock select and clock divider */
0361     cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
0362     switch (adc_feature->clk_div) {
0363     case 1:
0364         break;
0365     case 2:
0366         cfg_data |= VF610_ADC_CLK_DIV2;
0367         break;
0368     case 4:
0369         cfg_data |= VF610_ADC_CLK_DIV4;
0370         break;
0371     case 8:
0372         cfg_data |= VF610_ADC_CLK_DIV8;
0373         break;
0374     case 16:
0375         switch (adc_feature->clk_sel) {
0376         case VF610_ADCIOC_BUSCLK_SET:
0377             cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
0378             break;
0379         default:
0380             dev_err(info->dev, "error clk divider\n");
0381             break;
0382         }
0383         break;
0384     }
0385 
0386     /*
0387      * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
0388      * determined.
0389      */
0390     switch (adc_feature->lst_adder_index) {
0391     case VF610_ADCK_CYCLES_3:
0392         break;
0393     case VF610_ADCK_CYCLES_5:
0394         cfg_data |= VF610_ADC_ADSTS_SHORT;
0395         break;
0396     case VF610_ADCK_CYCLES_7:
0397         cfg_data |= VF610_ADC_ADSTS_NORMAL;
0398         break;
0399     case VF610_ADCK_CYCLES_9:
0400         cfg_data |= VF610_ADC_ADSTS_LONG;
0401         break;
0402     case VF610_ADCK_CYCLES_13:
0403         cfg_data |= VF610_ADC_ADLSMP_LONG;
0404         break;
0405     case VF610_ADCK_CYCLES_17:
0406         cfg_data |= VF610_ADC_ADLSMP_LONG;
0407         cfg_data |= VF610_ADC_ADSTS_SHORT;
0408         break;
0409     case VF610_ADCK_CYCLES_21:
0410         cfg_data |= VF610_ADC_ADLSMP_LONG;
0411         cfg_data |= VF610_ADC_ADSTS_NORMAL;
0412         break;
0413     case VF610_ADCK_CYCLES_25:
0414         cfg_data |= VF610_ADC_ADLSMP_LONG;
0415         cfg_data |= VF610_ADC_ADSTS_NORMAL;
0416         break;
0417     default:
0418         dev_err(info->dev, "error in sample time select\n");
0419     }
0420 
0421     /* update hardware average selection */
0422     cfg_data &= ~VF610_ADC_AVGS_MASK;
0423     gc_data &= ~VF610_ADC_AVGEN;
0424     switch (adc_feature->sample_rate) {
0425     case VF610_ADC_SAMPLE_1:
0426         break;
0427     case VF610_ADC_SAMPLE_4:
0428         gc_data |= VF610_ADC_AVGEN;
0429         break;
0430     case VF610_ADC_SAMPLE_8:
0431         gc_data |= VF610_ADC_AVGEN;
0432         cfg_data |= VF610_ADC_AVGS_8;
0433         break;
0434     case VF610_ADC_SAMPLE_16:
0435         gc_data |= VF610_ADC_AVGEN;
0436         cfg_data |= VF610_ADC_AVGS_16;
0437         break;
0438     case VF610_ADC_SAMPLE_32:
0439         gc_data |= VF610_ADC_AVGEN;
0440         cfg_data |= VF610_ADC_AVGS_32;
0441         break;
0442     default:
0443         dev_err(info->dev,
0444             "error hardware sample average select\n");
0445     }
0446 
0447     writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
0448     writel(gc_data, info->regs + VF610_REG_ADC_GC);
0449 }
0450 
0451 static void vf610_adc_hw_init(struct vf610_adc *info)
0452 {
0453     /* CFG: Feature set */
0454     vf610_adc_cfg_post_set(info);
0455     vf610_adc_sample_set(info);
0456 
0457     /* adc calibration */
0458     vf610_adc_calibration(info);
0459 
0460     /* CFG: power and speed set */
0461     vf610_adc_cfg_set(info);
0462 }
0463 
0464 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
0465                      const struct iio_chan_spec *chan,
0466                      unsigned int mode)
0467 {
0468     struct vf610_adc *info = iio_priv(indio_dev);
0469 
0470     mutex_lock(&indio_dev->mlock);
0471     info->adc_feature.conv_mode = mode;
0472     vf610_adc_calculate_rates(info);
0473     vf610_adc_hw_init(info);
0474     mutex_unlock(&indio_dev->mlock);
0475 
0476     return 0;
0477 }
0478 
0479 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
0480                      const struct iio_chan_spec *chan)
0481 {
0482     struct vf610_adc *info = iio_priv(indio_dev);
0483 
0484     return info->adc_feature.conv_mode;
0485 }
0486 
0487 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
0488                          "low-power" };
0489 
0490 static const struct iio_enum vf610_conversion_mode = {
0491     .items = vf610_conv_modes,
0492     .num_items = ARRAY_SIZE(vf610_conv_modes),
0493     .get = vf610_get_conversion_mode,
0494     .set = vf610_set_conversion_mode,
0495 };
0496 
0497 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
0498     IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
0499     {},
0500 };
0501 
0502 #define VF610_ADC_CHAN(_idx, _chan_type) {          \
0503     .type = (_chan_type),                   \
0504     .indexed = 1,                       \
0505     .channel = (_idx),                  \
0506     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0507     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
0508                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0509     .ext_info = vf610_ext_info,             \
0510     .scan_index = (_idx),           \
0511     .scan_type = {                  \
0512         .sign = 'u',                \
0513         .realbits = 12,             \
0514         .storagebits = 16,          \
0515     },                      \
0516 }
0517 
0518 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {  \
0519     .type = (_chan_type),   \
0520     .channel = (_idx),      \
0521     .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
0522     .scan_index = (_idx),                   \
0523     .scan_type = {                      \
0524         .sign = 'u',                    \
0525         .realbits = 12,                 \
0526         .storagebits = 16,              \
0527     },                          \
0528 }
0529 
0530 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
0531     VF610_ADC_CHAN(0, IIO_VOLTAGE),
0532     VF610_ADC_CHAN(1, IIO_VOLTAGE),
0533     VF610_ADC_CHAN(2, IIO_VOLTAGE),
0534     VF610_ADC_CHAN(3, IIO_VOLTAGE),
0535     VF610_ADC_CHAN(4, IIO_VOLTAGE),
0536     VF610_ADC_CHAN(5, IIO_VOLTAGE),
0537     VF610_ADC_CHAN(6, IIO_VOLTAGE),
0538     VF610_ADC_CHAN(7, IIO_VOLTAGE),
0539     VF610_ADC_CHAN(8, IIO_VOLTAGE),
0540     VF610_ADC_CHAN(9, IIO_VOLTAGE),
0541     VF610_ADC_CHAN(10, IIO_VOLTAGE),
0542     VF610_ADC_CHAN(11, IIO_VOLTAGE),
0543     VF610_ADC_CHAN(12, IIO_VOLTAGE),
0544     VF610_ADC_CHAN(13, IIO_VOLTAGE),
0545     VF610_ADC_CHAN(14, IIO_VOLTAGE),
0546     VF610_ADC_CHAN(15, IIO_VOLTAGE),
0547     VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
0548     IIO_CHAN_SOFT_TIMESTAMP(32),
0549     /* sentinel */
0550 };
0551 
0552 static int vf610_adc_read_data(struct vf610_adc *info)
0553 {
0554     int result;
0555 
0556     result = readl(info->regs + VF610_REG_ADC_R0);
0557 
0558     switch (info->adc_feature.res_mode) {
0559     case 8:
0560         result &= 0xFF;
0561         break;
0562     case 10:
0563         result &= 0x3FF;
0564         break;
0565     case 12:
0566         result &= 0xFFF;
0567         break;
0568     default:
0569         break;
0570     }
0571 
0572     return result;
0573 }
0574 
0575 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
0576 {
0577     struct iio_dev *indio_dev = dev_id;
0578     struct vf610_adc *info = iio_priv(indio_dev);
0579     int coco;
0580 
0581     coco = readl(info->regs + VF610_REG_ADC_HS);
0582     if (coco & VF610_ADC_HS_COCO0) {
0583         info->value = vf610_adc_read_data(info);
0584         if (iio_buffer_enabled(indio_dev)) {
0585             info->scan.chan = info->value;
0586             iio_push_to_buffers_with_timestamp(indio_dev,
0587                     &info->scan,
0588                     iio_get_time_ns(indio_dev));
0589             iio_trigger_notify_done(indio_dev->trig);
0590         } else
0591             complete(&info->completion);
0592     }
0593 
0594     return IRQ_HANDLED;
0595 }
0596 
0597 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
0598                 struct device_attribute *attr, char *buf)
0599 {
0600     struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
0601     size_t len = 0;
0602     int i;
0603 
0604     for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
0605         len += scnprintf(buf + len, PAGE_SIZE - len,
0606             "%u ", info->sample_freq_avail[i]);
0607 
0608     /* replace trailing space by newline */
0609     buf[len - 1] = '\n';
0610 
0611     return len;
0612 }
0613 
0614 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
0615 
0616 static struct attribute *vf610_attributes[] = {
0617     &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
0618     NULL
0619 };
0620 
0621 static const struct attribute_group vf610_attribute_group = {
0622     .attrs = vf610_attributes,
0623 };
0624 
0625 static int vf610_read_raw(struct iio_dev *indio_dev,
0626             struct iio_chan_spec const *chan,
0627             int *val,
0628             int *val2,
0629             long mask)
0630 {
0631     struct vf610_adc *info = iio_priv(indio_dev);
0632     unsigned int hc_cfg;
0633     long ret;
0634 
0635     switch (mask) {
0636     case IIO_CHAN_INFO_RAW:
0637     case IIO_CHAN_INFO_PROCESSED:
0638         mutex_lock(&indio_dev->mlock);
0639         if (iio_buffer_enabled(indio_dev)) {
0640             mutex_unlock(&indio_dev->mlock);
0641             return -EBUSY;
0642         }
0643 
0644         reinit_completion(&info->completion);
0645         hc_cfg = VF610_ADC_ADCHC(chan->channel);
0646         hc_cfg |= VF610_ADC_AIEN;
0647         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
0648         ret = wait_for_completion_interruptible_timeout
0649                 (&info->completion, VF610_ADC_TIMEOUT);
0650         if (ret == 0) {
0651             mutex_unlock(&indio_dev->mlock);
0652             return -ETIMEDOUT;
0653         }
0654         if (ret < 0) {
0655             mutex_unlock(&indio_dev->mlock);
0656             return ret;
0657         }
0658 
0659         switch (chan->type) {
0660         case IIO_VOLTAGE:
0661             *val = info->value;
0662             break;
0663         case IIO_TEMP:
0664             /*
0665              * Calculate in degree Celsius times 1000
0666              * Using the typical sensor slope of 1.84 mV/°C
0667              * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
0668              */
0669             *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
0670                     1000000 / VF610_TEMP_SLOPE_COEFF;
0671 
0672             break;
0673         default:
0674             mutex_unlock(&indio_dev->mlock);
0675             return -EINVAL;
0676         }
0677 
0678         mutex_unlock(&indio_dev->mlock);
0679         return IIO_VAL_INT;
0680 
0681     case IIO_CHAN_INFO_SCALE:
0682         *val = info->vref_uv / 1000;
0683         *val2 = info->adc_feature.res_mode;
0684         return IIO_VAL_FRACTIONAL_LOG2;
0685 
0686     case IIO_CHAN_INFO_SAMP_FREQ:
0687         *val = info->sample_freq_avail[info->adc_feature.sample_rate];
0688         *val2 = 0;
0689         return IIO_VAL_INT;
0690 
0691     default:
0692         break;
0693     }
0694 
0695     return -EINVAL;
0696 }
0697 
0698 static int vf610_write_raw(struct iio_dev *indio_dev,
0699             struct iio_chan_spec const *chan,
0700             int val,
0701             int val2,
0702             long mask)
0703 {
0704     struct vf610_adc *info = iio_priv(indio_dev);
0705     int i;
0706 
0707     switch (mask) {
0708     case IIO_CHAN_INFO_SAMP_FREQ:
0709         for (i = 0;
0710             i < ARRAY_SIZE(info->sample_freq_avail);
0711             i++)
0712             if (val == info->sample_freq_avail[i]) {
0713                 info->adc_feature.sample_rate = i;
0714                 vf610_adc_sample_set(info);
0715                 return 0;
0716             }
0717         break;
0718 
0719     default:
0720         break;
0721     }
0722 
0723     return -EINVAL;
0724 }
0725 
0726 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
0727 {
0728     struct vf610_adc *info = iio_priv(indio_dev);
0729     unsigned int channel;
0730     int val;
0731 
0732     val = readl(info->regs + VF610_REG_ADC_GC);
0733     val |= VF610_ADC_ADCON;
0734     writel(val, info->regs + VF610_REG_ADC_GC);
0735 
0736     channel = find_first_bit(indio_dev->active_scan_mask,
0737                         indio_dev->masklength);
0738 
0739     val = VF610_ADC_ADCHC(channel);
0740     val |= VF610_ADC_AIEN;
0741 
0742     writel(val, info->regs + VF610_REG_ADC_HC0);
0743 
0744     return 0;
0745 }
0746 
0747 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
0748 {
0749     struct vf610_adc *info = iio_priv(indio_dev);
0750     unsigned int hc_cfg = 0;
0751     int val;
0752 
0753     val = readl(info->regs + VF610_REG_ADC_GC);
0754     val &= ~VF610_ADC_ADCON;
0755     writel(val, info->regs + VF610_REG_ADC_GC);
0756 
0757     hc_cfg |= VF610_ADC_CONV_DISABLE;
0758     hc_cfg &= ~VF610_ADC_AIEN;
0759 
0760     writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
0761 
0762     return 0;
0763 }
0764 
0765 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
0766     .postenable = &vf610_adc_buffer_postenable,
0767     .predisable = &vf610_adc_buffer_predisable,
0768     .validate_scan_mask = &iio_validate_scan_mask_onehot,
0769 };
0770 
0771 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
0772             unsigned reg, unsigned writeval,
0773             unsigned *readval)
0774 {
0775     struct vf610_adc *info = iio_priv(indio_dev);
0776 
0777     if ((readval == NULL) ||
0778         ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
0779         return -EINVAL;
0780 
0781     *readval = readl(info->regs + reg);
0782 
0783     return 0;
0784 }
0785 
0786 static const struct iio_info vf610_adc_iio_info = {
0787     .read_raw = &vf610_read_raw,
0788     .write_raw = &vf610_write_raw,
0789     .debugfs_reg_access = &vf610_adc_reg_access,
0790     .attrs = &vf610_attribute_group,
0791 };
0792 
0793 static const struct of_device_id vf610_adc_match[] = {
0794     { .compatible = "fsl,vf610-adc", },
0795     { /* sentinel */ }
0796 };
0797 MODULE_DEVICE_TABLE(of, vf610_adc_match);
0798 
0799 static int vf610_adc_probe(struct platform_device *pdev)
0800 {
0801     struct device *dev = &pdev->dev;
0802     struct vf610_adc *info;
0803     struct iio_dev *indio_dev;
0804     int irq;
0805     int ret;
0806 
0807     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
0808     if (!indio_dev) {
0809         dev_err(&pdev->dev, "Failed allocating iio device\n");
0810         return -ENOMEM;
0811     }
0812 
0813     info = iio_priv(indio_dev);
0814     info->dev = &pdev->dev;
0815 
0816     info->regs = devm_platform_ioremap_resource(pdev, 0);
0817     if (IS_ERR(info->regs))
0818         return PTR_ERR(info->regs);
0819 
0820     irq = platform_get_irq(pdev, 0);
0821     if (irq < 0)
0822         return irq;
0823 
0824     ret = devm_request_irq(info->dev, irq,
0825                 vf610_adc_isr, 0,
0826                 dev_name(&pdev->dev), indio_dev);
0827     if (ret < 0) {
0828         dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
0829         return ret;
0830     }
0831 
0832     info->clk = devm_clk_get(&pdev->dev, "adc");
0833     if (IS_ERR(info->clk)) {
0834         dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
0835                         PTR_ERR(info->clk));
0836         return PTR_ERR(info->clk);
0837     }
0838 
0839     info->vref = devm_regulator_get(&pdev->dev, "vref");
0840     if (IS_ERR(info->vref))
0841         return PTR_ERR(info->vref);
0842 
0843     ret = regulator_enable(info->vref);
0844     if (ret)
0845         return ret;
0846 
0847     info->vref_uv = regulator_get_voltage(info->vref);
0848 
0849     device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3);
0850 
0851     info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
0852     device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time);
0853 
0854     platform_set_drvdata(pdev, indio_dev);
0855 
0856     init_completion(&info->completion);
0857 
0858     indio_dev->name = dev_name(&pdev->dev);
0859     indio_dev->info = &vf610_adc_iio_info;
0860     indio_dev->modes = INDIO_DIRECT_MODE;
0861     indio_dev->channels = vf610_adc_iio_channels;
0862     indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
0863 
0864     ret = clk_prepare_enable(info->clk);
0865     if (ret) {
0866         dev_err(&pdev->dev,
0867             "Could not prepare or enable the clock.\n");
0868         goto error_adc_clk_enable;
0869     }
0870 
0871     vf610_adc_cfg_init(info);
0872     vf610_adc_hw_init(info);
0873 
0874     ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
0875                     NULL, &iio_triggered_buffer_setup_ops);
0876     if (ret < 0) {
0877         dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
0878         goto error_iio_device_register;
0879     }
0880 
0881     ret = iio_device_register(indio_dev);
0882     if (ret) {
0883         dev_err(&pdev->dev, "Couldn't register the device.\n");
0884         goto error_adc_buffer_init;
0885     }
0886 
0887     return 0;
0888 
0889 error_adc_buffer_init:
0890     iio_triggered_buffer_cleanup(indio_dev);
0891 error_iio_device_register:
0892     clk_disable_unprepare(info->clk);
0893 error_adc_clk_enable:
0894     regulator_disable(info->vref);
0895 
0896     return ret;
0897 }
0898 
0899 static int vf610_adc_remove(struct platform_device *pdev)
0900 {
0901     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0902     struct vf610_adc *info = iio_priv(indio_dev);
0903 
0904     iio_device_unregister(indio_dev);
0905     iio_triggered_buffer_cleanup(indio_dev);
0906     regulator_disable(info->vref);
0907     clk_disable_unprepare(info->clk);
0908 
0909     return 0;
0910 }
0911 
0912 static int vf610_adc_suspend(struct device *dev)
0913 {
0914     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0915     struct vf610_adc *info = iio_priv(indio_dev);
0916     int hc_cfg;
0917 
0918     /* ADC controller enters to stop mode */
0919     hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
0920     hc_cfg |= VF610_ADC_CONV_DISABLE;
0921     writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
0922 
0923     clk_disable_unprepare(info->clk);
0924     regulator_disable(info->vref);
0925 
0926     return 0;
0927 }
0928 
0929 static int vf610_adc_resume(struct device *dev)
0930 {
0931     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0932     struct vf610_adc *info = iio_priv(indio_dev);
0933     int ret;
0934 
0935     ret = regulator_enable(info->vref);
0936     if (ret)
0937         return ret;
0938 
0939     ret = clk_prepare_enable(info->clk);
0940     if (ret)
0941         goto disable_reg;
0942 
0943     vf610_adc_hw_init(info);
0944 
0945     return 0;
0946 
0947 disable_reg:
0948     regulator_disable(info->vref);
0949     return ret;
0950 }
0951 
0952 static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend,
0953                 vf610_adc_resume);
0954 
0955 static struct platform_driver vf610_adc_driver = {
0956     .probe          = vf610_adc_probe,
0957     .remove         = vf610_adc_remove,
0958     .driver         = {
0959         .name   = DRIVER_NAME,
0960         .of_match_table = vf610_adc_match,
0961         .pm     = pm_sleep_ptr(&vf610_adc_pm_ops),
0962     },
0963 };
0964 
0965 module_platform_driver(vf610_adc_driver);
0966 
0967 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
0968 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
0969 MODULE_LICENSE("GPL v2");
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