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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI ADC MFD driver
0004  *
0005  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/err.h>
0010 #include <linux/module.h>
0011 #include <linux/slab.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/io.h>
0015 #include <linux/iio/iio.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/iio/machine.h>
0019 #include <linux/iio/driver.h>
0020 #include <linux/iopoll.h>
0021 
0022 #include <linux/mfd/ti_am335x_tscadc.h>
0023 #include <linux/iio/buffer.h>
0024 #include <linux/iio/kfifo_buf.h>
0025 
0026 #include <linux/dmaengine.h>
0027 #include <linux/dma-mapping.h>
0028 
0029 #define DMA_BUFFER_SIZE     SZ_2K
0030 
0031 struct tiadc_dma {
0032     struct dma_slave_config conf;
0033     struct dma_chan     *chan;
0034     dma_addr_t      addr;
0035     dma_cookie_t        cookie;
0036     u8          *buf;
0037     int         current_period;
0038     int         period_size;
0039     u8          fifo_thresh;
0040 };
0041 
0042 struct tiadc_device {
0043     struct ti_tscadc_dev *mfd_tscadc;
0044     struct tiadc_dma dma;
0045     struct mutex fifo1_lock; /* to protect fifo access */
0046     int channels;
0047     int total_ch_enabled;
0048     u8 channel_line[8];
0049     u8 channel_step[8];
0050     int buffer_en_ch_steps;
0051     u16 data[8];
0052     u32 open_delay[8], sample_delay[8], step_avg[8];
0053 };
0054 
0055 static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
0056 {
0057     return readl(adc->mfd_tscadc->tscadc_base + reg);
0058 }
0059 
0060 static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
0061              unsigned int val)
0062 {
0063     writel(val, adc->mfd_tscadc->tscadc_base + reg);
0064 }
0065 
0066 static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
0067 {
0068     u32 step_en;
0069 
0070     step_en = ((1 << adc_dev->channels) - 1);
0071     step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
0072     return step_en;
0073 }
0074 
0075 static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
0076                   struct iio_chan_spec const *chan)
0077 {
0078     int i;
0079 
0080     for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
0081         if (chan->channel == adc_dev->channel_line[i]) {
0082             u32 step;
0083 
0084             step = adc_dev->channel_step[i];
0085             /* +1 for the charger */
0086             return 1 << (step + 1);
0087         }
0088     }
0089     WARN_ON(1);
0090     return 0;
0091 }
0092 
0093 static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
0094 {
0095     return 1 << adc_dev->channel_step[chan];
0096 }
0097 
0098 static int tiadc_wait_idle(struct tiadc_device *adc_dev)
0099 {
0100     u32 val;
0101 
0102     return readl_poll_timeout(adc_dev->mfd_tscadc->tscadc_base + REG_ADCFSM,
0103                   val, !(val & SEQ_STATUS), 10,
0104                   IDLE_TIMEOUT_MS * 1000 * adc_dev->channels);
0105 }
0106 
0107 static void tiadc_step_config(struct iio_dev *indio_dev)
0108 {
0109     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0110     unsigned int stepconfig;
0111     int i, steps = 0;
0112 
0113     /*
0114      * There are 16 configurable steps and 8 analog input
0115      * lines available which are shared between Touchscreen and ADC.
0116      *
0117      * Steps forwards i.e. from 0 towards 16 are used by ADC
0118      * depending on number of input lines needed.
0119      * Channel would represent which analog input
0120      * needs to be given to ADC to digitalize data.
0121      */
0122     for (i = 0; i < adc_dev->channels; i++) {
0123         int chan;
0124 
0125         chan = adc_dev->channel_line[i];
0126 
0127         if (adc_dev->step_avg[i])
0128             stepconfig = STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
0129                      STEPCONFIG_FIFO1;
0130         else
0131             stepconfig = STEPCONFIG_FIFO1;
0132 
0133         if (iio_buffer_enabled(indio_dev))
0134             stepconfig |= STEPCONFIG_MODE_SWCNT;
0135 
0136         tiadc_writel(adc_dev, REG_STEPCONFIG(steps),
0137                  stepconfig | STEPCONFIG_INP(chan) |
0138                  STEPCONFIG_INM_ADCREFM | STEPCONFIG_RFP_VREFP |
0139                  STEPCONFIG_RFM_VREFN);
0140 
0141         tiadc_writel(adc_dev, REG_STEPDELAY(steps),
0142                  STEPDELAY_OPEN(adc_dev->open_delay[i]) |
0143                  STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
0144 
0145         adc_dev->channel_step[i] = steps;
0146         steps++;
0147     }
0148 }
0149 
0150 static irqreturn_t tiadc_irq_h(int irq, void *private)
0151 {
0152     struct iio_dev *indio_dev = private;
0153     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0154     unsigned int status, config, adc_fsm;
0155     unsigned short count = 0;
0156 
0157     status = tiadc_readl(adc_dev, REG_IRQSTATUS);
0158 
0159     /*
0160      * ADC and touchscreen share the IRQ line.
0161      * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
0162      */
0163     if (status & IRQENB_FIFO1OVRRUN) {
0164         /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
0165         config = tiadc_readl(adc_dev, REG_CTRL);
0166         config &= ~(CNTRLREG_SSENB);
0167         tiadc_writel(adc_dev, REG_CTRL, config);
0168         tiadc_writel(adc_dev, REG_IRQSTATUS,
0169                  IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW |
0170                  IRQENB_FIFO1THRES);
0171 
0172         /*
0173          * Wait for the idle state.
0174          * ADC needs to finish the current conversion
0175          * before disabling the module
0176          */
0177         do {
0178             adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
0179         } while (adc_fsm != 0x10 && count++ < 100);
0180 
0181         tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_SSENB));
0182         return IRQ_HANDLED;
0183     } else if (status & IRQENB_FIFO1THRES) {
0184         /* Disable irq and wake worker thread */
0185         tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
0186         return IRQ_WAKE_THREAD;
0187     }
0188 
0189     return IRQ_NONE;
0190 }
0191 
0192 static irqreturn_t tiadc_worker_h(int irq, void *private)
0193 {
0194     struct iio_dev *indio_dev = private;
0195     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0196     int i, k, fifo1count, read;
0197     u16 *data = adc_dev->data;
0198 
0199     fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
0200     for (k = 0; k < fifo1count; k = k + i) {
0201         for (i = 0; i < indio_dev->scan_bytes / 2; i++) {
0202             read = tiadc_readl(adc_dev, REG_FIFO1);
0203             data[i] = read & FIFOREAD_DATA_MASK;
0204         }
0205         iio_push_to_buffers(indio_dev, (u8 *)data);
0206     }
0207 
0208     tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
0209     tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
0210 
0211     return IRQ_HANDLED;
0212 }
0213 
0214 static void tiadc_dma_rx_complete(void *param)
0215 {
0216     struct iio_dev *indio_dev = param;
0217     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0218     struct tiadc_dma *dma = &adc_dev->dma;
0219     u8 *data;
0220     int i;
0221 
0222     data = dma->buf + dma->current_period * dma->period_size;
0223     dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
0224 
0225     for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
0226         iio_push_to_buffers(indio_dev, data);
0227         data += indio_dev->scan_bytes;
0228     }
0229 }
0230 
0231 static int tiadc_start_dma(struct iio_dev *indio_dev)
0232 {
0233     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0234     struct tiadc_dma *dma = &adc_dev->dma;
0235     struct dma_async_tx_descriptor *desc;
0236 
0237     dma->current_period = 0; /* We start to fill period 0 */
0238 
0239     /*
0240      * Make the fifo thresh as the multiple of total number of
0241      * channels enabled, so make sure that cyclic DMA period
0242      * length is also a multiple of total number of channels
0243      * enabled. This ensures that no invalid data is reported
0244      * to the stack via iio_push_to_buffers().
0245      */
0246     dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
0247                      adc_dev->total_ch_enabled) - 1;
0248 
0249     /* Make sure that period length is multiple of fifo thresh level */
0250     dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
0251                      (dma->fifo_thresh + 1) * sizeof(u16));
0252 
0253     dma->conf.src_maxburst = dma->fifo_thresh + 1;
0254     dmaengine_slave_config(dma->chan, &dma->conf);
0255 
0256     desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
0257                      dma->period_size * 2,
0258                      dma->period_size, DMA_DEV_TO_MEM,
0259                      DMA_PREP_INTERRUPT);
0260     if (!desc)
0261         return -EBUSY;
0262 
0263     desc->callback = tiadc_dma_rx_complete;
0264     desc->callback_param = indio_dev;
0265 
0266     dma->cookie = dmaengine_submit(desc);
0267 
0268     dma_async_issue_pending(dma->chan);
0269 
0270     tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
0271     tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
0272     tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
0273 
0274     return 0;
0275 }
0276 
0277 static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
0278 {
0279     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0280     int i, fifo1count;
0281     int ret;
0282 
0283     ret = tiadc_wait_idle(adc_dev);
0284     if (ret)
0285         return ret;
0286 
0287     tiadc_writel(adc_dev, REG_IRQCLR,
0288              IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN |
0289              IRQENB_FIFO1UNDRFLW);
0290 
0291     /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
0292     fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
0293     for (i = 0; i < fifo1count; i++)
0294         tiadc_readl(adc_dev, REG_FIFO1);
0295 
0296     return 0;
0297 }
0298 
0299 static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
0300 {
0301     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0302     struct tiadc_dma *dma = &adc_dev->dma;
0303     unsigned int irq_enable;
0304     unsigned int enb = 0;
0305     u8 bit;
0306 
0307     tiadc_step_config(indio_dev);
0308     for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
0309         enb |= (get_adc_step_bit(adc_dev, bit) << 1);
0310         adc_dev->total_ch_enabled++;
0311     }
0312     adc_dev->buffer_en_ch_steps = enb;
0313 
0314     if (dma->chan)
0315         tiadc_start_dma(indio_dev);
0316 
0317     am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
0318 
0319     tiadc_writel(adc_dev, REG_IRQSTATUS,
0320              IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN |
0321              IRQENB_FIFO1UNDRFLW);
0322 
0323     irq_enable = IRQENB_FIFO1OVRRUN;
0324     if (!dma->chan)
0325         irq_enable |= IRQENB_FIFO1THRES;
0326     tiadc_writel(adc_dev,  REG_IRQENABLE, irq_enable);
0327 
0328     return 0;
0329 }
0330 
0331 static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
0332 {
0333     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0334     struct tiadc_dma *dma = &adc_dev->dma;
0335     int fifo1count, i;
0336 
0337     tiadc_writel(adc_dev, REG_IRQCLR,
0338              IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN |
0339              IRQENB_FIFO1UNDRFLW);
0340     am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
0341     adc_dev->buffer_en_ch_steps = 0;
0342     adc_dev->total_ch_enabled = 0;
0343     if (dma->chan) {
0344         tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
0345         dmaengine_terminate_async(dma->chan);
0346     }
0347 
0348     /* Flush FIFO of leftover data in the time it takes to disable adc */
0349     fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
0350     for (i = 0; i < fifo1count; i++)
0351         tiadc_readl(adc_dev, REG_FIFO1);
0352 
0353     return 0;
0354 }
0355 
0356 static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
0357 {
0358     tiadc_step_config(indio_dev);
0359 
0360     return 0;
0361 }
0362 
0363 static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
0364     .preenable = &tiadc_buffer_preenable,
0365     .postenable = &tiadc_buffer_postenable,
0366     .predisable = &tiadc_buffer_predisable,
0367     .postdisable = &tiadc_buffer_postdisable,
0368 };
0369 
0370 static int tiadc_iio_buffered_hardware_setup(struct device *dev,
0371                          struct iio_dev *indio_dev,
0372                          irqreturn_t (*pollfunc_bh)(int irq, void *p),
0373                          irqreturn_t (*pollfunc_th)(int irq, void *p),
0374                          int irq, unsigned long flags,
0375                          const struct iio_buffer_setup_ops *setup_ops)
0376 {
0377     int ret;
0378 
0379     ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, setup_ops);
0380     if (ret)
0381         return ret;
0382 
0383     return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh,
0384                      flags, indio_dev->name, indio_dev);
0385 }
0386 
0387 static const char * const chan_name_ain[] = {
0388     "AIN0",
0389     "AIN1",
0390     "AIN2",
0391     "AIN3",
0392     "AIN4",
0393     "AIN5",
0394     "AIN6",
0395     "AIN7",
0396 };
0397 
0398 static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev,
0399                   int channels)
0400 {
0401     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0402     struct iio_chan_spec *chan_array;
0403     struct iio_chan_spec *chan;
0404     int i;
0405 
0406     indio_dev->num_channels = channels;
0407     chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array),
0408                   GFP_KERNEL);
0409     if (!chan_array)
0410         return -ENOMEM;
0411 
0412     chan = chan_array;
0413     for (i = 0; i < channels; i++, chan++) {
0414         chan->type = IIO_VOLTAGE;
0415         chan->indexed = 1;
0416         chan->channel = adc_dev->channel_line[i];
0417         chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0418         chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0419         chan->datasheet_name = chan_name_ain[chan->channel];
0420         chan->scan_index = i;
0421         chan->scan_type.sign = 'u';
0422         chan->scan_type.realbits = 12;
0423         chan->scan_type.storagebits = 16;
0424     }
0425 
0426     indio_dev->channels = chan_array;
0427 
0428     return 0;
0429 }
0430 
0431 static int tiadc_read_raw(struct iio_dev *indio_dev,
0432               struct iio_chan_spec const *chan, int *val, int *val2,
0433               long mask)
0434 {
0435     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0436     int i, map_val;
0437     unsigned int fifo1count, read, stepid;
0438     bool found = false;
0439     u32 step_en;
0440     unsigned long timeout;
0441     int ret;
0442 
0443     switch (mask) {
0444     case IIO_CHAN_INFO_RAW:
0445         break;
0446     case IIO_CHAN_INFO_SCALE:
0447         switch (chan->type) {
0448         case IIO_VOLTAGE:
0449             *val = 1800;
0450             *val2 = chan->scan_type.realbits;
0451             return IIO_VAL_FRACTIONAL_LOG2;
0452         default:
0453             return -EINVAL;
0454         }
0455         break;
0456     default:
0457         return -EINVAL;
0458     }
0459 
0460     if (iio_buffer_enabled(indio_dev))
0461         return -EBUSY;
0462 
0463     step_en = get_adc_chan_step_mask(adc_dev, chan);
0464     if (!step_en)
0465         return -EINVAL;
0466 
0467     mutex_lock(&adc_dev->fifo1_lock);
0468 
0469     ret = tiadc_wait_idle(adc_dev);
0470     if (ret)
0471         goto err_unlock;
0472 
0473     fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
0474     while (fifo1count--)
0475         tiadc_readl(adc_dev, REG_FIFO1);
0476 
0477     am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
0478 
0479     /* Wait for Fifo threshold interrupt */
0480     timeout = jiffies + msecs_to_jiffies(IDLE_TIMEOUT_MS * adc_dev->channels);
0481     while (1) {
0482         fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
0483         if (fifo1count)
0484             break;
0485 
0486         if (time_after(jiffies, timeout)) {
0487             am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
0488             ret = -EAGAIN;
0489             goto err_unlock;
0490         }
0491     }
0492 
0493     map_val = adc_dev->channel_step[chan->scan_index];
0494 
0495     /*
0496      * We check the complete FIFO. We programmed just one entry but in case
0497      * something went wrong we left empty handed (-EAGAIN previously) and
0498      * then the value apeared somehow in the FIFO we would have two entries.
0499      * Therefore we read every item and keep only the latest version of the
0500      * requested channel.
0501      */
0502     for (i = 0; i < fifo1count; i++) {
0503         read = tiadc_readl(adc_dev, REG_FIFO1);
0504         stepid = read & FIFOREAD_CHNLID_MASK;
0505         stepid = stepid >> 0x10;
0506 
0507         if (stepid == map_val) {
0508             read = read & FIFOREAD_DATA_MASK;
0509             found = true;
0510             *val = (u16)read;
0511         }
0512     }
0513 
0514     am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
0515 
0516     if (!found)
0517         ret = -EBUSY;
0518 
0519 err_unlock:
0520     mutex_unlock(&adc_dev->fifo1_lock);
0521     return ret ? ret : IIO_VAL_INT;
0522 }
0523 
0524 static const struct iio_info tiadc_info = {
0525     .read_raw = &tiadc_read_raw,
0526 };
0527 
0528 static int tiadc_request_dma(struct platform_device *pdev,
0529                  struct tiadc_device *adc_dev)
0530 {
0531     struct tiadc_dma    *dma = &adc_dev->dma;
0532     dma_cap_mask_t      mask;
0533 
0534     /* Default slave configuration parameters */
0535     dma->conf.direction = DMA_DEV_TO_MEM;
0536     dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0537     dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
0538 
0539     dma_cap_zero(mask);
0540     dma_cap_set(DMA_CYCLIC, mask);
0541 
0542     /* Get a channel for RX */
0543     dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
0544     if (IS_ERR(dma->chan)) {
0545         int ret = PTR_ERR(dma->chan);
0546 
0547         dma->chan = NULL;
0548         return ret;
0549     }
0550 
0551     /* RX buffer */
0552     dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
0553                       &dma->addr, GFP_KERNEL);
0554     if (!dma->buf)
0555         goto err;
0556 
0557     return 0;
0558 
0559 err:
0560     dma_release_channel(dma->chan);
0561     return -ENOMEM;
0562 }
0563 
0564 static int tiadc_parse_dt(struct platform_device *pdev,
0565               struct tiadc_device *adc_dev)
0566 {
0567     struct device_node *node = pdev->dev.of_node;
0568     struct property *prop;
0569     const __be32 *cur;
0570     int channels = 0;
0571     u32 val;
0572     int i;
0573 
0574     of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
0575         adc_dev->channel_line[channels] = val;
0576 
0577         /* Set Default values for optional DT parameters */
0578         adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
0579         adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
0580         adc_dev->step_avg[channels] = 16;
0581 
0582         channels++;
0583     }
0584 
0585     adc_dev->channels = channels;
0586 
0587     of_property_read_u32_array(node, "ti,chan-step-avg",
0588                    adc_dev->step_avg, channels);
0589     of_property_read_u32_array(node, "ti,chan-step-opendelay",
0590                    adc_dev->open_delay, channels);
0591     of_property_read_u32_array(node, "ti,chan-step-sampledelay",
0592                    adc_dev->sample_delay, channels);
0593 
0594     for (i = 0; i < adc_dev->channels; i++) {
0595         int chan;
0596 
0597         chan = adc_dev->channel_line[i];
0598 
0599         if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
0600             dev_warn(&pdev->dev,
0601                  "chan %d: wrong step avg, truncated to %ld\n",
0602                  chan, STEPCONFIG_AVG_16);
0603             adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
0604         }
0605 
0606         if (adc_dev->open_delay[i] > STEPCONFIG_MAX_OPENDLY) {
0607             dev_warn(&pdev->dev,
0608                  "chan %d: wrong open delay, truncated to 0x%lX\n",
0609                  chan, STEPCONFIG_MAX_OPENDLY);
0610             adc_dev->open_delay[i] = STEPCONFIG_MAX_OPENDLY;
0611         }
0612 
0613         if (adc_dev->sample_delay[i] > STEPCONFIG_MAX_SAMPLE) {
0614             dev_warn(&pdev->dev,
0615                  "chan %d: wrong sample delay, truncated to 0x%lX\n",
0616                  chan, STEPCONFIG_MAX_SAMPLE);
0617             adc_dev->sample_delay[i] = STEPCONFIG_MAX_SAMPLE;
0618         }
0619     }
0620 
0621     return 0;
0622 }
0623 
0624 static int tiadc_probe(struct platform_device *pdev)
0625 {
0626     struct iio_dev      *indio_dev;
0627     struct tiadc_device *adc_dev;
0628     struct device_node  *node = pdev->dev.of_node;
0629     int         err;
0630 
0631     if (!node) {
0632         dev_err(&pdev->dev, "Could not find valid DT data.\n");
0633         return -EINVAL;
0634     }
0635 
0636     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
0637     if (!indio_dev) {
0638         dev_err(&pdev->dev, "failed to allocate iio device\n");
0639         return -ENOMEM;
0640     }
0641     adc_dev = iio_priv(indio_dev);
0642 
0643     adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev);
0644     tiadc_parse_dt(pdev, adc_dev);
0645 
0646     indio_dev->name = dev_name(&pdev->dev);
0647     indio_dev->modes = INDIO_DIRECT_MODE;
0648     indio_dev->info = &tiadc_info;
0649 
0650     tiadc_step_config(indio_dev);
0651     tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
0652     mutex_init(&adc_dev->fifo1_lock);
0653 
0654     err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels);
0655     if (err < 0)
0656         return err;
0657 
0658     err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev,
0659                         &tiadc_worker_h,
0660                         &tiadc_irq_h,
0661                         adc_dev->mfd_tscadc->irq,
0662                         IRQF_SHARED,
0663                         &tiadc_buffer_setup_ops);
0664     if (err)
0665         return err;
0666 
0667     err = iio_device_register(indio_dev);
0668     if (err)
0669         return err;
0670 
0671     platform_set_drvdata(pdev, indio_dev);
0672 
0673     err = tiadc_request_dma(pdev, adc_dev);
0674     if (err && err == -EPROBE_DEFER)
0675         goto err_dma;
0676 
0677     return 0;
0678 
0679 err_dma:
0680     iio_device_unregister(indio_dev);
0681 
0682     return err;
0683 }
0684 
0685 static int tiadc_remove(struct platform_device *pdev)
0686 {
0687     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0688     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0689     struct tiadc_dma *dma = &adc_dev->dma;
0690     u32 step_en;
0691 
0692     if (dma->chan) {
0693         dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
0694                   dma->buf, dma->addr);
0695         dma_release_channel(dma->chan);
0696     }
0697     iio_device_unregister(indio_dev);
0698 
0699     step_en = get_adc_step_mask(adc_dev);
0700     am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en);
0701 
0702     return 0;
0703 }
0704 
0705 static int tiadc_suspend(struct device *dev)
0706 {
0707     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0708     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0709     unsigned int idle;
0710 
0711     idle = tiadc_readl(adc_dev, REG_CTRL);
0712     idle &= ~(CNTRLREG_SSENB);
0713     tiadc_writel(adc_dev, REG_CTRL, idle | CNTRLREG_POWERDOWN);
0714 
0715     return 0;
0716 }
0717 
0718 static int tiadc_resume(struct device *dev)
0719 {
0720     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0721     struct tiadc_device *adc_dev = iio_priv(indio_dev);
0722     unsigned int restore;
0723 
0724     /* Make sure ADC is powered up */
0725     restore = tiadc_readl(adc_dev, REG_CTRL);
0726     restore &= ~CNTRLREG_POWERDOWN;
0727     tiadc_writel(adc_dev, REG_CTRL, restore);
0728 
0729     tiadc_step_config(indio_dev);
0730     am335x_tsc_se_set_cache(adc_dev->mfd_tscadc,
0731                 adc_dev->buffer_en_ch_steps);
0732     return 0;
0733 }
0734 
0735 static DEFINE_SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
0736 
0737 static const struct of_device_id ti_adc_dt_ids[] = {
0738     { .compatible = "ti,am3359-adc", },
0739     { .compatible = "ti,am4372-adc", },
0740     { }
0741 };
0742 MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
0743 
0744 static struct platform_driver tiadc_driver = {
0745     .driver = {
0746         .name   = "TI-am335x-adc",
0747         .pm = pm_sleep_ptr(&tiadc_pm_ops),
0748         .of_match_table = ti_adc_dt_ids,
0749     },
0750     .probe  = tiadc_probe,
0751     .remove = tiadc_remove,
0752 };
0753 module_platform_driver(tiadc_driver);
0754 
0755 MODULE_DESCRIPTION("TI ADC controller driver");
0756 MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
0757 MODULE_LICENSE("GPL");
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